Struct W

pub struct W<U, REG> { /* private fields */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn addrfaulten(&mut self) -> ADDRFAULTEN_W<'_>

Bit 0 - Invalid Address Bus Fault Response Enable

pub fn clkdisfaulten(&mut self) -> CLKDISFAULTEN_W<'_>

Bit 1 - Clock-disabled Bus Fault Response Enable

pub fn pwrupondemand(&mut self) -> PWRUPONDEMAND_W<'_>

Bit 2 - Power Up on Demand During Wake Up

pub fn ifcreadclear(&mut self) -> IFCREADCLEAR_W<'_>

Bit 3 - IFC Read Clears IF

pub fn timeoutfaulten(&mut self) -> TIMEOUTFAULTEN_W<'_>

Bit 4 - Timeout Bus Fault Response Enable

impl W<u32, Reg<u32, _READCTRL>>

pub fn ifcdis(&mut self) -> IFCDIS_W<'_>

Bit 3 - Internal Flash Cache Disable

pub fn aidis(&mut self) -> AIDIS_W<'_>

Bit 4 - Automatic Invalidate Disable

pub fn iccdis(&mut self) -> ICCDIS_W<'_>

Bit 5 - Interrupt Context Cache Disable

pub fn prefetch(&mut self) -> PREFETCH_W<'_>

Bit 8 - Prefetch Mode

pub fn usehprot(&mut self) -> USEHPROT_W<'_>

Bit 9 - AHB_HPROT Mode

pub fn mode(&mut self) -> MODE_W<'_>

Bits 24:25 - Read Mode

pub fn scbtp(&mut self) -> SCBTP_W<'_>

Bit 28 - Suppress Conditional Branch Target Perfetch

impl W<u32, Reg<u32, _WRITECTRL>>

pub fn wren(&mut self) -> WREN_W<'_>

Bit 0 - Enable Write/Erase Controller

pub fn irqeraseabort(&mut self) -> IRQERASEABORT_W<'_>

Bit 1 - Abort Page Erase on Interrupt

pub fn rwwen(&mut self) -> RWWEN_W<'_>

Bit 5 - Read-While-Write Enable

impl W<u32, Reg<u32, _WRITECMD>>

pub fn laddrim(&mut self) -> LADDRIM_W<'_>

Bit 0 - Load MSC_ADDRB Into ADDR

pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>

Bit 1 - Erase Page

pub fn writeend(&mut self) -> WRITEEND_W<'_>

Bit 2 - End Write Mode

pub fn writeonce(&mut self) -> WRITEONCE_W<'_>

Bit 3 - Word Write-Once Trigger

pub fn writetrig(&mut self) -> WRITETRIG_W<'_>

Bit 4 - Word Write Sequence Trigger

pub fn eraseabort(&mut self) -> ERASEABORT_W<'_>

Bit 5 - Abort Erase Sequence

pub fn erasemain0(&mut self) -> ERASEMAIN0_W<'_>

Bit 8 - Mass Erase Region 0

pub fn erasemain1(&mut self) -> ERASEMAIN1_W<'_>

Bit 9 - Mass Erase Region 1

pub fn clearwdata(&mut self) -> CLEARWDATA_W<'_>

Bit 12 - Clear WDATA State

impl W<u32, Reg<u32, _ADDRB>>

pub fn addrb(&mut self) -> ADDRB_W<'_>

Bits 0:31 - Page Erase or Write Address Buffer

impl W<u32, Reg<u32, _WDATA>>

pub fn wdata(&mut self) -> WDATA_W<'_>

Bits 0:31 - Write Data

impl W<u32, Reg<u32, _IFS>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - Set ERASE Interrupt Flag

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - Set WRITE Interrupt Flag

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - Set CHOF Interrupt Flag

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - Set CMOF Interrupt Flag

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - Set PWRUPF Interrupt Flag

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - Set ICACHERR Interrupt Flag

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - Set WDATAOV Interrupt Flag

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - Set LVEWRITE Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - Clear ERASE Interrupt Flag

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - Clear WRITE Interrupt Flag

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - Clear CHOF Interrupt Flag

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - Clear CMOF Interrupt Flag

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - Clear PWRUPF Interrupt Flag

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - Clear ICACHERR Interrupt Flag

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - Clear WDATAOV Interrupt Flag

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - Clear LVEWRITE Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 0 - ERASE Interrupt Enable

pub fn write(&mut self) -> WRITE_W<'_>

Bit 1 - WRITE Interrupt Enable

pub fn chof(&mut self) -> CHOF_W<'_>

Bit 2 - CHOF Interrupt Enable

pub fn cmof(&mut self) -> CMOF_W<'_>

Bit 3 - CMOF Interrupt Enable

pub fn pwrupf(&mut self) -> PWRUPF_W<'_>

Bit 4 - PWRUPF Interrupt Enable

pub fn icacherr(&mut self) -> ICACHERR_W<'_>

Bit 5 - ICACHERR Interrupt Enable

pub fn wdataov(&mut self) -> WDATAOV_W<'_>

Bit 6 - WDATAOV Interrupt Enable

pub fn lvewrite(&mut self) -> LVEWRITE_W<'_>

Bit 8 - LVEWRITE Interrupt Enable

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock

impl W<u32, Reg<u32, _CACHECMD>>

pub fn invcache(&mut self) -> INVCACHE_W<'_>

Bit 0 - Invalidate Instruction Cache

pub fn startpc(&mut self) -> STARTPC_W<'_>

Bit 1 - Start Performance Counters

pub fn stoppc(&mut self) -> STOPPC_W<'_>

Bit 2 - Stop Performance Counters

impl W<u32, Reg<u32, _MASSLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Mass Erase Lock

impl W<u32, Reg<u32, _STARTUP>>

pub fn stdly0(&mut self) -> STDLY0_W<'_>

Bits 0:9 - Startup Delay 0

pub fn stdly1(&mut self) -> STDLY1_W<'_>

Bits 12:21 - Startup Delay 0

pub fn astwait(&mut self) -> ASTWAIT_W<'_>

Bit 24 - Active Startup Wait

pub fn stwsen(&mut self) -> STWSEN_W<'_>

Bit 25 - Startup Waitstates Enable

pub fn stwsaen(&mut self) -> STWSAEN_W<'_>

Bit 26 - Startup Waitstates Always Enable

pub fn stws(&mut self) -> STWS_W<'_>

Bits 28:30 - Startup Waitstates

impl W<u32, Reg<u32, _BANKSWITCHLOCK>>

pub fn bankswitchlockkey(&mut self) -> BANKSWITCHLOCKKEY_W<'_>

Bits 0:15 - Bank Switching Lock

impl W<u32, Reg<u32, _CMD>>

pub fn pwrup(&mut self) -> PWRUP_W<'_>

Bit 0 - Flash Power Up Command

pub fn switchingbank(&mut self) -> SWITCHINGBANK_W<'_>

Bit 1 - BANK SWITCHING COMMAND

impl W<u32, Reg<u32, _BOOTLOADERCTRL>>

pub fn blrdis(&mut self) -> BLRDIS_W<'_>

Bit 0 - Flash Bootloader Read Disable

pub fn blwdis(&mut self) -> BLWDIS_W<'_>

Bit 1 - Flash Bootloader Write/Erase Disable

impl W<u32, Reg<u32, _AAPUNLOCKCMD>>

pub fn unlockaap(&mut self) -> UNLOCKAAP_W<'_>

Bit 0 - Software Unlock AAP Command

impl W<u32, Reg<u32, _CACHECONFIG0>>

pub fn cachelplevel(&mut self) -> CACHELPLEVEL_W<'_>

Bits 0:1 - Instruction Cache Low-Power Level

impl W<u32, Reg<u32, _RAMCTRL>>

pub fn ramcacheen(&mut self) -> RAMCACHEEN_W<'_>

Bit 0 - RAM CACHE Enable

pub fn ram1cacheen(&mut self) -> RAM1CACHEEN_W<'_>

Bit 8 - RAM1 CACHE Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn em2block(&mut self) -> EM2BLOCK_W<'_>

Bit 1 - Energy Mode 2 Block

pub fn em2boddis(&mut self) -> EM2BODDIS_W<'_>

Bit 2 - Disable BOD in EM2

pub fn em01ld(&mut self) -> EM01LD_W<'_>

Bit 3 - Reserved for internal use. Do not change.

pub fn em23vscaleautowsen(&mut self) -> EM23VSCALEAUTOWSEN_W<'_>

Bit 4 - Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage

pub fn em23vscale(&mut self) -> EM23VSCALE_W<'_>

Bits 8:9 - EM23 Voltage Scale

pub fn em4hvscale(&mut self) -> EM4HVSCALE_W<'_>

Bits 16:17 - EM4H Voltage Scale

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _RAM0CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bits 0:3 - RAM0 Blockset Power-down

impl W<u32, Reg<u32, _CMD>>

pub fn em4unlatch(&mut self) -> EM4UNLATCH_W<'_>

Bit 0 - EM4 Unlatch

pub fn em01vscale0(&mut self) -> EM01VSCALE0_W<'_>

Bit 4 - EM01 Voltage Scale Command to Scale to Voltage Scale Level 0

pub fn em01vscale2(&mut self) -> EM01VSCALE2_W<'_>

Bit 6 - EM01 Voltage Scale Command to Scale to Voltage Scale Level 2

impl W<u32, Reg<u32, _EM4CTRL>>

pub fn em4state(&mut self) -> EM4STATE_W<'_>

Bit 0 - Energy Mode 4 State

pub fn retainlfrco(&mut self) -> RETAINLFRCO_W<'_>

Bit 1 - LFRCO Retain During EM4

pub fn retainlfxo(&mut self) -> RETAINLFXO_W<'_>

Bit 2 - LFXO Retain During EM4

pub fn retainulfrco(&mut self) -> RETAINULFRCO_W<'_>

Bit 3 - ULFRCO Retain During EM4S

pub fn em4ioretmode(&mut self) -> EM4IORETMODE_W<'_>

Bits 4:5 - EM4 IO Retention Disable

pub fn em4entry(&mut self) -> EM4ENTRY_W<'_>

Bits 16:17 - Energy Mode 4 Entry

impl W<u32, Reg<u32, _TEMPLIMITS>>

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bits 0:7 - Temperature Low Limit

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bits 8:15 - Temperature High Limit

pub fn em4wuen(&mut self) -> EM4WUEN_W<'_>

Bit 16 - Enable EM4 Wakeup Due to Low/high Temperature

impl W<u32, Reg<u32, _IFS>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - Set VMONAVDDFALL Interrupt Flag

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - Set VMONAVDDRISE Interrupt Flag

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - Set VMONALTAVDDFALL Interrupt Flag

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - Set VMONALTAVDDRISE Interrupt Flag

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - Set VMONDVDDFALL Interrupt Flag

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - Set VMONDVDDRISE Interrupt Flag

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - Set VMONIO0FALL Interrupt Flag

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - Set VMONIO0RISE Interrupt Flag

pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W<'_>

Bit 14 - Set VMONFVDDFALL Interrupt Flag

pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W<'_>

Bit 15 - Set VMONFVDDRISE Interrupt Flag

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - Set PFETOVERCURRENTLIMIT Interrupt Flag

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - Set NFETOVERCURRENTLIMIT Interrupt Flag

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - Set DCDCLPRUNNING Interrupt Flag

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - Set DCDCLNRUNNING Interrupt Flag

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - Set DCDCINBYPASS Interrupt Flag

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - Set EM23WAKEUP Interrupt Flag

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - Set VSCALEDONE Interrupt Flag

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - Set TEMP Interrupt Flag

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - Set TEMPLOW Interrupt Flag

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - Set TEMPHIGH Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - Clear VMONAVDDFALL Interrupt Flag

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - Clear VMONAVDDRISE Interrupt Flag

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - Clear VMONALTAVDDFALL Interrupt Flag

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - Clear VMONALTAVDDRISE Interrupt Flag

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - Clear VMONDVDDFALL Interrupt Flag

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - Clear VMONDVDDRISE Interrupt Flag

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - Clear VMONIO0FALL Interrupt Flag

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - Clear VMONIO0RISE Interrupt Flag

pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W<'_>

Bit 14 - Clear VMONFVDDFALL Interrupt Flag

pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W<'_>

Bit 15 - Clear VMONFVDDRISE Interrupt Flag

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - Clear PFETOVERCURRENTLIMIT Interrupt Flag

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - Clear NFETOVERCURRENTLIMIT Interrupt Flag

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - Clear DCDCLPRUNNING Interrupt Flag

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - Clear DCDCLNRUNNING Interrupt Flag

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - Clear DCDCINBYPASS Interrupt Flag

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - Clear EM23WAKEUP Interrupt Flag

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - Clear VSCALEDONE Interrupt Flag

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - Clear TEMP Interrupt Flag

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - Clear TEMPLOW Interrupt Flag

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - Clear TEMPHIGH Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn vmonavddfall(&mut self) -> VMONAVDDFALL_W<'_>

Bit 0 - VMONAVDDFALL Interrupt Enable

pub fn vmonavddrise(&mut self) -> VMONAVDDRISE_W<'_>

Bit 1 - VMONAVDDRISE Interrupt Enable

pub fn vmonaltavddfall(&mut self) -> VMONALTAVDDFALL_W<'_>

Bit 2 - VMONALTAVDDFALL Interrupt Enable

pub fn vmonaltavddrise(&mut self) -> VMONALTAVDDRISE_W<'_>

Bit 3 - VMONALTAVDDRISE Interrupt Enable

pub fn vmondvddfall(&mut self) -> VMONDVDDFALL_W<'_>

Bit 4 - VMONDVDDFALL Interrupt Enable

pub fn vmondvddrise(&mut self) -> VMONDVDDRISE_W<'_>

Bit 5 - VMONDVDDRISE Interrupt Enable

pub fn vmonio0fall(&mut self) -> VMONIO0FALL_W<'_>

Bit 6 - VMONIO0FALL Interrupt Enable

pub fn vmonio0rise(&mut self) -> VMONIO0RISE_W<'_>

Bit 7 - VMONIO0RISE Interrupt Enable

pub fn vmonfvddfall(&mut self) -> VMONFVDDFALL_W<'_>

Bit 14 - VMONFVDDFALL Interrupt Enable

pub fn vmonfvddrise(&mut self) -> VMONFVDDRISE_W<'_>

Bit 15 - VMONFVDDRISE Interrupt Enable

pub fn pfetovercurrentlimit(&mut self) -> PFETOVERCURRENTLIMIT_W<'_>

Bit 16 - PFETOVERCURRENTLIMIT Interrupt Enable

pub fn nfetovercurrentlimit(&mut self) -> NFETOVERCURRENTLIMIT_W<'_>

Bit 17 - NFETOVERCURRENTLIMIT Interrupt Enable

pub fn dcdclprunning(&mut self) -> DCDCLPRUNNING_W<'_>

Bit 18 - DCDCLPRUNNING Interrupt Enable

pub fn dcdclnrunning(&mut self) -> DCDCLNRUNNING_W<'_>

Bit 19 - DCDCLNRUNNING Interrupt Enable

pub fn dcdcinbypass(&mut self) -> DCDCINBYPASS_W<'_>

Bit 20 - DCDCINBYPASS Interrupt Enable

pub fn em23wakeup(&mut self) -> EM23WAKEUP_W<'_>

Bit 24 - EM23WAKEUP Interrupt Enable

pub fn vscaledone(&mut self) -> VSCALEDONE_W<'_>

Bit 25 - VSCALEDONE Interrupt Enable

pub fn temp(&mut self) -> TEMP_W<'_>

Bit 29 - TEMP Interrupt Enable

pub fn templow(&mut self) -> TEMPLOW_W<'_>

Bit 30 - TEMPLOW Interrupt Enable

pub fn temphigh(&mut self) -> TEMPHIGH_W<'_>

Bit 31 - TEMPHIGH Interrupt Enable

impl W<u32, Reg<u32, _PWRLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Regulator and Supply Configuration Lock Key

impl W<u32, Reg<u32, _PWRCFG>>

pub fn pwrcfg(&mut self) -> PWRCFG_W<'_>

Bits 0:3 - Power Configuration

impl W<u32, Reg<u32, _PWRCTRL>>

pub fn anasw(&mut self) -> ANASW_W<'_>

Bit 5 - Analog Switch Selection

pub fn regpwrsel(&mut self) -> REGPWRSEL_W<'_>

Bit 10 - This Field Selects the Input Supply Pin for the Digital LDO

pub fn dvddboddis(&mut self) -> DVDDBODDIS_W<'_>

Bit 12 - DVDD BOD Disable

impl W<u32, Reg<u32, _DCDCCTRL>>

pub fn dcdcmode(&mut self) -> DCDCMODE_W<'_>

Bits 0:1 - Regulator Mode

pub fn dcdcmodeem23(&mut self) -> DCDCMODEEM23_W<'_>

Bit 4 - DCDC Mode EM23

pub fn dcdcmodeem4(&mut self) -> DCDCMODEEM4_W<'_>

Bit 5 - DCDC Mode EM4H

impl W<u32, Reg<u32, _DCDCMISCCTRL>>

pub fn lnforceccm(&mut self) -> LNFORCECCM_W<'_>

Bit 0 - Force DCDC Into CCM Mode in Low Noise Operation

pub fn lpcmphysdis(&mut self) -> LPCMPHYSDIS_W<'_>

Bit 1 - Disable LP Mode Hysteresis in the State Machine Control

pub fn lpcmphyshi(&mut self) -> LPCMPHYSHI_W<'_>

Bit 2 - Comparator Threshold on the High Side

pub fn lnforceccmimm(&mut self) -> LNFORCECCMIMM_W<'_>

Bit 5 - Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM

pub fn pfetcnt(&mut self) -> PFETCNT_W<'_>

Bits 8:11 - PFET Switch Number Selection

pub fn nfetcnt(&mut self) -> NFETCNT_W<'_>

Bits 12:15 - NFET Switch Number Selection

pub fn byplimsel(&mut self) -> BYPLIMSEL_W<'_>

Bits 16:19 - Current Limit in Bypass Mode

pub fn lpclimilimsel(&mut self) -> LPCLIMILIMSEL_W<'_>

Bits 20:22 - Current Limit Level Selection for Current Limiter in LP Mode

pub fn lnclimilimsel(&mut self) -> LNCLIMILIMSEL_W<'_>

Bits 24:26 - Current Limit Level Selection for Current Limiter in LN Mode

pub fn lpcmpbiasem234h(&mut self) -> LPCMPBIASEM234H_W<'_>

Bits 28:29 - LP Mode Comparator Bias Selection for EM23 or EM4H

impl W<u32, Reg<u32, _DCDCZDETCTRL>>

pub fn zdetilimsel(&mut self) -> ZDETILIMSEL_W<'_>

Bits 4:6 - Reverse Current Limit Level Selection for Zero Detector

pub fn zdetblankdly(&mut self) -> ZDETBLANKDLY_W<'_>

Bits 8:9 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _DCDCCLIMCTRL>>

pub fn climblankdly(&mut self) -> CLIMBLANKDLY_W<'_>

Bits 8:9 - Reserved for internal use. Do not change.

pub fn byplimen(&mut self) -> BYPLIMEN_W<'_>

Bit 13 - Bypass Current Limit Enable

impl W<u32, Reg<u32, _DCDCLNCOMPCTRL>>

pub fn compenr1(&mut self) -> COMPENR1_W<'_>

Bits 0:2 - Low Noise Mode Compensator R1 Trim Value

pub fn compenr2(&mut self) -> COMPENR2_W<'_>

Bits 4:8 - Low Noise Mode Compensator R2 Trim Value

pub fn compenr3(&mut self) -> COMPENR3_W<'_>

Bits 12:15 - Low Noise Mode Compensator R3 Trim Value

pub fn compenc1(&mut self) -> COMPENC1_W<'_>

Bits 20:21 - Low Noise Mode Compensator C1 Trim Value

pub fn compenc2(&mut self) -> COMPENC2_W<'_>

Bits 24:26 - Low Noise Mode Compensator C2 Trim Value

pub fn compenc3(&mut self) -> COMPENC3_W<'_>

Bits 28:31 - Low Noise Mode Compensator C3 Trim Value

impl W<u32, Reg<u32, _DCDCLNVCTRL>>

pub fn lnatt(&mut self) -> LNATT_W<'_>

Bit 1 - Low Noise Mode Feedback Attenuation

pub fn lnvref(&mut self) -> LNVREF_W<'_>

Bits 8:14 - Low Noise Mode VREF Trim

impl W<u32, Reg<u32, _DCDCLPVCTRL>>

pub fn lpatt(&mut self) -> LPATT_W<'_>

Bit 0 - Low Power Feedback Attenuation

pub fn lpvref(&mut self) -> LPVREF_W<'_>

Bits 1:8 - LP Mode Reference Selection for EM23 and EM4H

impl W<u32, Reg<u32, _DCDCLPCTRL>>

pub fn lpcmphysselem234h(&mut self) -> LPCMPHYSSELEM234H_W<'_>

Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H

pub fn lpvrefdutyen(&mut self) -> LPVREFDUTYEN_W<'_>

Bit 24 - LP Mode Duty Cycling Enable

pub fn lpblank(&mut self) -> LPBLANK_W<'_>

Bits 25:26 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _DCDCLNFREQCTRL>>

pub fn rcoband(&mut self) -> RCOBAND_W<'_>

Bits 0:2 - LN Mode RCO Frequency Band Selection

pub fn rcotrim(&mut self) -> RCOTRIM_W<'_>

Bits 24:28 - Reserved for internal use. Do not change.

impl W<u32, Reg<u32, _VMONAVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn fallthresfine(&mut self) -> FALLTHRESFINE_W<'_>

Bits 8:11 - Falling Threshold Fine Adjust

pub fn fallthrescoarse(&mut self) -> FALLTHRESCOARSE_W<'_>

Bits 12:15 - Falling Threshold Coarse Adjust

pub fn risethresfine(&mut self) -> RISETHRESFINE_W<'_>

Bits 16:19 - Rising Threshold Fine Adjust

pub fn risethrescoarse(&mut self) -> RISETHRESCOARSE_W<'_>

Bits 20:23 - Rising Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONALTAVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONDVDDCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _VMONIO0CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

pub fn risewu(&mut self) -> RISEWU_W<'_>

Bit 2 - Rise Wakeup

pub fn fallwu(&mut self) -> FALLWU_W<'_>

Bit 3 - Fall Wakeup

pub fn retdis(&mut self) -> RETDIS_W<'_>

Bit 4 - EM4 IO0 Retention Disable

pub fn thresfine(&mut self) -> THRESFINE_W<'_>

Bits 8:11 - Threshold Fine Adjust

pub fn threscoarse(&mut self) -> THRESCOARSE_W<'_>

Bits 12:15 - Threshold Coarse Adjust

impl W<u32, Reg<u32, _RAM1CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bits 0:1 - RAM1 Blockset Power-down

impl W<u32, Reg<u32, _RAM2CTRL>>

pub fn rampowerdown(&mut self) -> RAMPOWERDOWN_W<'_>

Bit 0 - RAM2 Blockset Power-down

impl W<u32, Reg<u32, _DCDCLPEM01CFG>>

pub fn lpcmpbiasem01(&mut self) -> LPCMPBIASEM01_W<'_>

Bits 8:9 - LP Mode Comparator Bias Selection for EM01

pub fn lpcmphysselem01(&mut self) -> LPCMPHYSSELEM01_W<'_>

Bits 12:15 - LP Mode Hysteresis Selection for EM01

impl W<u32, Reg<u32, _EM23PERNORETAINCMD>>

pub fn acmp0unlock(&mut self) -> ACMP0UNLOCK_W<'_>

Bit 0 - Clears Status Bit of ACMP0 and Unlocks Access to It

pub fn acmp1unlock(&mut self) -> ACMP1UNLOCK_W<'_>

Bit 1 - Clears Status Bit of ACMP1 and Unlocks Access to It

pub fn pcnt0unlock(&mut self) -> PCNT0UNLOCK_W<'_>

Bit 2 - Clears Status Bit of PCNT0 and Unlocks Access to It

pub fn pcnt1unlock(&mut self) -> PCNT1UNLOCK_W<'_>

Bit 3 - Clears Status Bit of PCNT1 and Unlocks Access to It

pub fn pcnt2unlock(&mut self) -> PCNT2UNLOCK_W<'_>

Bit 4 - Clears Status Bit of PCNT2 and Unlocks Access to It

pub fn i2c0unlock(&mut self) -> I2C0UNLOCK_W<'_>

Bit 5 - Clears Status Bit of I2C0 and Unlocks Access to It

pub fn i2c1unlock(&mut self) -> I2C1UNLOCK_W<'_>

Bit 6 - Clears Status Bit of I2C1 and Unlocks Access to It

pub fn dac0unlock(&mut self) -> DAC0UNLOCK_W<'_>

Bit 7 - Clears Status Bit of DAC0 and Unlocks Access to It

pub fn idac0unlock(&mut self) -> IDAC0UNLOCK_W<'_>

Bit 8 - Clears Status Bit of IDAC0 and Unlocks Access to It

pub fn adc0unlock(&mut self) -> ADC0UNLOCK_W<'_>

Bit 9 - Clears Status Bit of ADC0 and Unlocks Access to It

pub fn letimer0unlock(&mut self) -> LETIMER0UNLOCK_W<'_>

Bit 10 - Clears Status Bit of LETIMER0 and Unlocks Access to It

pub fn wdog0unlock(&mut self) -> WDOG0UNLOCK_W<'_>

Bit 11 - Clears Status Bit of WDOG0 and Unlocks Access to It

pub fn wdog1unlock(&mut self) -> WDOG1UNLOCK_W<'_>

Bit 12 - Clears Status Bit of WDOG1 and Unlocks Access to It

pub fn lesense0unlock(&mut self) -> LESENSE0UNLOCK_W<'_>

Bit 13 - Clears Status Bit of LESENSE0 and Unlocks Access to It

pub fn csenunlock(&mut self) -> CSENUNLOCK_W<'_>

Bit 14 - Clears Status Bit of CSEN and Unlocks Access to It

pub fn leuart0unlock(&mut self) -> LEUART0UNLOCK_W<'_>

Bit 15 - Clears Status Bit of LEUART0 and Unlocks Access to It

impl W<u32, Reg<u32, _EM23PERNORETAINCTRL>>

pub fn acmp0dis(&mut self) -> ACMP0DIS_W<'_>

Bit 0 - Allow Power Down of ACMP0 During EM23

pub fn acmp1dis(&mut self) -> ACMP1DIS_W<'_>

Bit 1 - Allow Power Down of ACMP1 During EM23

pub fn pcnt0dis(&mut self) -> PCNT0DIS_W<'_>

Bit 2 - Allow Power Down of PCNT0 During EM23

pub fn pcnt1dis(&mut self) -> PCNT1DIS_W<'_>

Bit 3 - Allow Power Down of PCNT1 During EM23

pub fn pcnt2dis(&mut self) -> PCNT2DIS_W<'_>

Bit 4 - Allow Power Down of PCNT2 During EM23

pub fn i2c0dis(&mut self) -> I2C0DIS_W<'_>

Bit 5 - Allow Power Down of I2C0 During EM23

pub fn i2c1dis(&mut self) -> I2C1DIS_W<'_>

Bit 6 - Allow Power Down of I2C1 During EM23

pub fn vdac0dis(&mut self) -> VDAC0DIS_W<'_>

Bit 7 - Allow Power Down of DAC0 During EM23

pub fn idac0dis(&mut self) -> IDAC0DIS_W<'_>

Bit 8 - Allow Power Down of IDAC0 During EM23

pub fn adc0dis(&mut self) -> ADC0DIS_W<'_>

Bit 9 - Allow Power Down of ADC0 During EM23

pub fn letimer0dis(&mut self) -> LETIMER0DIS_W<'_>

Bit 10 - Allow Power Down of LETIMER0 During EM23

pub fn wdog0dis(&mut self) -> WDOG0DIS_W<'_>

Bit 11 - Allow Power Down of WDOG0 During EM23

pub fn wdog1dis(&mut self) -> WDOG1DIS_W<'_>

Bit 12 - Allow Power Down of WDOG1 During EM23

pub fn lesense0dis(&mut self) -> LESENSE0DIS_W<'_>

Bit 13 - Allow Power Down of LESENSE0 During EM23

pub fn csendis(&mut self) -> CSENDIS_W<'_>

Bit 14 - Allow Power Down of CSEN During EM23

pub fn leuart0dis(&mut self) -> LEUART0DIS_W<'_>

Bit 15 - Allow Power Down of LEUART0 During EM23

impl W<u32, Reg<u32, _CTRL>>

pub fn wdogrmode(&mut self) -> WDOGRMODE_W<'_>

Bits 0:2 - WDOG Reset Mode

pub fn lockuprmode(&mut self) -> LOCKUPRMODE_W<'_>

Bits 4:6 - Core LOCKUP Reset Mode

pub fn sysrmode(&mut self) -> SYSRMODE_W<'_>

Bits 8:10 - Core Sysreset Reset Mode

pub fn pinrmode(&mut self) -> PINRMODE_W<'_>

Bits 12:14 - PIN Reset Mode

pub fn resetstate(&mut self) -> RESETSTATE_W<'_>

Bits 24:25 - System Software Reset State

impl W<u32, Reg<u32, _CMD>>

pub fn rcclr(&mut self) -> RCCLR_W<'_>

Bit 0 - Reset Cause Clear

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn clkoutsel0(&mut self) -> CLKOUTSEL0_W<'_>

Bits 0:3 - Clock Output Select 0

pub fn clkoutsel1(&mut self) -> CLKOUTSEL1_W<'_>

Bits 5:8 - Clock Output Select 1

pub fn wshfle(&mut self) -> WSHFLE_W<'_>

Bit 16 - Wait State for High-Frequency LE Interface

pub fn hfperclken(&mut self) -> HFPERCLKEN_W<'_>

Bit 20 - HFPERCLK Enable

impl W<u32, Reg<u32, _HFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - HFRCO Tuning Value

pub fn finetuning(&mut self) -> FINETUNING_W<'_>

Bits 8:13 - HFRCO Fine Tuning Value

pub fn freqrange(&mut self) -> FREQRANGE_W<'_>

Bits 16:20 - HFRCO Frequency Range

pub fn cmpbias(&mut self) -> CMPBIAS_W<'_>

Bits 21:23 - HFRCO Comparator Bias Current

pub fn ldohp(&mut self) -> LDOHP_W<'_>

Bit 24 - HFRCO LDO High Power Mode

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 25:26 - Locally Divide HFRCO Clock Output

pub fn finetuningen(&mut self) -> FINETUNINGEN_W<'_>

Bit 27 - Enable Reference for Fine Tuning

pub fn vreftc(&mut self) -> VREFTC_W<'_>

Bits 28:31 - HFRCO Temperature Coefficient Trim on Comparator Reference

impl W<u32, Reg<u32, _AUXHFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - AUXHFRCO Tuning Value

pub fn finetuning(&mut self) -> FINETUNING_W<'_>

Bits 8:13 - AUXHFRCO Fine Tuning Value

pub fn freqrange(&mut self) -> FREQRANGE_W<'_>

Bits 16:20 - AUXHFRCO Frequency Range

pub fn cmpbias(&mut self) -> CMPBIAS_W<'_>

Bits 21:23 - AUXHFRCO Comparator Bias Current

pub fn ldohp(&mut self) -> LDOHP_W<'_>

Bit 24 - AUXHFRCO LDO High Power Mode

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 25:26 - Locally Divide AUXHFRCO Clock Output

pub fn finetuningen(&mut self) -> FINETUNINGEN_W<'_>

Bit 27 - Enable Reference for Fine Tuning

pub fn vreftc(&mut self) -> VREFTC_W<'_>

Bits 28:31 - AUXHFRCO Temperature Coefficient Trim on Comparator Reference

impl W<u32, Reg<u32, _LFRCOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:8 - LFRCO Tuning Value

pub fn envref(&mut self) -> ENVREF_W<'_>

Bit 16 - Enable Duty Cycling of Vref

pub fn enchop(&mut self) -> ENCHOP_W<'_>

Bit 17 - Enable Comparator Chopping

pub fn endem(&mut self) -> ENDEM_W<'_>

Bit 18 - Enable Dynamic Element Matching

pub fn vrefupdate(&mut self) -> VREFUPDATE_W<'_>

Bits 20:21 - Control Vref Update Rate

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 24:25 - LFRCO Timeout

pub fn gmccurtune(&mut self) -> GMCCURTUNE_W<'_>

Bits 28:31 - Tuning of Gmc Current

impl W<u32, Reg<u32, _HFXOCTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - HFXO Mode

pub fn peakdetshuntoptmode(&mut self) -> PEAKDETSHUNTOPTMODE_W<'_>

Bits 4:5 - HFXO Automatic Peak Detection and Shunt Current Optimization Mode

pub fn lowpower(&mut self) -> LOWPOWER_W<'_>

Bit 8 - Low Power Mode Control

pub fn xti2gnd(&mut self) -> XTI2GND_W<'_>

Bit 9 - Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off

pub fn xto2gnd(&mut self) -> XTO2GND_W<'_>

Bit 10 - Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off

pub fn lftimeout(&mut self) -> LFTIMEOUT_W<'_>

Bits 24:26 - HFXO Low Frequency Timeout

pub fn autostartem0em1(&mut self) -> AUTOSTARTEM0EM1_W<'_>

Bit 28 - Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3

pub fn autostartselem0em1(&mut self) -> AUTOSTARTSELEM0EM1_W<'_>

Bit 29 - Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3

impl W<u32, Reg<u32, _HFXOSTARTUPCTRL>>

pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<'_>

Bits 0:6 - Sets the Startup Oscillator Core Bias Current

pub fn ctune(&mut self) -> CTUNE_W<'_>

Bits 11:19 - Sets Oscillator Tuning Capacitance

impl W<u32, Reg<u32, _HFXOSTEADYSTATECTRL>>

pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W<'_>

Bits 0:6 - Sets the Steady State Oscillator Core Bias Current.

pub fn regish(&mut self) -> REGISH_W<'_>

Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)

pub fn ctune(&mut self) -> CTUNE_W<'_>

Bits 11:19 - Sets Oscillator Tuning Capacitance

pub fn regselilow(&mut self) -> REGSELILOW_W<'_>

Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal

pub fn peakdeten(&mut self) -> PEAKDETEN_W<'_>

Bit 26 - Enables Oscillator Peak Detectors

pub fn regishupper(&mut self) -> REGISHUPPER_W<'_>

Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA

impl W<u32, Reg<u32, _HFXOTIMEOUTCTRL>>

pub fn startuptimeout(&mut self) -> STARTUPTIMEOUT_W<'_>

Bits 0:3 - Wait Duration in HFXO Startup Enable Wait State

pub fn steadytimeout(&mut self) -> STEADYTIMEOUT_W<'_>

Bits 4:7 - Wait Duration in HFXO Startup Steady Wait State

pub fn peakdettimeout(&mut self) -> PEAKDETTIMEOUT_W<'_>

Bits 12:15 - Wait Duration in HFXO Peak Detection Wait State

pub fn shuntopttimeout(&mut self) -> SHUNTOPTTIMEOUT_W<'_>

Bits 16:19 - Wait Duration in HFXO Shunt Current Optimization Wait State

impl W<u32, Reg<u32, _LFXOCTRL>>

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 0:6 - LFXO Internal Capacitor Array Tuning Value

pub fn mode(&mut self) -> MODE_W<'_>

Bits 8:9 - LFXO Mode

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 11:12 - LFXO Startup Gain

pub fn highampl(&mut self) -> HIGHAMPL_W<'_>

Bit 14 - LFXO High XTAL Oscillation Amplitude Enable

pub fn agc(&mut self) -> AGC_W<'_>

Bit 15 - LFXO AGC Enable

pub fn cur(&mut self) -> CUR_W<'_>

Bits 16:17 - LFXO Current Trim

pub fn bufcur(&mut self) -> BUFCUR_W<'_>

Bit 20 - LFXO Buffer Bias Current

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 24:26 - LFXO Timeout

impl W<u32, Reg<u32, _DPLLCTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - Operating Mode Control

pub fn edgesel(&mut self) -> EDGESEL_W<'_>

Bit 1 - Reference Edge Select

pub fn autorecover(&mut self) -> AUTORECOVER_W<'_>

Bit 2 - Automatic Recovery Ctrl

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 3:4 - Reference Clock Selection Control

impl W<u32, Reg<u32, _DPLLCTRL1>>

pub fn m(&mut self) -> M_W<'_>

Bits 0:11 - Factor M

pub fn n(&mut self) -> N_W<'_>

Bits 16:27 - Factor N

impl W<u32, Reg<u32, _CALCTRL>>

pub fn upsel(&mut self) -> UPSEL_W<'_>

Bits 0:2 - Calibration Up-counter Select

pub fn downsel(&mut self) -> DOWNSEL_W<'_>

Bits 4:6 - Calibration Down-counter Select

pub fn cont(&mut self) -> CONT_W<'_>

Bit 8 - Continuous Calibration

pub fn prsupsel(&mut self) -> PRSUPSEL_W<'_>

Bits 16:19 - PRS Select for PRS Input When Selected in UPSEL

pub fn prsdownsel(&mut self) -> PRSDOWNSEL_W<'_>

Bits 24:27 - PRS Select for PRS Input When Selected in DOWNSEL

impl W<u32, Reg<u32, _CALCNT>>

pub fn calcnt(&mut self) -> CALCNT_W<'_>

Bits 0:19 - Calibration Counter

impl W<u32, Reg<u32, _OSCENCMD>>

pub fn hfrcoen(&mut self) -> HFRCOEN_W<'_>

Bit 0 - HFRCO Enable

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 1 - HFRCO Disable

pub fn hfxoen(&mut self) -> HFXOEN_W<'_>

Bit 2 - HFXO Enable

pub fn hfxodis(&mut self) -> HFXODIS_W<'_>

Bit 3 - HFXO Disable

pub fn auxhfrcoen(&mut self) -> AUXHFRCOEN_W<'_>

Bit 4 - AUXHFRCO Enable

pub fn auxhfrcodis(&mut self) -> AUXHFRCODIS_W<'_>

Bit 5 - AUXHFRCO Disable

pub fn lfrcoen(&mut self) -> LFRCOEN_W<'_>

Bit 6 - LFRCO Enable

pub fn lfrcodis(&mut self) -> LFRCODIS_W<'_>

Bit 7 - LFRCO Disable

pub fn lfxoen(&mut self) -> LFXOEN_W<'_>

Bit 8 - LFXO Enable

pub fn lfxodis(&mut self) -> LFXODIS_W<'_>

Bit 9 - LFXO Disable

pub fn dpllen(&mut self) -> DPLLEN_W<'_>

Bit 12 - DPLL Enable

pub fn dplldis(&mut self) -> DPLLDIS_W<'_>

Bit 13 - DPLL Disable

impl W<u32, Reg<u32, _CMD>>

pub fn calstart(&mut self) -> CALSTART_W<'_>

Bit 0 - Calibration Start

pub fn calstop(&mut self) -> CALSTOP_W<'_>

Bit 1 - Calibration Stop

pub fn hfxopeakdetstart(&mut self) -> HFXOPEAKDETSTART_W<'_>

Bit 4 - HFXO Peak Detection Start

pub fn hfxoshuntoptstart(&mut self) -> HFXOSHUNTOPTSTART_W<'_>

Bit 5 - HFXO Shunt Current Optimization Start

impl W<u32, Reg<u32, _DBGCLKSEL>>

pub fn dbg(&mut self) -> DBG_W<'_>

Bit 0 - Debug Trace Clock

impl W<u32, Reg<u32, _HFCLKSEL>>

pub fn hf(&mut self) -> HF_W<'_>

Bits 0:2 - HFCLK Select

impl W<u32, Reg<u32, _LFACLKSEL>>

pub fn lfa(&mut self) -> LFA_W<'_>

Bits 0:2 - Clock Select for LFA

impl W<u32, Reg<u32, _LFBCLKSEL>>

pub fn lfb(&mut self) -> LFB_W<'_>

Bits 0:2 - Clock Select for LFB

impl W<u32, Reg<u32, _LFECLKSEL>>

pub fn lfe(&mut self) -> LFE_W<'_>

Bits 0:2 - Clock Select for LFE

impl W<u32, Reg<u32, _IFS>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - Set HFRCORDY Interrupt Flag

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - Set HFXORDY Interrupt Flag

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - Set LFRCORDY Interrupt Flag

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - Set LFXORDY Interrupt Flag

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - Set AUXHFRCORDY Interrupt Flag

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - Set CALRDY Interrupt Flag

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - Set CALOF Interrupt Flag

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - Set HFXODISERR Interrupt Flag

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - Set HFXOAUTOSW Interrupt Flag

pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W<'_>

Bit 10 - Set HFXOPEAKDETERR Interrupt Flag

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - Set HFXOPEAKDETRDY Interrupt Flag

pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W<'_>

Bit 12 - Set HFXOSHUNTOPTRDY Interrupt Flag

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - Set HFRCODIS Interrupt Flag

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - Set LFTIMEOUTERR Interrupt Flag

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - Set DPLLRDY Interrupt Flag

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - Set DPLLLOCKFAILLOW Interrupt Flag

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - Set DPLLLOCKFAILHIGH Interrupt Flag

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - Set CMUERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - Clear HFRCORDY Interrupt Flag

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - Clear HFXORDY Interrupt Flag

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - Clear LFRCORDY Interrupt Flag

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - Clear LFXORDY Interrupt Flag

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - Clear AUXHFRCORDY Interrupt Flag

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - Clear CALRDY Interrupt Flag

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - Clear CALOF Interrupt Flag

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - Clear HFXODISERR Interrupt Flag

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - Clear HFXOAUTOSW Interrupt Flag

pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W<'_>

Bit 10 - Clear HFXOPEAKDETERR Interrupt Flag

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - Clear HFXOPEAKDETRDY Interrupt Flag

pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W<'_>

Bit 12 - Clear HFXOSHUNTOPTRDY Interrupt Flag

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - Clear HFRCODIS Interrupt Flag

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - Clear LFTIMEOUTERR Interrupt Flag

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - Clear DPLLRDY Interrupt Flag

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - Clear DPLLLOCKFAILLOW Interrupt Flag

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - Clear DPLLLOCKFAILHIGH Interrupt Flag

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - Clear CMUERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn hfrcordy(&mut self) -> HFRCORDY_W<'_>

Bit 0 - HFRCORDY Interrupt Enable

pub fn hfxordy(&mut self) -> HFXORDY_W<'_>

Bit 1 - HFXORDY Interrupt Enable

pub fn lfrcordy(&mut self) -> LFRCORDY_W<'_>

Bit 2 - LFRCORDY Interrupt Enable

pub fn lfxordy(&mut self) -> LFXORDY_W<'_>

Bit 3 - LFXORDY Interrupt Enable

pub fn auxhfrcordy(&mut self) -> AUXHFRCORDY_W<'_>

Bit 4 - AUXHFRCORDY Interrupt Enable

pub fn calrdy(&mut self) -> CALRDY_W<'_>

Bit 5 - CALRDY Interrupt Enable

pub fn calof(&mut self) -> CALOF_W<'_>

Bit 6 - CALOF Interrupt Enable

pub fn hfxodiserr(&mut self) -> HFXODISERR_W<'_>

Bit 8 - HFXODISERR Interrupt Enable

pub fn hfxoautosw(&mut self) -> HFXOAUTOSW_W<'_>

Bit 9 - HFXOAUTOSW Interrupt Enable

pub fn hfxopeakdeterr(&mut self) -> HFXOPEAKDETERR_W<'_>

Bit 10 - HFXOPEAKDETERR Interrupt Enable

pub fn hfxopeakdetrdy(&mut self) -> HFXOPEAKDETRDY_W<'_>

Bit 11 - HFXOPEAKDETRDY Interrupt Enable

pub fn hfxoshuntoptrdy(&mut self) -> HFXOSHUNTOPTRDY_W<'_>

Bit 12 - HFXOSHUNTOPTRDY Interrupt Enable

pub fn hfrcodis(&mut self) -> HFRCODIS_W<'_>

Bit 13 - HFRCODIS Interrupt Enable

pub fn lftimeouterr(&mut self) -> LFTIMEOUTERR_W<'_>

Bit 14 - LFTIMEOUTERR Interrupt Enable

pub fn dpllrdy(&mut self) -> DPLLRDY_W<'_>

Bit 15 - DPLLRDY Interrupt Enable

pub fn dplllockfaillow(&mut self) -> DPLLLOCKFAILLOW_W<'_>

Bit 16 - DPLLLOCKFAILLOW Interrupt Enable

pub fn dplllockfailhigh(&mut self) -> DPLLLOCKFAILHIGH_W<'_>

Bit 17 - DPLLLOCKFAILHIGH Interrupt Enable

pub fn cmuerr(&mut self) -> CMUERR_W<'_>

Bit 31 - CMUERR Interrupt Enable

impl W<u32, Reg<u32, _HFBUSCLKEN0>>

pub fn crypto0(&mut self) -> CRYPTO0_W<'_>

Bit 0 - Advanced Encryption Standard Accelerator 0 Clock Enable

pub fn crypto1(&mut self) -> CRYPTO1_W<'_>

Bit 1 - Advanced Encryption Standard Accelerator 1 Clock Enable

pub fn le(&mut self) -> LE_W<'_>

Bit 2 - Low Energy Peripheral Interface Clock Enable

pub fn gpio(&mut self) -> GPIO_W<'_>

Bit 3 - General purpose Input/Output Clock Enable

pub fn prs(&mut self) -> PRS_W<'_>

Bit 4 - Peripheral Reflex System Clock Enable

pub fn ldma(&mut self) -> LDMA_W<'_>

Bit 5 - Linked Direct Memory Access Controller Clock Enable

pub fn gpcrc(&mut self) -> GPCRC_W<'_>

Bit 6 - General Purpose CRC Clock Enable

impl W<u32, Reg<u32, _HFPERCLKEN0>>

pub fn timer0(&mut self) -> TIMER0_W<'_>

Bit 0 - Timer 0 Clock Enable

pub fn timer1(&mut self) -> TIMER1_W<'_>

Bit 1 - Timer 1 Clock Enable

pub fn wtimer0(&mut self) -> WTIMER0_W<'_>

Bit 2 - Wide Timer 0 Clock Enable

pub fn wtimer1(&mut self) -> WTIMER1_W<'_>

Bit 3 - Wide Timer 1 Clock Enable

pub fn usart0(&mut self) -> USART0_W<'_>

Bit 4 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

pub fn usart1(&mut self) -> USART1_W<'_>

Bit 5 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

pub fn usart2(&mut self) -> USART2_W<'_>

Bit 6 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable

pub fn usart3(&mut self) -> USART3_W<'_>

Bit 7 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 8 - I2C 0 Clock Enable

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 9 - I2C 1 Clock Enable

pub fn acmp0(&mut self) -> ACMP0_W<'_>

Bit 10 - Analog Comparator 0 Clock Enable

pub fn acmp1(&mut self) -> ACMP1_W<'_>

Bit 11 - Analog Comparator 1 Clock Enable

pub fn cryotimer(&mut self) -> CRYOTIMER_W<'_>

Bit 12 - CRYOTIMER Clock Enable

pub fn adc0(&mut self) -> ADC0_W<'_>

Bit 13 - Analog to Digital Converter 0 Clock Enable

pub fn idac0(&mut self) -> IDAC0_W<'_>

Bit 14 - Current Digital to Analog Converter 0 Clock Enable

pub fn vdac0(&mut self) -> VDAC0_W<'_>

Bit 15 - Digital to Analog Converter 0 Clock Enable

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 16 - Capacitive touch sense module Clock Enable

pub fn trng0(&mut self) -> TRNG0_W<'_>

Bit 17 - True Random Number Generator 0 Clock Enable

impl W<u32, Reg<u32, _LFACLKEN0>>

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bit 0 - Low Energy Timer 0 Clock Enable

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bit 1 - Low Energy Sensor Interface Clock Enable

impl W<u32, Reg<u32, _LFBCLKEN0>>

pub fn systick(&mut self) -> SYSTICK_W<'_>

Bit 0 - Clock Enable

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bit 1 - Low Energy UART 0 Clock Enable

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 2 - Capacitive touch sense module Clock Enable

impl W<u32, Reg<u32, _LFECLKEN0>>

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bit 0 - Real-Time Counter and Calendar Clock Enable

impl W<u32, Reg<u32, _HFPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:12 - HFCLK Prescaler

pub fn hfclklepresc(&mut self) -> HFCLKLEPRESC_W<'_>

Bit 24 - HFCLKLE Prescaler

impl W<u32, Reg<u32, _HFCOREPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFCORECLK Prescaler

impl W<u32, Reg<u32, _HFPERPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:16 - HFPERCLK Prescaler

impl W<u32, Reg<u32, _HFEXPPRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:12 - HFEXPCLK Prescaler

impl W<u32, Reg<u32, _LFAPRESC0>>

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bits 0:3 - Low Energy Timer 0 Prescaler

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bits 4:5 - Low Energy Sensor Interface Prescaler

impl W<u32, Reg<u32, _LFBPRESC0>>

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bits 4:5 - Low Energy UART 0 Prescaler

pub fn csen(&mut self) -> CSEN_W<'_>

Bits 8:9 - Capacitive touch sense module Prescaler

impl W<u32, Reg<u32, _LFEPRESC0>>

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bits 0:1 - Real-Time Counter and Calendar Prescaler

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _PCNTCTRL>>

pub fn pcnt0clken(&mut self) -> PCNT0CLKEN_W<'_>

Bit 0 - PCNT0 Clock Enable

pub fn pcnt0clksel(&mut self) -> PCNT0CLKSEL_W<'_>

Bit 1 - PCNT0 Clock Select

pub fn pcnt1clken(&mut self) -> PCNT1CLKEN_W<'_>

Bit 2 - PCNT1 Clock Enable

pub fn pcnt1clksel(&mut self) -> PCNT1CLKSEL_W<'_>

Bit 3 - PCNT1 Clock Select

pub fn pcnt2clken(&mut self) -> PCNT2CLKEN_W<'_>

Bit 4 - PCNT2 Clock Enable

pub fn pcnt2clksel(&mut self) -> PCNT2CLKSEL_W<'_>

Bit 5 - PCNT2 Clock Select

impl W<u32, Reg<u32, _ADCCTRL>>

pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W<'_>

Bits 4:5 - ADC0 Clock Select

pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W<'_>

Bit 8 - Invert Clock Selected By ADC0CLKSEL

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn clkout0pen(&mut self) -> CLKOUT0PEN_W<'_>

Bit 0 - CLKOUT0 Pin Enable

pub fn clkout1pen(&mut self) -> CLKOUT1PEN_W<'_>

Bit 1 - CLKOUT1 Pin Enable

pub fn clkin0pen(&mut self) -> CLKIN0PEN_W<'_>

Bit 28 - CLKIN0 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn clkout0loc(&mut self) -> CLKOUT0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn clkout1loc(&mut self) -> CLKOUT1LOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn clkin0loc(&mut self) -> CLKIN0LOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _HFRCOSS>>

pub fn ssamp(&mut self) -> SSAMP_W<'_>

Bits 0:2 - Spread Spectrum Amplitude

pub fn ssinv(&mut self) -> SSINV_W<'_>

Bits 8:12 - Spread Spectrum Update Interval

impl W<u32, Reg<u32, _CTRL>>

pub fn aes(&mut self) -> AES_W<'_>

Bit 0 - AES Mode

pub fn keybufdis(&mut self) -> KEYBUFDIS_W<'_>

Bit 1 - Key Buffer Disable

pub fn sha(&mut self) -> SHA_W<'_>

Bit 2 - SHA Mode

pub fn nobusystall(&mut self) -> NOBUSYSTALL_W<'_>

Bit 10 - No Stalling of Bus When Busy

pub fn incwidth(&mut self) -> INCWIDTH_W<'_>

Bits 14:15 - Increment Width

pub fn dma0mode(&mut self) -> DMA0MODE_W<'_>

Bits 16:17 - DMA0 Read Mode

pub fn dma0rsel(&mut self) -> DMA0RSEL_W<'_>

Bits 20:21 - DMA0 Read Register Select

pub fn dma1mode(&mut self) -> DMA1MODE_W<'_>

Bits 24:25 - DMA1 Read Mode

pub fn dma1rsel(&mut self) -> DMA1RSEL_W<'_>

Bits 28:29 - DATA0 DMA Unaligned Read Register Select

pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W<'_>

Bit 31 - Combined Data0 Write DMA Request

impl W<u32, Reg<u32, _WAC>>

pub fn modulus(&mut self) -> MODULUS_W<'_>

Bits 0:3 - Modular Operation Modulus

pub fn modop(&mut self) -> MODOP_W<'_>

Bit 4 - Modular Operation Field Type

pub fn mulwidth(&mut self) -> MULWIDTH_W<'_>

Bits 8:9 - Multiply Width

pub fn resultwidth(&mut self) -> RESULTWIDTH_W<'_>

Bits 10:11 - Result Width

impl W<u32, Reg<u32, _CMD>>

pub fn instr(&mut self) -> INSTR_W<'_>

Bits 0:7 - Execute Instruction

pub fn seqstart(&mut self) -> SEQSTART_W<'_>

Bit 9 - Encryption/Decryption SEQUENCE Start

pub fn seqstop(&mut self) -> SEQSTOP_W<'_>

Bit 10 - Sequence Stop

pub fn seqstep(&mut self) -> SEQSTEP_W<'_>

Bit 11 - Sequence Step

impl W<u32, Reg<u32, _KEY>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - Key Access

impl W<u32, Reg<u32, _KEYBUF>>

pub fn keybuf(&mut self) -> KEYBUF_W<'_>

Bits 0:31 - Key Buffer Access

impl W<u32, Reg<u32, _SEQCTRL>>

pub fn lengtha(&mut self) -> LENGTHA_W<'_>

Bits 0:13 - Buffer Length a in Bytes

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 20:21 - Size of Data Blocks

pub fn dma0skip(&mut self) -> DMA0SKIP_W<'_>

Bits 24:25 - DMA0 Skip

pub fn dma1skip(&mut self) -> DMA1SKIP_W<'_>

Bits 26:27 - DMA1 Skip

pub fn dma0presa(&mut self) -> DMA0PRESA_W<'_>

Bit 28 - DMA0 Preserve a

pub fn dma1presa(&mut self) -> DMA1PRESA_W<'_>

Bit 29 - DMA1 Preserve a

pub fn halt(&mut self) -> HALT_W<'_>

Bit 31 - Halt Sequence

impl W<u32, Reg<u32, _SEQCTRLB>>

pub fn lengthb(&mut self) -> LENGTHB_W<'_>

Bits 0:13 - Buffer Length B in Bytes

pub fn dma0presb(&mut self) -> DMA0PRESB_W<'_>

Bit 28 - DMA0 Preserve B

pub fn dma1presb(&mut self) -> DMA1PRESB_W<'_>

Bit 29 - DMA1 Preserve B

impl W<u32, Reg<u32, _IFS>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - Set INSTRDONE Interrupt Flag

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - Set SEQDONE Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - Clear INSTRDONE Interrupt Flag

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - Clear SEQDONE Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn instrdone(&mut self) -> INSTRDONE_W<'_>

Bit 0 - INSTRDONE Interrupt Enable

pub fn seqdone(&mut self) -> SEQDONE_W<'_>

Bit 1 - SEQDONE Interrupt Enable

impl W<u32, Reg<u32, _SEQ0>>

pub fn instr0(&mut self) -> INSTR0_W<'_>

Bits 0:7 - Sequence Instruction 0

pub fn instr1(&mut self) -> INSTR1_W<'_>

Bits 8:15 - Sequence Instruction 1

pub fn instr2(&mut self) -> INSTR2_W<'_>

Bits 16:23 - Sequence Instruction 2

pub fn instr3(&mut self) -> INSTR3_W<'_>

Bits 24:31 - Sequence Instruction 3

impl W<u32, Reg<u32, _SEQ1>>

pub fn instr4(&mut self) -> INSTR4_W<'_>

Bits 0:7 - Sequence Instruction 4

pub fn instr5(&mut self) -> INSTR5_W<'_>

Bits 8:15 - Sequence Instruction 5

pub fn instr6(&mut self) -> INSTR6_W<'_>

Bits 16:23 - Sequence Instruction 6

pub fn instr7(&mut self) -> INSTR7_W<'_>

Bits 24:31 - Sequence Instruction 7

impl W<u32, Reg<u32, _SEQ2>>

pub fn instr8(&mut self) -> INSTR8_W<'_>

Bits 0:7 - Sequence Instruction 8

pub fn instr9(&mut self) -> INSTR9_W<'_>

Bits 8:15 - Sequence Instruction 9

pub fn instr10(&mut self) -> INSTR10_W<'_>

Bits 16:23 - Sequence Instruction 10

pub fn instr11(&mut self) -> INSTR11_W<'_>

Bits 24:31 - Sequence Instruction 11

impl W<u32, Reg<u32, _SEQ3>>

pub fn instr12(&mut self) -> INSTR12_W<'_>

Bits 0:7 - Sequence Instruction 12

pub fn instr13(&mut self) -> INSTR13_W<'_>

Bits 8:15 - Sequence Instruction 13

pub fn instr14(&mut self) -> INSTR14_W<'_>

Bits 16:23 - Sequence Instruction 14

pub fn instr15(&mut self) -> INSTR15_W<'_>

Bits 24:31 - Sequence Instruction 15

impl W<u32, Reg<u32, _SEQ4>>

pub fn instr16(&mut self) -> INSTR16_W<'_>

Bits 0:7 - Sequence Instruction 16

pub fn instr17(&mut self) -> INSTR17_W<'_>

Bits 8:15 - Sequence Instruction 17

pub fn instr18(&mut self) -> INSTR18_W<'_>

Bits 16:23 - Sequence Instruction 18

pub fn instr19(&mut self) -> INSTR19_W<'_>

Bits 24:31 - Sequence Instruction 19

impl W<u32, Reg<u32, _DATA0>>

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:31 - Data 0 Access

impl W<u32, Reg<u32, _DATA1>>

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 0:31 - Data 1 Access

impl W<u32, Reg<u32, _DATA2>>

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 0:31 - Data 2 Access

impl W<u32, Reg<u32, _DATA3>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 0:31 - Data 3 Access

impl W<u32, Reg<u32, _DATA0XOR>>

pub fn data0xor(&mut self) -> DATA0XOR_W<'_>

Bits 0:31 - XOR Data 0 Access

impl W<u32, Reg<u32, _DATA0BYTE>>

pub fn data0byte(&mut self) -> DATA0BYTE_W<'_>

Bits 0:7 - Data 0 Byte Access

impl W<u32, Reg<u32, _DATA1BYTE>>

pub fn data1byte(&mut self) -> DATA1BYTE_W<'_>

Bits 0:7 - Data 1 Byte Access

impl W<u32, Reg<u32, _DATA0XORBYTE>>

pub fn data0xorbyte(&mut self) -> DATA0XORBYTE_W<'_>

Bits 0:7 - Data 0 XOR Byte Access

impl W<u32, Reg<u32, _DATA0BYTE12>>

pub fn data0byte12(&mut self) -> DATA0BYTE12_W<'_>

Bits 0:7 - Data 0 Byte 12 Access

impl W<u32, Reg<u32, _DATA0BYTE13>>

pub fn data0byte13(&mut self) -> DATA0BYTE13_W<'_>

Bits 0:7 - Data 0 Byte 13 Access

impl W<u32, Reg<u32, _DATA0BYTE14>>

pub fn data0byte14(&mut self) -> DATA0BYTE14_W<'_>

Bits 0:7 - Data 0 Byte 14 Access

impl W<u32, Reg<u32, _DATA0BYTE15>>

pub fn data0byte15(&mut self) -> DATA0BYTE15_W<'_>

Bits 0:7 - Data 0 Byte 15 Access

impl W<u32, Reg<u32, _DDATA0>>

pub fn ddata0(&mut self) -> DDATA0_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA1>>

pub fn ddata1(&mut self) -> DDATA1_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA2>>

pub fn ddata2(&mut self) -> DDATA2_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA3>>

pub fn ddata3(&mut self) -> DDATA3_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA4>>

pub fn ddata4(&mut self) -> DDATA4_W<'_>

Bits 0:31 - Double Data 0 Access

impl W<u32, Reg<u32, _DDATA0BIG>>

pub fn ddata0big(&mut self) -> DDATA0BIG_W<'_>

Bits 0:31 - Double Data 0 Big Endian Access

impl W<u32, Reg<u32, _DDATA0BYTE>>

pub fn ddata0byte(&mut self) -> DDATA0BYTE_W<'_>

Bits 0:7 - Ddata 0 Byte Access

impl W<u32, Reg<u32, _DDATA1BYTE>>

pub fn ddata1byte(&mut self) -> DDATA1BYTE_W<'_>

Bits 0:7 - Ddata 1 Byte Access

impl W<u32, Reg<u32, _DDATA0BYTE32>>

pub fn ddata0byte32(&mut self) -> DDATA0BYTE32_W<'_>

Bits 0:3 - Ddata 0 Byte 32 Access

impl W<u32, Reg<u32, _QDATA0>>

pub fn qdata0(&mut self) -> QDATA0_W<'_>

Bits 0:31 - Quad Data 0 Access

impl W<u32, Reg<u32, _QDATA1>>

pub fn qdata1(&mut self) -> QDATA1_W<'_>

Bits 0:31 - Quad Data 1 Access

impl W<u32, Reg<u32, _QDATA1BIG>>

pub fn qdata1big(&mut self) -> QDATA1BIG_W<'_>

Bits 0:31 - Quad Data 1 Big Endian Access

impl W<u32, Reg<u32, _QDATA0BYTE>>

pub fn qdata0byte(&mut self) -> QDATA0BYTE_W<'_>

Bits 0:7 - Qdata 0 Byte Access

impl W<u32, Reg<u32, _QDATA1BYTE>>

pub fn qdata1byte(&mut self) -> QDATA1BYTE_W<'_>

Bits 0:7 - Qdata 1 Byte Access

impl W<u32, Reg<u32, _PA_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PA_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PA_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PA_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PA_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PA_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PA_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PB_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PB_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PB_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PB_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PB_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PB_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PB_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PC_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PC_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PC_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PC_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PC_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PC_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PC_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PD_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PD_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PD_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PD_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PD_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PD_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PD_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PF_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PF_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PF_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PF_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PF_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PF_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PF_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PI_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PI_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PI_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PI_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PI_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PI_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PI_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PJ_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PJ_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PJ_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PJ_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PJ_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PJ_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PJ_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _PK_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bit 0 - Drive Strength for Port

pub fn slewrate(&mut self) -> SLEWRATE_W<'_>

Bits 4:6 - Slewrate Limit for Port

pub fn dindis(&mut self) -> DINDIS_W<'_>

Bit 12 - Data in Disable

pub fn drivestrengthalt(&mut self) -> DRIVESTRENGTHALT_W<'_>

Bit 16 - Alternate Drive Strength for Port

pub fn slewratealt(&mut self) -> SLEWRATEALT_W<'_>

Bits 20:22 - Alternate Slewrate Limit for Port

pub fn dindisalt(&mut self) -> DINDISALT_W<'_>

Bit 28 - Alternate Data in Disable

impl W<u32, Reg<u32, _PK_MODEL>>

pub fn mode0(&mut self) -> MODE0_W<'_>

Bits 0:3 - Pin 0 Mode

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 4:7 - Pin 1 Mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 8:11 - Pin 2 Mode

pub fn mode3(&mut self) -> MODE3_W<'_>

Bits 12:15 - Pin 3 Mode

pub fn mode4(&mut self) -> MODE4_W<'_>

Bits 16:19 - Pin 4 Mode

pub fn mode5(&mut self) -> MODE5_W<'_>

Bits 20:23 - Pin 5 Mode

pub fn mode6(&mut self) -> MODE6_W<'_>

Bits 24:27 - Pin 6 Mode

pub fn mode7(&mut self) -> MODE7_W<'_>

Bits 28:31 - Pin 7 Mode

impl W<u32, Reg<u32, _PK_MODEH>>

pub fn mode8(&mut self) -> MODE8_W<'_>

Bits 0:3 - Pin 8 Mode

pub fn mode9(&mut self) -> MODE9_W<'_>

Bits 4:7 - Pin 9 Mode

pub fn mode10(&mut self) -> MODE10_W<'_>

Bits 8:11 - Pin 10 Mode

pub fn mode11(&mut self) -> MODE11_W<'_>

Bits 12:15 - Pin 11 Mode

pub fn mode12(&mut self) -> MODE12_W<'_>

Bits 16:19 - Pin 12 Mode

pub fn mode13(&mut self) -> MODE13_W<'_>

Bits 20:23 - Pin 13 Mode

pub fn mode14(&mut self) -> MODE14_W<'_>

Bits 24:27 - Pin 14 Mode

pub fn mode15(&mut self) -> MODE15_W<'_>

Bits 28:31 - Pin 15 Mode

impl W<u32, Reg<u32, _PK_DOUT>>

pub fn dout(&mut self) -> DOUT_W<'_>

Bits 0:15 - Data Out

impl W<u32, Reg<u32, _PK_DOUTTGL>>

pub fn douttgl(&mut self) -> DOUTTGL_W<'_>

Bits 0:15 - Data Out Toggle

impl W<u32, Reg<u32, _PK_PINLOCKN>>

pub fn pinlockn(&mut self) -> PINLOCKN_W<'_>

Bits 0:15 - Unlocked Pins

impl W<u32, Reg<u32, _PK_OVTDIS>>

pub fn ovtdis(&mut self) -> OVTDIS_W<'_>

Bits 0:15 - Disable Over Voltage Capability

impl W<u32, Reg<u32, _EXTIPSELL>>

pub fn extipsel0(&mut self) -> EXTIPSEL0_W<'_>

Bits 0:3 - External Interrupt 0 Port Select

pub fn extipsel1(&mut self) -> EXTIPSEL1_W<'_>

Bits 4:7 - External Interrupt 1 Port Select

pub fn extipsel2(&mut self) -> EXTIPSEL2_W<'_>

Bits 8:11 - External Interrupt 2 Port Select

pub fn extipsel3(&mut self) -> EXTIPSEL3_W<'_>

Bits 12:15 - External Interrupt 3 Port Select

pub fn extipsel4(&mut self) -> EXTIPSEL4_W<'_>

Bits 16:19 - External Interrupt 4 Port Select

pub fn extipsel5(&mut self) -> EXTIPSEL5_W<'_>

Bits 20:23 - External Interrupt 5 Port Select

pub fn extipsel6(&mut self) -> EXTIPSEL6_W<'_>

Bits 24:27 - External Interrupt 6 Port Select

pub fn extipsel7(&mut self) -> EXTIPSEL7_W<'_>

Bits 28:31 - External Interrupt 7 Port Select

impl W<u32, Reg<u32, _EXTIPSELH>>

pub fn extipsel8(&mut self) -> EXTIPSEL8_W<'_>

Bits 0:3 - External Interrupt 8 Port Select

pub fn extipsel9(&mut self) -> EXTIPSEL9_W<'_>

Bits 4:7 - External Interrupt 9 Port Select

pub fn extipsel10(&mut self) -> EXTIPSEL10_W<'_>

Bits 8:11 - External Interrupt 10 Port Select

pub fn extipsel11(&mut self) -> EXTIPSEL11_W<'_>

Bits 12:15 - External Interrupt 11 Port Select

pub fn extipsel12(&mut self) -> EXTIPSEL12_W<'_>

Bits 16:19 - External Interrupt 12 Port Select

pub fn extipsel13(&mut self) -> EXTIPSEL13_W<'_>

Bits 20:23 - External Interrupt 13 Port Select

pub fn extipsel14(&mut self) -> EXTIPSEL14_W<'_>

Bits 24:27 - External Interrupt 14 Port Select

pub fn extipsel15(&mut self) -> EXTIPSEL15_W<'_>

Bits 28:31 - External Interrupt 15 Port Select

impl W<u32, Reg<u32, _EXTIPINSELL>>

pub fn extipinsel0(&mut self) -> EXTIPINSEL0_W<'_>

Bits 0:1 - External Interrupt 0 Pin Select

pub fn extipinsel1(&mut self) -> EXTIPINSEL1_W<'_>

Bits 4:5 - External Interrupt 1 Pin Select

pub fn extipinsel2(&mut self) -> EXTIPINSEL2_W<'_>

Bits 8:9 - External Interrupt 2 Pin Select

pub fn extipinsel3(&mut self) -> EXTIPINSEL3_W<'_>

Bits 12:13 - External Interrupt 3 Pin Select

pub fn extipinsel4(&mut self) -> EXTIPINSEL4_W<'_>

Bits 16:17 - External Interrupt 4 Pin Select

pub fn extipinsel5(&mut self) -> EXTIPINSEL5_W<'_>

Bits 20:21 - External Interrupt 5 Pin Select

pub fn extipinsel6(&mut self) -> EXTIPINSEL6_W<'_>

Bits 24:25 - External Interrupt 6 Pin Select

pub fn extipinsel7(&mut self) -> EXTIPINSEL7_W<'_>

Bits 28:29 - External Interrupt 7 Pin Select

impl W<u32, Reg<u32, _EXTIPINSELH>>

pub fn extipinsel8(&mut self) -> EXTIPINSEL8_W<'_>

Bits 0:1 - External Interrupt 8 Pin Select

pub fn extipinsel9(&mut self) -> EXTIPINSEL9_W<'_>

Bits 4:5 - External Interrupt 9 Pin Select

pub fn extipinsel10(&mut self) -> EXTIPINSEL10_W<'_>

Bits 8:9 - External Interrupt 10 Pin Select

pub fn extipinsel11(&mut self) -> EXTIPINSEL11_W<'_>

Bits 12:13 - External Interrupt 11 Pin Select

pub fn extipinsel12(&mut self) -> EXTIPINSEL12_W<'_>

Bits 16:17 - External Interrupt 12 Pin Select

pub fn extipinsel13(&mut self) -> EXTIPINSEL13_W<'_>

Bits 20:21 - External Interrupt 13 Pin Select

pub fn extipinsel14(&mut self) -> EXTIPINSEL14_W<'_>

Bits 24:25 - External Interrupt 14 Pin Select

pub fn extipinsel15(&mut self) -> EXTIPINSEL15_W<'_>

Bits 28:29 - External Interrupt 15 Pin Select

impl W<u32, Reg<u32, _EXTIRISE>>

pub fn extirise(&mut self) -> EXTIRISE_W<'_>

Bits 0:15 - External Interrupt N Rising Edge Trigger Enable

impl W<u32, Reg<u32, _EXTIFALL>>

pub fn extifall(&mut self) -> EXTIFALL_W<'_>

Bits 0:15 - External Interrupt N Falling Edge Trigger Enable

impl W<u32, Reg<u32, _EXTILEVEL>>

pub fn em4wu0(&mut self) -> EM4WU0_W<'_>

Bit 16 - EM4 Wake Up Level for EM4WU0 Pin

pub fn em4wu1(&mut self) -> EM4WU1_W<'_>

Bit 17 - EM4 Wake Up Level for EM4WU1 Pin

pub fn em4wu4(&mut self) -> EM4WU4_W<'_>

Bit 20 - EM4 Wake Up Level for EM4WU4 Pin

pub fn em4wu8(&mut self) -> EM4WU8_W<'_>

Bit 24 - EM4 Wake Up Level for EM4WU8 Pin

pub fn em4wu9(&mut self) -> EM4WU9_W<'_>

Bit 25 - EM4 Wake Up Level for EM4WU9 Pin

pub fn em4wu12(&mut self) -> EM4WU12_W<'_>

Bit 28 - EM4 Wake Up Level for EM4WU12 Pin

impl W<u32, Reg<u32, _IFS>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - Set EXT Interrupt Flag

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - Set EM4WU Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - Clear EXT Interrupt Flag

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - Clear EM4WU Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ext(&mut self) -> EXT_W<'_>

Bits 0:15 - EXT Interrupt Enable

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bits 16:31 - EM4WU Interrupt Enable

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wuen(&mut self) -> EM4WUEN_W<'_>

Bits 16:31 - EM4 Wake Up Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W<'_>

Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable

pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W<'_>

Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable

pub fn tdopen(&mut self) -> TDOPEN_W<'_>

Bit 2 - JTAG Test Debug Output Pin Enable

pub fn tdipen(&mut self) -> TDIPEN_W<'_>

Bit 3 - JTAG Test Debug Input Pin Enable

pub fn swvpen(&mut self) -> SWVPEN_W<'_>

Bit 4 - Serial Wire Viewer Output Pin Enable

pub fn etmtclkpen(&mut self) -> ETMTCLKPEN_W<'_>

Bit 16 - ETM Trace Clock Pin Enable

pub fn etmtd0pen(&mut self) -> ETMTD0PEN_W<'_>

Bit 17 - ETM Trace Data Pin Enable

pub fn etmtd1pen(&mut self) -> ETMTD1PEN_W<'_>

Bit 18 - ETM Trace Data Pin Enable

pub fn etmtd2pen(&mut self) -> ETMTD2PEN_W<'_>

Bit 19 - ETM Trace Data Pin Enable

pub fn etmtd3pen(&mut self) -> ETMTD3PEN_W<'_>

Bit 20 - ETM Trace Data Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn swvloc(&mut self) -> SWVLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn etmtclkloc(&mut self) -> ETMTCLKLOC_W<'_>

Bits 0:5 - I/O Location

pub fn etmtd0loc(&mut self) -> ETMTD0LOC_W<'_>

Bits 8:13 - I/O Location

pub fn etmtd1loc(&mut self) -> ETMTD1LOC_W<'_>

Bits 14:19 - I/O Location

pub fn etmtd2loc(&mut self) -> ETMTD2LOC_W<'_>

Bits 20:25 - I/O Location

pub fn etmtd3loc(&mut self) -> ETMTD3LOC_W<'_>

Bits 26:31 - I/O Location

impl W<u32, Reg<u32, _INSENSE>>

pub fn int(&mut self) -> INT_W<'_>

Bit 0 - Interrupt Sense Enable

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 1 - EM4WU Interrupt Sense Enable

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _SWPULSE>>

pub fn ch0pulse(&mut self) -> CH0PULSE_W<'_>

Bit 0 - Channel 0 Pulse Generation

pub fn ch1pulse(&mut self) -> CH1PULSE_W<'_>

Bit 1 - Channel 1 Pulse Generation

pub fn ch2pulse(&mut self) -> CH2PULSE_W<'_>

Bit 2 - Channel 2 Pulse Generation

pub fn ch3pulse(&mut self) -> CH3PULSE_W<'_>

Bit 3 - Channel 3 Pulse Generation

pub fn ch4pulse(&mut self) -> CH4PULSE_W<'_>

Bit 4 - Channel 4 Pulse Generation

pub fn ch5pulse(&mut self) -> CH5PULSE_W<'_>

Bit 5 - Channel 5 Pulse Generation

pub fn ch6pulse(&mut self) -> CH6PULSE_W<'_>

Bit 6 - Channel 6 Pulse Generation

pub fn ch7pulse(&mut self) -> CH7PULSE_W<'_>

Bit 7 - Channel 7 Pulse Generation

pub fn ch8pulse(&mut self) -> CH8PULSE_W<'_>

Bit 8 - Channel 8 Pulse Generation

pub fn ch9pulse(&mut self) -> CH9PULSE_W<'_>

Bit 9 - Channel 9 Pulse Generation

pub fn ch10pulse(&mut self) -> CH10PULSE_W<'_>

Bit 10 - Channel 10 Pulse Generation

pub fn ch11pulse(&mut self) -> CH11PULSE_W<'_>

Bit 11 - Channel 11 Pulse Generation

impl W<u32, Reg<u32, _SWLEVEL>>

pub fn ch0level(&mut self) -> CH0LEVEL_W<'_>

Bit 0 - Channel 0 Software Level

pub fn ch1level(&mut self) -> CH1LEVEL_W<'_>

Bit 1 - Channel 1 Software Level

pub fn ch2level(&mut self) -> CH2LEVEL_W<'_>

Bit 2 - Channel 2 Software Level

pub fn ch3level(&mut self) -> CH3LEVEL_W<'_>

Bit 3 - Channel 3 Software Level

pub fn ch4level(&mut self) -> CH4LEVEL_W<'_>

Bit 4 - Channel 4 Software Level

pub fn ch5level(&mut self) -> CH5LEVEL_W<'_>

Bit 5 - Channel 5 Software Level

pub fn ch6level(&mut self) -> CH6LEVEL_W<'_>

Bit 6 - Channel 6 Software Level

pub fn ch7level(&mut self) -> CH7LEVEL_W<'_>

Bit 7 - Channel 7 Software Level

pub fn ch8level(&mut self) -> CH8LEVEL_W<'_>

Bit 8 - Channel 8 Software Level

pub fn ch9level(&mut self) -> CH9LEVEL_W<'_>

Bit 9 - Channel 9 Software Level

pub fn ch10level(&mut self) -> CH10LEVEL_W<'_>

Bit 10 - Channel 10 Software Level

pub fn ch11level(&mut self) -> CH11LEVEL_W<'_>

Bit 11 - Channel 11 Software Level

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn ch0pen(&mut self) -> CH0PEN_W<'_>

Bit 0 - CH0 Pin Enable

pub fn ch1pen(&mut self) -> CH1PEN_W<'_>

Bit 1 - CH1 Pin Enable

pub fn ch2pen(&mut self) -> CH2PEN_W<'_>

Bit 2 - CH2 Pin Enable

pub fn ch3pen(&mut self) -> CH3PEN_W<'_>

Bit 3 - CH3 Pin Enable

pub fn ch4pen(&mut self) -> CH4PEN_W<'_>

Bit 4 - CH4 Pin Enable

pub fn ch5pen(&mut self) -> CH5PEN_W<'_>

Bit 5 - CH5 Pin Enable

pub fn ch6pen(&mut self) -> CH6PEN_W<'_>

Bit 6 - CH6 Pin Enable

pub fn ch7pen(&mut self) -> CH7PEN_W<'_>

Bit 7 - CH7 Pin Enable

pub fn ch8pen(&mut self) -> CH8PEN_W<'_>

Bit 8 - CH8 Pin Enable

pub fn ch9pen(&mut self) -> CH9PEN_W<'_>

Bit 9 - CH9 Pin Enable

pub fn ch10pen(&mut self) -> CH10PEN_W<'_>

Bit 10 - CH10 Pin Enable

pub fn ch11pen(&mut self) -> CH11PEN_W<'_>

Bit 11 - CH11 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn ch0loc(&mut self) -> CH0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch1loc(&mut self) -> CH1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch2loc(&mut self) -> CH2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch3loc(&mut self) -> CH3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ch4loc(&mut self) -> CH4LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch5loc(&mut self) -> CH5LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch6loc(&mut self) -> CH6LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch7loc(&mut self) -> CH7LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn ch8loc(&mut self) -> CH8LOC_W<'_>

Bits 0:5 - I/O Location

pub fn ch9loc(&mut self) -> CH9LOC_W<'_>

Bits 8:13 - I/O Location

pub fn ch10loc(&mut self) -> CH10LOC_W<'_>

Bits 16:21 - I/O Location

pub fn ch11loc(&mut self) -> CH11LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn sevonprs(&mut self) -> SEVONPRS_W<'_>

Bit 0 - Set Event on PRS

pub fn sevonprssel(&mut self) -> SEVONPRSSEL_W<'_>

Bits 1:4 - SEVONPRS PRS Channel Select

impl W<u32, Reg<u32, _DMAREQ0>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:9 - DMA Request 0 PRS Channel Select

impl W<u32, Reg<u32, _DMAREQ1>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:9 - DMA Request 1 PRS Channel Select

impl W<u32, Reg<u32, _CH0_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH1_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH2_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH3_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH4_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH5_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH6_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH7_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH8_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH9_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH10_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CH11_CTRL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:2 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 8:14 - Source Select

pub fn edsel(&mut self) -> EDSEL_W<'_>

Bits 20:21 - Edge Detect Select

pub fn stretch(&mut self) -> STRETCH_W<'_>

Bit 25 - Stretch Channel Output

pub fn inv(&mut self) -> INV_W<'_>

Bit 26 - Invert Channel

pub fn orprev(&mut self) -> ORPREV_W<'_>

Bit 27 - Or Previous

pub fn andnext(&mut self) -> ANDNEXT_W<'_>

Bit 28 - And Next

pub fn async_(&mut self) -> ASYNC_W<'_>

Bit 30 - Asynchronous Reflex

impl W<u32, Reg<u32, _CTRL>>

pub fn syncprsseten(&mut self) -> SYNCPRSSETEN_W<'_>

Bits 0:7 - Synchronization PRS Set Enable

pub fn syncprsclren(&mut self) -> SYNCPRSCLREN_W<'_>

Bits 8:15 - Synchronization PRS Clear Enable

pub fn numfixed(&mut self) -> NUMFIXED_W<'_>

Bits 24:26 - Number of Fixed Priority Channels

impl W<u32, Reg<u32, _SYNC>>

pub fn synctrig(&mut self) -> SYNCTRIG_W<'_>

Bits 0:7 - Synchronization Trigger

impl W<u32, Reg<u32, _CHEN>>

pub fn chen(&mut self) -> CHEN_W<'_>

Bits 0:7 - Channel Enables

impl W<u32, Reg<u32, _CHDONE>>

pub fn chdone(&mut self) -> CHDONE_W<'_>

Bits 0:7 - DMA Channel Linking or Done

impl W<u32, Reg<u32, _DBGHALT>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bits 0:7 - DMA Debug Halt

impl W<u32, Reg<u32, _SWREQ>>

pub fn swreq(&mut self) -> SWREQ_W<'_>

Bits 0:7 - Software Transfer Requests

impl W<u32, Reg<u32, _REQDIS>>

pub fn reqdis(&mut self) -> REQDIS_W<'_>

Bits 0:7 - DMA Request Disables

impl W<u32, Reg<u32, _LINKLOAD>>

pub fn linkload(&mut self) -> LINKLOAD_W<'_>

Bits 0:7 - DMA Link Loads

impl W<u32, Reg<u32, _REQCLEAR>>

pub fn reqclear(&mut self) -> REQCLEAR_W<'_>

Bits 0:7 - DMA Request Clear

impl W<u32, Reg<u32, _IFS>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:7 - Set DONE Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - Set ERROR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:7 - Clear DONE Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - Clear ERROR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn done(&mut self) -> DONE_W<'_>

Bits 0:7 - DONE Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 31 - ERROR Interrupt Enable

impl W<u32, Reg<u32, _CH0_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH0_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH0_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH0_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH0_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH0_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH0_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH1_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH1_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH1_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH1_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH1_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH1_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH1_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH2_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH2_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH2_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH2_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH2_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH2_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH2_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH3_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH3_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH3_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH3_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH3_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH3_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH3_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH4_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH4_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH4_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH4_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH4_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH4_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH4_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH5_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH5_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH5_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH5_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH5_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH5_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH5_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH6_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH6_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH6_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH6_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH6_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH6_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH6_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _CH7_REQSEL>>

pub fn sigsel(&mut self) -> SIGSEL_W<'_>

Bits 0:3 - Signal Select

pub fn sourcesel(&mut self) -> SOURCESEL_W<'_>

Bits 16:21 - Source Select

impl W<u32, Reg<u32, _CH7_CFG>>

pub fn arbslots(&mut self) -> ARBSLOTS_W<'_>

Bits 16:17 - Arbitration Slot Number Select

pub fn srcincsign(&mut self) -> SRCINCSIGN_W<'_>

Bit 20 - Source Address Increment Sign

pub fn dstincsign(&mut self) -> DSTINCSIGN_W<'_>

Bit 21 - Destination Address Increment Sign

impl W<u32, Reg<u32, _CH7_LOOP>>

pub fn loopcnt(&mut self) -> LOOPCNT_W<'_>

Bits 0:7 - Linked Structure Sequence Loop Counter

impl W<u32, Reg<u32, _CH7_CTRL>>

pub fn structreq(&mut self) -> STRUCTREQ_W<'_>

Bit 3 - Structure DMA Transfer Request

pub fn xfercnt(&mut self) -> XFERCNT_W<'_>

Bits 4:14 - DMA Unit Data Transfer Count

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 15 - Endian Byte Swap

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 16:19 - Block Transfer Size

pub fn doneifsen(&mut self) -> DONEIFSEN_W<'_>

Bit 20 - DMA Operation Done Interrupt Flag Set Enable

pub fn reqmode(&mut self) -> REQMODE_W<'_>

Bit 21 - DMA Request Transfer Mode Select

pub fn decloopcnt(&mut self) -> DECLOOPCNT_W<'_>

Bit 22 - Decrement Loop Count

pub fn ignoresreq(&mut self) -> IGNORESREQ_W<'_>

Bit 23 - Ignore Sreq

pub fn srcinc(&mut self) -> SRCINC_W<'_>

Bits 24:25 - Source Address Increment Size

pub fn size(&mut self) -> SIZE_W<'_>

Bits 26:27 - Unit Data Transfer Size

pub fn dstinc(&mut self) -> DSTINC_W<'_>

Bits 28:29 - Destination Address Increment Size

impl W<u32, Reg<u32, _CH7_SRC>>

pub fn srcaddr(&mut self) -> SRCADDR_W<'_>

Bits 0:31 - Source Data Address

impl W<u32, Reg<u32, _CH7_DST>>

pub fn dstaddr(&mut self) -> DSTADDR_W<'_>

Bits 0:31 - Destination Data Address

impl W<u32, Reg<u32, _CH7_LINK>>

pub fn link(&mut self) -> LINK_W<'_>

Bit 1 - Link Next Structure

pub fn linkaddr(&mut self) -> LINKADDR_W<'_>

Bits 2:31 - Link Structure Address

impl W<u32, Reg<u32, _IFS>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - Set FPIOC Interrupt Flag

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - Set FPDZC Interrupt Flag

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - Set FPUFC Interrupt Flag

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - Set FPOFC Interrupt Flag

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - Set FPIDC Interrupt Flag

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - Set FPIXC Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - Clear FPIOC Interrupt Flag

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - Clear FPDZC Interrupt Flag

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - Clear FPUFC Interrupt Flag

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - Clear FPOFC Interrupt Flag

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - Clear FPIDC Interrupt Flag

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - Clear FPIXC Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn fpioc(&mut self) -> FPIOC_W<'_>

Bit 0 - FPIOC Interrupt Enable

pub fn fpdzc(&mut self) -> FPDZC_W<'_>

Bit 1 - FPDZC Interrupt Enable

pub fn fpufc(&mut self) -> FPUFC_W<'_>

Bit 2 - FPUFC Interrupt Enable

pub fn fpofc(&mut self) -> FPOFC_W<'_>

Bit 3 - FPOFC Interrupt Enable

pub fn fpidc(&mut self) -> FPIDC_W<'_>

Bit 4 - FPIDC Interrupt Enable

pub fn fpixc(&mut self) -> FPIXC_W<'_>

Bit 5 - FPIXC Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - CRC Functionality Enable

pub fn polysel(&mut self) -> POLYSEL_W<'_>

Bit 4 - Polynomial Select

pub fn bytemode(&mut self) -> BYTEMODE_W<'_>

Bit 8 - Byte Mode Enable

pub fn bitreverse(&mut self) -> BITREVERSE_W<'_>

Bit 9 - Byte-level Bit Reverse Enable

pub fn bytereverse(&mut self) -> BYTEREVERSE_W<'_>

Bit 10 - Byte Reverse Mode

pub fn autoinit(&mut self) -> AUTOINIT_W<'_>

Bit 13 - Auto Init Enable

impl W<u32, Reg<u32, _CMD>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialization Enable

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - CRC Initialization Value

impl W<u32, Reg<u32, _POLY>>

pub fn poly(&mut self) -> POLY_W<'_>

Bits 0:15 - CRC Polynomial Value

impl W<u32, Reg<u32, _INPUTDATA>>

pub fn inputdata(&mut self) -> INPUTDATA_W<'_>

Bits 0:31 - Input Data for 32-bit

impl W<u32, Reg<u32, _INPUTDATAHWORD>>

pub fn inputdatahword(&mut self) -> INPUTDATAHWORD_W<'_>

Bits 0:15 - Input Data for 16-bit

impl W<u32, Reg<u32, _INPUTDATABYTE>>

pub fn inputdatabyte(&mut self) -> INPUTDATABYTE_W<'_>

Bits 0:7 - Input Data for 8-bit

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:7 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:3 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:11 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer Mode

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 3 - Timer Start/Stop/Reload Synchronization

pub fn osmen(&mut self) -> OSMEN_W<'_>

Bit 4 - One-shot Mode Enable

pub fn qdm(&mut self) -> QDM_W<'_>

Bit 5 - Quadrature Decoder Mode Selection

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 6 - Debug Mode Run Enable

pub fn dmaclract(&mut self) -> DMACLRACT_W<'_>

Bit 7 - DMA Request Clear on Active

pub fn risea(&mut self) -> RISEA_W<'_>

Bits 8:9 - Timer Rising Input Edge Action

pub fn falla(&mut self) -> FALLA_W<'_>

Bits 10:11 - Timer Falling Input Edge Action

pub fn x2cnt(&mut self) -> X2CNT_W<'_>

Bit 13 - 2x Count Mode

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 16:17 - Clock Source Select

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 24:27 - Prescaler Setting

pub fn ati(&mut self) -> ATI_W<'_>

Bit 28 - Always Track Inputs

pub fn rsscoist(&mut self) -> RSSCOIST_W<'_>

Bit 29 - Reload-Start Sets Compare Output Initial State

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Timer

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Timer

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Set UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Set DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Set CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Set CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Set ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Set ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Set ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Set ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - Clear UF Interrupt Flag

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - Clear DIRCHG Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - Clear CC2 Interrupt Flag

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - Clear CC3 Interrupt Flag

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - Clear ICBOF0 Interrupt Flag

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - Clear ICBOF1 Interrupt Flag

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - Clear ICBOF2 Interrupt Flag

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - Clear ICBOF3 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 1 - UF Interrupt Enable

pub fn dirchg(&mut self) -> DIRCHG_W<'_>

Bit 2 - DIRCHG Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 4 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 5 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 6 - CC2 Interrupt Enable

pub fn cc3(&mut self) -> CC3_W<'_>

Bit 7 - CC3 Interrupt Enable

pub fn icbof0(&mut self) -> ICBOF0_W<'_>

Bit 8 - ICBOF0 Interrupt Enable

pub fn icbof1(&mut self) -> ICBOF1_W<'_>

Bit 9 - ICBOF1 Interrupt Enable

pub fn icbof2(&mut self) -> ICBOF2_W<'_>

Bit 10 - ICBOF2 Interrupt Enable

pub fn icbof3(&mut self) -> ICBOF3_W<'_>

Bit 11 - ICBOF3 Interrupt Enable

impl W<u32, Reg<u32, _TOP>>

pub fn top(&mut self) -> TOP_W<'_>

Bits 0:31 - Counter Top Value

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:31 - Counter Top Value Buffer

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _LOCK>>

pub fn timerlockkey(&mut self) -> TIMERLOCKKEY_W<'_>

Bits 0:15 - Timer Lock Key

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn cc0pen(&mut self) -> CC0PEN_W<'_>

Bit 0 - CC Channel 0 Pin Enable

pub fn cc1pen(&mut self) -> CC1PEN_W<'_>

Bit 1 - CC Channel 1 Pin Enable

pub fn cc2pen(&mut self) -> CC2PEN_W<'_>

Bit 2 - CC Channel 2 Pin Enable

pub fn cc3pen(&mut self) -> CC3PEN_W<'_>

Bit 3 - CC Channel 3 Pin Enable

pub fn cdti0pen(&mut self) -> CDTI0PEN_W<'_>

Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable

pub fn cdti1pen(&mut self) -> CDTI1PEN_W<'_>

Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable

pub fn cdti2pen(&mut self) -> CDTI2PEN_W<'_>

Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn cc0loc(&mut self) -> CC0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cc1loc(&mut self) -> CC1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cc2loc(&mut self) -> CC2LOC_W<'_>

Bits 16:21 - I/O Location

pub fn cc3loc(&mut self) -> CC3LOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC2>>

pub fn cdti0loc(&mut self) -> CDTI0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn cdti1loc(&mut self) -> CDTI1LOC_W<'_>

Bits 8:13 - I/O Location

pub fn cdti2loc(&mut self) -> CDTI2LOC_W<'_>

Bits 16:21 - I/O Location

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC0_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC1_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC2_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _CC3_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn outinv(&mut self) -> OUTINV_W<'_>

Bit 2 - Output Invert

pub fn coist(&mut self) -> COIST_W<'_>

Bit 4 - Compare Output Initial State

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 8:9 - Compare Match Output Action

pub fn cofoa(&mut self) -> COFOA_W<'_>

Bits 10:11 - Counter Overflow Output Action

pub fn cufoa(&mut self) -> CUFOA_W<'_>

Bits 12:13 - Counter Underflow Output Action

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 16:19 - Compare/Capture Channel PRS Input Channel Selection

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 24:25 - Input Capture Edge Select

pub fn icevctrl(&mut self) -> ICEVCTRL_W<'_>

Bits 26:27 - Input Capture Event Control

pub fn prsconf(&mut self) -> PRSCONF_W<'_>

Bit 28 - PRS Configuration

pub fn insel(&mut self) -> INSEL_W<'_>

Bit 29 - Input Selection

pub fn filt(&mut self) -> FILT_W<'_>

Bit 30 - Digital Filter

impl W<u32, Reg<u32, _CC3_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - CC Channel Value

impl W<u32, Reg<u32, _CC3_CCVB>>

pub fn ccvb(&mut self) -> CCVB_W<'_>

Bits 0:31 - CC Channel Value Buffer

impl W<u32, Reg<u32, _DTCTRL>>

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTI Enable

pub fn dtdas(&mut self) -> DTDAS_W<'_>

Bit 1 - DTI Automatic Start-up Functionality

pub fn dtipol(&mut self) -> DTIPOL_W<'_>

Bit 2 - DTI Inactive Polarity

pub fn dtcinv(&mut self) -> DTCINV_W<'_>

Bit 3 - DTI Complementary Output Invert

pub fn dtprssel(&mut self) -> DTPRSSEL_W<'_>

Bits 4:7 - DTI PRS Source Channel Select

pub fn dtar(&mut self) -> DTAR_W<'_>

Bit 9 - DTI Always Run

pub fn dtfats(&mut self) -> DTFATS_W<'_>

Bit 10 - DTI Fault Action on Timer Stop

pub fn dtprsen(&mut self) -> DTPRSEN_W<'_>

Bit 24 - DTI PRS Source Enable

impl W<u32, Reg<u32, _DTTIME>>

pub fn dtpresc(&mut self) -> DTPRESC_W<'_>

Bits 0:3 - DTI Prescaler Setting

pub fn dtriset(&mut self) -> DTRISET_W<'_>

Bits 8:13 - DTI Rise-time

pub fn dtfallt(&mut self) -> DTFALLT_W<'_>

Bits 16:21 - DTI Fall-time

impl W<u32, Reg<u32, _DTFC>>

pub fn dtprs0fsel(&mut self) -> DTPRS0FSEL_W<'_>

Bits 0:3 - DTI PRS Fault Source 0 Select

pub fn dtprs1fsel(&mut self) -> DTPRS1FSEL_W<'_>

Bits 8:11 - DTI PRS Fault Source 1 Select

pub fn dtfa(&mut self) -> DTFA_W<'_>

Bits 16:17 - DTI Fault Action

pub fn dtprs0fen(&mut self) -> DTPRS0FEN_W<'_>

Bit 24 - DTI PRS 0 Fault Enable

pub fn dtprs1fen(&mut self) -> DTPRS1FEN_W<'_>

Bit 25 - DTI PRS 1 Fault Enable

pub fn dtdbgfen(&mut self) -> DTDBGFEN_W<'_>

Bit 26 - DTI Debugger Fault Enable

pub fn dtlockupfen(&mut self) -> DTLOCKUPFEN_W<'_>

Bit 27 - DTI Lockup Fault Enable

impl W<u32, Reg<u32, _DTOGEN>>

pub fn dtogcc0en(&mut self) -> DTOGCC0EN_W<'_>

Bit 0 - DTI CC0 Output Generation Enable

pub fn dtogcc1en(&mut self) -> DTOGCC1EN_W<'_>

Bit 1 - DTI CC1 Output Generation Enable

pub fn dtogcc2en(&mut self) -> DTOGCC2EN_W<'_>

Bit 2 - DTI CC2 Output Generation Enable

pub fn dtogcdti0en(&mut self) -> DTOGCDTI0EN_W<'_>

Bit 3 - DTI CDTI0 Output Generation Enable

pub fn dtogcdti1en(&mut self) -> DTOGCDTI1EN_W<'_>

Bit 4 - DTI CDTI1 Output Generation Enable

pub fn dtogcdti2en(&mut self) -> DTOGCDTI2EN_W<'_>

Bit 5 - DTI CDTI2 Output Generation Enable

impl W<u32, Reg<u32, _DTFAULTC>>

pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<'_>

Bit 0 - DTI PRS0 Fault Clear

pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<'_>

Bit 1 - DTI PRS1 Fault Clear

pub fn dtdbgfc(&mut self) -> DTDBGFC_W<'_>

Bit 2 - DTI Debugger Fault Clear

pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<'_>

Bit 3 - DTI Lockup Fault Clear

impl W<u32, Reg<u32, _DTLOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - DTI Lock Key

impl W<u32, Reg<u32, _CTRL>>

pub fn sync(&mut self) -> SYNC_W<'_>

Bit 0 - USART Synchronous Mode

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 1 - Loopback Enable

pub fn ccen(&mut self) -> CCEN_W<'_>

Bit 2 - Collision Check Enable

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 3 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 4 - Multi-Processor Address-Bit

pub fn ovs(&mut self) -> OVS_W<'_>

Bits 5:6 - Oversampling

pub fn clkpol(&mut self) -> CLKPOL_W<'_>

Bit 8 - Clock Polarity

pub fn clkpha(&mut self) -> CLKPHA_W<'_>

Bit 9 - Clock Edge for Setup/Sample

pub fn msbf(&mut self) -> MSBF_W<'_>

Bit 10 - Most Significant Bit First

pub fn csma(&mut self) -> CSMA_W<'_>

Bit 11 - Action on Slave-Select in Master Mode

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 12 - TX Buffer Interrupt Level

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 13 - Receiver Input Invert

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 14 - Transmitter Output Invert

pub fn csinv(&mut self) -> CSINV_W<'_>

Bit 15 - Chip Select Invert

pub fn autocs(&mut self) -> AUTOCS_W<'_>

Bit 16 - Automatic Chip Select

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 17 - Automatic TX Tristate

pub fn scmode(&mut self) -> SCMODE_W<'_>

Bit 18 - SmartCard Mode

pub fn scretrans(&mut self) -> SCRETRANS_W<'_>

Bit 19 - SmartCard Retransmit

pub fn skipperrf(&mut self) -> SKIPPERRF_W<'_>

Bit 20 - Skip Parity Error Frames

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 21 - Bit 8 Default Value

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 22 - Halt DMA on Error

pub fn errsrx(&mut self) -> ERRSRX_W<'_>

Bit 23 - Disable RX on Error

pub fn errstx(&mut self) -> ERRSTX_W<'_>

Bit 24 - Disable TX on Error

pub fn sssearly(&mut self) -> SSSEARLY_W<'_>

Bit 25 - Synchronous Slave Setup Early

pub fn byteswap(&mut self) -> BYTESWAP_W<'_>

Bit 28 - Byteswap in Double Accesses

pub fn autotx(&mut self) -> AUTOTX_W<'_>

Bit 29 - Always Transmit When RX Not Full

pub fn mvdis(&mut self) -> MVDIS_W<'_>

Bit 30 - Majority Vote Disable

pub fn smsdelay(&mut self) -> SMSDELAY_W<'_>

Bit 31 - Synchronous Master Sample Delay

impl W<u32, Reg<u32, _FRAME>>

pub fn databits(&mut self) -> DATABITS_W<'_>

Bits 0:3 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 8:9 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bits 12:13 - Stop-Bit Mode

impl W<u32, Reg<u32, _TRIGCTRL>>

pub fn rxten(&mut self) -> RXTEN_W<'_>

Bit 4 - Receive Trigger Enable

pub fn txten(&mut self) -> TXTEN_W<'_>

Bit 5 - Transmit Trigger Enable

pub fn autotxten(&mut self) -> AUTOTXTEN_W<'_>

Bit 6 - AUTOTX Trigger Enable

pub fn txarx0en(&mut self) -> TXARX0EN_W<'_>

Bit 7 - Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL

pub fn txarx1en(&mut self) -> TXARX1EN_W<'_>

Bit 8 - Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL

pub fn txarx2en(&mut self) -> TXARX2EN_W<'_>

Bit 9 - Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL

pub fn rxatx0en(&mut self) -> RXATX0EN_W<'_>

Bit 10 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times

pub fn rxatx1en(&mut self) -> RXATX1EN_W<'_>

Bit 11 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times

pub fn rxatx2en(&mut self) -> RXATX2EN_W<'_>

Bit 12 - Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times

pub fn tsel(&mut self) -> TSEL_W<'_>

Bits 16:19 - Trigger PRS Channel Select

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn masteren(&mut self) -> MASTEREN_W<'_>

Bit 4 - Master Enable

pub fn masterdis(&mut self) -> MASTERDIS_W<'_>

Bit 5 - Master Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 6 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 7 - Receiver Block Disable

pub fn txtrien(&mut self) -> TXTRIEN_W<'_>

Bit 8 - Transmitter Tristate Enable

pub fn txtridis(&mut self) -> TXTRIDIS_W<'_>

Bit 9 - Transmitter Tristate Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 10 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 11 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:22 - Fractional Clock Divider

pub fn autobauden(&mut self) -> AUTOBAUDEN_W<'_>

Bit 31 - AUTOBAUD Detection Enable

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdatax(&mut self) -> TXDATAX_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat(&mut self) -> UBRXAT_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat(&mut self) -> TXTRIAT_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLEX>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:8 - TX Data

pub fn ubrxat0(&mut self) -> UBRXAT0_W<'_>

Bit 11 - Unblock RX After Transmission

pub fn txtriat0(&mut self) -> TXTRIAT0_W<'_>

Bit 12 - Set TXTRI After Transmission

pub fn txbreak0(&mut self) -> TXBREAK0_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat0(&mut self) -> TXDISAT0_W<'_>

Bit 14 - Clear TXEN After Transmission

pub fn rxenat0(&mut self) -> RXENAT0_W<'_>

Bit 15 - Enable RX After Transmission

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 16:24 - TX Data

pub fn ubrxat1(&mut self) -> UBRXAT1_W<'_>

Bit 27 - Unblock RX After Transmission

pub fn txtriat1(&mut self) -> TXTRIAT1_W<'_>

Bit 28 - Set TXTRI After Transmission

pub fn txbreak1(&mut self) -> TXBREAK1_W<'_>

Bit 29 - Transmit Data as Break

pub fn txdisat1(&mut self) -> TXDISAT1_W<'_>

Bit 30 - Clear TXEN After Transmission

pub fn rxenat1(&mut self) -> RXENAT1_W<'_>

Bit 31 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Set RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Set TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Set TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Set MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Set SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Set CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Set TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Set TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Set TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Set TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - Clear RXFULL Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - Clear TXOF Interrupt Flag

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - Clear TXUF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - Clear MPAF Interrupt Flag

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - Clear SSM Interrupt Flag

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - Clear CCF Interrupt Flag

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - Clear TXIDLE Interrupt Flag

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - Clear TCMP0 Interrupt Flag

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - Clear TCMP1 Interrupt Flag

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - Clear TCMP2 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 3 - RXFULL Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 4 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 5 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 6 - TXOF Interrupt Enable

pub fn txuf(&mut self) -> TXUF_W<'_>

Bit 7 - TXUF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 8 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 9 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 10 - MPAF Interrupt Enable

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 11 - SSM Interrupt Enable

pub fn ccf(&mut self) -> CCF_W<'_>

Bit 12 - CCF Interrupt Enable

pub fn txidle(&mut self) -> TXIDLE_W<'_>

Bit 13 - TXIDLE Interrupt Enable

pub fn tcmp0(&mut self) -> TCMP0_W<'_>

Bit 14 - TCMP0 Interrupt Enable

pub fn tcmp1(&mut self) -> TCMP1_W<'_>

Bit 15 - TCMP1 Interrupt Enable

pub fn tcmp2(&mut self) -> TCMP2_W<'_>

Bit 16 - TCMP2 Interrupt Enable

impl W<u32, Reg<u32, _IRCTRL>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Enable IrDA Module

pub fn irpw(&mut self) -> IRPW_W<'_>

Bits 1:2 - IrDA TX Pulse Width

pub fn irfilt(&mut self) -> IRFILT_W<'_>

Bit 3 - IrDA RX Filter

pub fn irprsen(&mut self) -> IRPRSEN_W<'_>

Bit 7 - IrDA PRS Channel Enable

pub fn irprssel(&mut self) -> IRPRSSEL_W<'_>

Bits 8:11 - IrDA PRS Channel Select

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:3 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 7 - PRS RX Enable

pub fn clkprssel(&mut self) -> CLKPRSSEL_W<'_>

Bits 8:11 - CLK PRS Channel Select

pub fn clkprs(&mut self) -> CLKPRS_W<'_>

Bit 15 - PRS CLK Enable

impl W<u32, Reg<u32, _I2SCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable I2S Mode

pub fn mono(&mut self) -> MONO_W<'_>

Bit 1 - Stero or Mono

pub fn justify(&mut self) -> JUSTIFY_W<'_>

Bit 2 - Justification of I2S Data

pub fn dmasplit(&mut self) -> DMASPLIT_W<'_>

Bit 3 - Separate DMA Request for Left/Right Data

pub fn delay(&mut self) -> DELAY_W<'_>

Bit 4 - Delay on I2S Data

pub fn format(&mut self) -> FORMAT_W<'_>

Bits 8:10 - I2S Word Format

impl W<u32, Reg<u32, _TIMING>>

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 16:18 - TX Frame Start Delay

pub fn cssetup(&mut self) -> CSSETUP_W<'_>

Bits 20:22 - Chip Select Setup

pub fn ics(&mut self) -> ICS_W<'_>

Bits 24:26 - Inter-character Spacing

pub fn cshold(&mut self) -> CSHOLD_W<'_>

Bits 28:30 - Chip Select Hold

impl W<u32, Reg<u32, _CTRLX>>

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 0 - Debug Halt

pub fn ctsinv(&mut self) -> CTSINV_W<'_>

Bit 1 - CTS Pin Inversion

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 2 - CTS Function Enabled

pub fn rtsinv(&mut self) -> RTSINV_W<'_>

Bit 3 - RTS Pin Inversion

impl W<u32, Reg<u32, _TIMECMP0>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 0

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 0

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP0

impl W<u32, Reg<u32, _TIMECMP1>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 1

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 1

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP1

impl W<u32, Reg<u32, _TIMECMP2>>

pub fn tcmpval(&mut self) -> TCMPVAL_W<'_>

Bits 0:7 - Timer Comparator 2

pub fn tstart(&mut self) -> TSTART_W<'_>

Bits 16:18 - Timer Start Source

pub fn tstop(&mut self) -> TSTOP_W<'_>

Bits 20:22 - Source Used to Disable Comparator 2

pub fn restarten(&mut self) -> RESTARTEN_W<'_>

Bit 24 - Restart Timer on TCMP2

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

pub fn cspen(&mut self) -> CSPEN_W<'_>

Bit 2 - CS Pin Enable

pub fn clkpen(&mut self) -> CLKPEN_W<'_>

Bit 3 - CLK Pin Enable

pub fn ctspen(&mut self) -> CTSPEN_W<'_>

Bit 4 - CTS Pin Enable

pub fn rtspen(&mut self) -> RTSPEN_W<'_>

Bit 5 - RTS Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

pub fn csloc(&mut self) -> CSLOC_W<'_>

Bits 16:21 - I/O Location

pub fn clkloc(&mut self) -> CLKLOC_W<'_>

Bits 24:29 - I/O Location

impl W<u32, Reg<u32, _ROUTELOC1>>

pub fn ctsloc(&mut self) -> CTSLOC_W<'_>

Bits 0:5 - I/O Location

pub fn rtsloc(&mut self) -> RTSLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn autotri(&mut self) -> AUTOTRI_W<'_>

Bit 0 - Automatic Transmitter Tristate

pub fn databits(&mut self) -> DATABITS_W<'_>

Bit 1 - Data-Bit Mode

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 2:3 - Parity-Bit Mode

pub fn stopbits(&mut self) -> STOPBITS_W<'_>

Bit 4 - Stop-Bit Mode

pub fn inv(&mut self) -> INV_W<'_>

Bit 5 - Invert Input and Output

pub fn errsdma(&mut self) -> ERRSDMA_W<'_>

Bit 6 - Clear RX DMA on Error

pub fn loopbk(&mut self) -> LOOPBK_W<'_>

Bit 7 - Loopback Enable

pub fn sfubrx(&mut self) -> SFUBRX_W<'_>

Bit 8 - Start-Frame UnBlock RX

pub fn mpm(&mut self) -> MPM_W<'_>

Bit 9 - Multi-Processor Mode

pub fn mpab(&mut self) -> MPAB_W<'_>

Bit 10 - Multi-Processor Address-Bit

pub fn bit8dv(&mut self) -> BIT8DV_W<'_>

Bit 11 - Bit 8 Default Value

pub fn rxdmawu(&mut self) -> RXDMAWU_W<'_>

Bit 12 - RX DMA Wakeup

pub fn txdmawu(&mut self) -> TXDMAWU_W<'_>

Bit 13 - TX DMA Wakeup

pub fn txdelay(&mut self) -> TXDELAY_W<'_>

Bits 14:15 - TX Delay Transmission

impl W<u32, Reg<u32, _CMD>>

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 0 - Receiver Enable

pub fn rxdis(&mut self) -> RXDIS_W<'_>

Bit 1 - Receiver Disable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 2 - Transmitter Enable

pub fn txdis(&mut self) -> TXDIS_W<'_>

Bit 3 - Transmitter Disable

pub fn rxblocken(&mut self) -> RXBLOCKEN_W<'_>

Bit 4 - Receiver Block Enable

pub fn rxblockdis(&mut self) -> RXBLOCKDIS_W<'_>

Bit 5 - Receiver Block Disable

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearrx(&mut self) -> CLEARRX_W<'_>

Bit 7 - Clear RX

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 3:16 - Fractional Clock Divider

impl W<u32, Reg<u32, _STARTFRAME>>

pub fn startframe(&mut self) -> STARTFRAME_W<'_>

Bits 0:8 - Start Frame

impl W<u32, Reg<u32, _SIGFRAME>>

pub fn sigframe(&mut self) -> SIGFRAME_W<'_>

Bits 0:8 - Signal Frame

impl W<u32, Reg<u32, _TXDATAX>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:8 - TX Data

pub fn txbreak(&mut self) -> TXBREAK_W<'_>

Bit 13 - Transmit Data as Break

pub fn txdisat(&mut self) -> TXDISAT_W<'_>

Bit 14 - Disable TX After Transmission

pub fn rxenat(&mut self) -> RXENAT_W<'_>

Bit 15 - Enable RX After Transmission

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Set TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Set RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Set RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Set TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Set PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Set FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Set MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Set STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Set SIGF Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - Clear TXC Interrupt Flag

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - Clear RXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - Clear RXUF Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - Clear TXOF Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - Clear PERR Interrupt Flag

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - Clear FERR Interrupt Flag

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - Clear MPAF Interrupt Flag

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - Clear STARTF Interrupt Flag

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - Clear SIGF Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn txc(&mut self) -> TXC_W<'_>

Bit 0 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 1 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 2 - RXDATAV Interrupt Enable

pub fn rxof(&mut self) -> RXOF_W<'_>

Bit 3 - RXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 4 - RXUF Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 5 - TXOF Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 6 - PERR Interrupt Enable

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 7 - FERR Interrupt Enable

pub fn mpaf(&mut self) -> MPAF_W<'_>

Bit 8 - MPAF Interrupt Enable

pub fn startf(&mut self) -> STARTF_W<'_>

Bit 9 - STARTF Interrupt Enable

pub fn sigf(&mut self) -> SIGF_W<'_>

Bit 10 - SIGF Interrupt Enable

impl W<u32, Reg<u32, _PULSECTRL>>

pub fn pulsew(&mut self) -> PULSEW_W<'_>

Bits 0:3 - Pulse Width

pub fn pulseen(&mut self) -> PULSEEN_W<'_>

Bit 4 - Pulse Generator/Extender Enable

pub fn pulsefilt(&mut self) -> PULSEFILT_W<'_>

Bit 5 - Pulse Filter

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn rxpen(&mut self) -> RXPEN_W<'_>

Bit 0 - RX Pin Enable

pub fn txpen(&mut self) -> TXPEN_W<'_>

Bit 1 - TX Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn rxloc(&mut self) -> RXLOC_W<'_>

Bits 0:5 - I/O Location

pub fn txloc(&mut self) -> TXLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _INPUT>>

pub fn rxprssel(&mut self) -> RXPRSSEL_W<'_>

Bits 0:3 - RX PRS Channel Select

pub fn rxprs(&mut self) -> RXPRS_W<'_>

Bit 5 - PRS RX Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn repmode(&mut self) -> REPMODE_W<'_>

Bits 0:1 - Repeat Mode

pub fn ufoa0(&mut self) -> UFOA0_W<'_>

Bits 2:3 - Underflow Output Action 0

pub fn ufoa1(&mut self) -> UFOA1_W<'_>

Bits 4:5 - Underflow Output Action 1

pub fn opol0(&mut self) -> OPOL0_W<'_>

Bit 6 - Output 0 Polarity

pub fn opol1(&mut self) -> OPOL1_W<'_>

Bit 7 - Output 1 Polarity

pub fn buftop(&mut self) -> BUFTOP_W<'_>

Bit 8 - Buffered Top

pub fn comp0top(&mut self) -> COMP0TOP_W<'_>

Bit 9 - Compare Value 0 is Top Value

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 12 - Debug Mode Run Enable

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start LETIMER

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop LETIMER

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 2 - Clear LETIMER

pub fn cto0(&mut self) -> CTO0_W<'_>

Bit 3 - Clear Toggle Output 0

pub fn cto1(&mut self) -> CTO1_W<'_>

Bit 4 - Clear Toggle Output 1

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _COMP0>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:15 - Compare Value 0

impl W<u32, Reg<u32, _COMP1>>

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 0:15 - Compare Value 1

impl W<u32, Reg<u32, _REP0>>

pub fn rep0(&mut self) -> REP0_W<'_>

Bits 0:7 - Repeat Counter 0

impl W<u32, Reg<u32, _REP1>>

pub fn rep1(&mut self) -> REP1_W<'_>

Bits 0:7 - Repeat Counter 1

impl W<u32, Reg<u32, _IFS>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Set COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Set COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Set UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Set REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Set REP1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Clear COMP0 Interrupt Flag

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Clear COMP1 Interrupt Flag

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - Clear UF Interrupt Flag

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - Clear REP0 Interrupt Flag

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - Clear REP1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - COMP0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - COMP1 Interrupt Enable

pub fn uf(&mut self) -> UF_W<'_>

Bit 2 - UF Interrupt Enable

pub fn rep0(&mut self) -> REP0_W<'_>

Bit 3 - REP0 Interrupt Enable

pub fn rep1(&mut self) -> REP1_W<'_>

Bit 4 - REP1 Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn out0pen(&mut self) -> OUT0PEN_W<'_>

Bit 0 - Output 0 Pin Enable

pub fn out1pen(&mut self) -> OUT1PEN_W<'_>

Bit 1 - Output 1 Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn out0loc(&mut self) -> OUT0LOC_W<'_>

Bits 0:5 - I/O Location

pub fn out1loc(&mut self) -> OUT1LOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _PRSSEL>>

pub fn prsstartsel(&mut self) -> PRSSTARTSEL_W<'_>

Bits 0:3 - PRS Start Select

pub fn prsstopsel(&mut self) -> PRSSTOPSEL_W<'_>

Bits 6:9 - PRS Stop Select

pub fn prsclearsel(&mut self) -> PRSCLEARSEL_W<'_>

Bits 12:15 - PRS Clear Select

pub fn prsstartmode(&mut self) -> PRSSTARTMODE_W<'_>

Bits 18:19 - PRS Start Mode

pub fn prsstopmode(&mut self) -> PRSSTOPMODE_W<'_>

Bits 22:23 - PRS Stop Mode

pub fn prsclearmode(&mut self) -> PRSCLEARMODE_W<'_>

Bits 26:27 - PRS Clear Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable CRYOTIMER

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn oscsel(&mut self) -> OSCSEL_W<'_>

Bits 2:3 - Select Low Frequency Oscillator

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 5:7 - Prescaler Setting

impl W<u32, Reg<u32, _PERIODSEL>>

pub fn periodsel(&mut self) -> PERIODSEL_W<'_>

Bits 0:5 - Interrupts/Wakeup Events Period Setting

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 0 - EM4 Wake-up Enable

impl W<u32, Reg<u32, _IFS>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - Set PERIOD Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - Clear PERIOD Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn period(&mut self) -> PERIOD_W<'_>

Bit 0 - PERIOD Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:2 - Mode Select

pub fn filt(&mut self) -> FILT_W<'_>

Bit 3 - Enable Digital Pulse Width Filter

pub fn rsten(&mut self) -> RSTEN_W<'_>

Bit 4 - Enable PCNT Clock Domain Reset

pub fn cntrsten(&mut self) -> CNTRSTEN_W<'_>

Bit 5 - Enable CNT Reset

pub fn auxcntrsten(&mut self) -> AUXCNTRSTEN_W<'_>

Bit 6 - Enable AUXCNT Reset

pub fn debughalt(&mut self) -> DEBUGHALT_W<'_>

Bit 7 - Debug Mode Halt Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 8 - Enable Hysteresis

pub fn s1cdir(&mut self) -> S1CDIR_W<'_>

Bit 9 - Count Direction Determined By S1

pub fn cntev(&mut self) -> CNTEV_W<'_>

Bits 10:11 - Controls When the Counter Counts

pub fn auxcntev(&mut self) -> AUXCNTEV_W<'_>

Bits 12:13 - Controls When the Auxiliary Counter Counts

pub fn cntdir(&mut self) -> CNTDIR_W<'_>

Bit 14 - Non-Quadrature Mode Counter Direction Control

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 15 - Edge Select

pub fn tccmode(&mut self) -> TCCMODE_W<'_>

Bits 16:17 - Sets the Mode for Triggered Compare and Clear

pub fn tccpresc(&mut self) -> TCCPRESC_W<'_>

Bits 19:20 - Set the LFA Prescaler for Triggered Compare and Clear

pub fn tcccomp(&mut self) -> TCCCOMP_W<'_>

Bits 22:23 - Triggered Compare and Clear Compare Mode

pub fn prsgateen(&mut self) -> PRSGATEEN_W<'_>

Bit 24 - PRS Gate Enable

pub fn tccprspol(&mut self) -> TCCPRSPOL_W<'_>

Bit 25 - TCC PRS Polarity Select

pub fn tccprssel(&mut self) -> TCCPRSSEL_W<'_>

Bits 26:29 - TCC PRS Channel Select

pub fn topbhfsel(&mut self) -> TOPBHFSEL_W<'_>

Bit 31 - TOPB High Frequency Value Select

impl W<u32, Reg<u32, _CMD>>

pub fn lcntim(&mut self) -> LCNTIM_W<'_>

Bit 0 - Load CNT Immediately

pub fn ltopbim(&mut self) -> LTOPBIM_W<'_>

Bit 1 - Load TOPB Immediately

impl W<u32, Reg<u32, _TOPB>>

pub fn topb(&mut self) -> TOPB_W<'_>

Bits 0:15 - Counter Top Buffer

impl W<u32, Reg<u32, _IFS>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Set UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Set OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Set DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Set AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Set TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Set OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - Clear UF Interrupt Flag

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - Clear OF Interrupt Flag

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - Clear DIRCNG Interrupt Flag

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - Clear AUXOF Interrupt Flag

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - Clear TCC Interrupt Flag

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - Clear OQSTERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn uf(&mut self) -> UF_W<'_>

Bit 0 - UF Interrupt Enable

pub fn of(&mut self) -> OF_W<'_>

Bit 1 - OF Interrupt Enable

pub fn dircng(&mut self) -> DIRCNG_W<'_>

Bit 2 - DIRCNG Interrupt Enable

pub fn auxof(&mut self) -> AUXOF_W<'_>

Bit 3 - AUXOF Interrupt Enable

pub fn tcc(&mut self) -> TCC_W<'_>

Bit 4 - TCC Interrupt Enable

pub fn oqsterr(&mut self) -> OQSTERR_W<'_>

Bit 5 - OQSTERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn s0inloc(&mut self) -> S0INLOC_W<'_>

Bits 0:5 - I/O Location

pub fn s1inloc(&mut self) -> S1INLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _FREEZE>>

pub fn regfreeze(&mut self) -> REGFREEZE_W<'_>

Bit 0 - Register Update Freeze

impl W<u32, Reg<u32, _INPUT>>

pub fn s0prssel(&mut self) -> S0PRSSEL_W<'_>

Bits 0:3 - S0IN PRS Channel Select

pub fn s0prsen(&mut self) -> S0PRSEN_W<'_>

Bit 5 - S0IN PRS Enable

pub fn s1prssel(&mut self) -> S1PRSSEL_W<'_>

Bits 6:9 - S1IN PRS Channel Select

pub fn s1prsen(&mut self) -> S1PRSEN_W<'_>

Bit 11 - S1IN PRS Enable

impl W<u32, Reg<u32, _OVSCFG>>

pub fn filtlen(&mut self) -> FILTLEN_W<'_>

Bits 0:7 - Configure Filter Length for Inputs S0IN and S1IN

pub fn flutterrm(&mut self) -> FLUTTERRM_W<'_>

Bit 12 - Flutter Remove

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - I2C Enable

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Addressable as Slave

pub fn autoack(&mut self) -> AUTOACK_W<'_>

Bit 2 - Automatic Acknowledge

pub fn autose(&mut self) -> AUTOSE_W<'_>

Bit 3 - Automatic STOP When Empty

pub fn autosn(&mut self) -> AUTOSN_W<'_>

Bit 4 - Automatic STOP on NACK

pub fn arbdis(&mut self) -> ARBDIS_W<'_>

Bit 5 - Arbitration Disable

pub fn gcamen(&mut self) -> GCAMEN_W<'_>

Bit 6 - General Call Address Match Enable

pub fn txbil(&mut self) -> TXBIL_W<'_>

Bit 7 - TX Buffer Interrupt Level

pub fn clhr(&mut self) -> CLHR_W<'_>

Bits 8:9 - Clock Low High Ratio

pub fn bito(&mut self) -> BITO_W<'_>

Bits 12:13 - Bus Idle Timeout

pub fn gibito(&mut self) -> GIBITO_W<'_>

Bit 15 - Go Idle on Bus Idle Timeout

pub fn clto(&mut self) -> CLTO_W<'_>

Bits 16:18 - Clock Low Timeout

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Send Start Condition

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Send Stop Condition

pub fn ack(&mut self) -> ACK_W<'_>

Bit 2 - Send ACK

pub fn nack(&mut self) -> NACK_W<'_>

Bit 3 - Send NACK

pub fn cont(&mut self) -> CONT_W<'_>

Bit 4 - Continue Transmission

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 5 - Abort Transmission

pub fn cleartx(&mut self) -> CLEARTX_W<'_>

Bit 6 - Clear TX

pub fn clearpc(&mut self) -> CLEARPC_W<'_>

Bit 7 - Clear Pending Commands

impl W<u32, Reg<u32, _CLKDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:8 - Clock Divider

impl W<u32, Reg<u32, _SADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:7 - Slave Address

impl W<u32, Reg<u32, _SADDRMASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 1:7 - Slave Address Mask

impl W<u32, Reg<u32, _TXDATA>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - TX Data

impl W<u32, Reg<u32, _TXDOUBLE>>

pub fn txdata0(&mut self) -> TXDATA0_W<'_>

Bits 0:7 - TX Data

pub fn txdata1(&mut self) -> TXDATA1_W<'_>

Bits 8:15 - TX Data

impl W<u32, Reg<u32, _IFS>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Set START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Set RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Set ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Set TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Set ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Set NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Set MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Set ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Set BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Set BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Set TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Set RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Set BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Set CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Set SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Set RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Set CLERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Clear START Interrupt Flag

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - Clear RSTART Interrupt Flag

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - Clear ADDR Interrupt Flag

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - Clear TXC Interrupt Flag

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - Clear ACK Interrupt Flag

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - Clear NACK Interrupt Flag

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - Clear MSTOP Interrupt Flag

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - Clear ARBLOST Interrupt Flag

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - Clear BUSERR Interrupt Flag

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - Clear BUSHOLD Interrupt Flag

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - Clear TXOF Interrupt Flag

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - Clear RXUF Interrupt Flag

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - Clear BITO Interrupt Flag

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - Clear CLTO Interrupt Flag

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - Clear SSTOP Interrupt Flag

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - Clear RXFULL Interrupt Flag

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - Clear CLERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - START Interrupt Enable

pub fn rstart(&mut self) -> RSTART_W<'_>

Bit 1 - RSTART Interrupt Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bit 2 - ADDR Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 3 - TXC Interrupt Enable

pub fn txbl(&mut self) -> TXBL_W<'_>

Bit 4 - TXBL Interrupt Enable

pub fn rxdatav(&mut self) -> RXDATAV_W<'_>

Bit 5 - RXDATAV Interrupt Enable

pub fn ack(&mut self) -> ACK_W<'_>

Bit 6 - ACK Interrupt Enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 7 - NACK Interrupt Enable

pub fn mstop(&mut self) -> MSTOP_W<'_>

Bit 8 - MSTOP Interrupt Enable

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 9 - ARBLOST Interrupt Enable

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 10 - BUSERR Interrupt Enable

pub fn bushold(&mut self) -> BUSHOLD_W<'_>

Bit 11 - BUSHOLD Interrupt Enable

pub fn txof(&mut self) -> TXOF_W<'_>

Bit 12 - TXOF Interrupt Enable

pub fn rxuf(&mut self) -> RXUF_W<'_>

Bit 13 - RXUF Interrupt Enable

pub fn bito(&mut self) -> BITO_W<'_>

Bit 14 - BITO Interrupt Enable

pub fn clto(&mut self) -> CLTO_W<'_>

Bit 15 - CLTO Interrupt Enable

pub fn sstop(&mut self) -> SSTOP_W<'_>

Bit 16 - SSTOP Interrupt Enable

pub fn rxfull(&mut self) -> RXFULL_W<'_>

Bit 17 - RXFULL Interrupt Enable

pub fn clerr(&mut self) -> CLERR_W<'_>

Bit 18 - CLERR Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn sdapen(&mut self) -> SDAPEN_W<'_>

Bit 0 - SDA Pin Enable

pub fn sclpen(&mut self) -> SCLPEN_W<'_>

Bit 1 - SCL Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn sdaloc(&mut self) -> SDALOC_W<'_>

Bits 0:5 - I/O Location

pub fn sclloc(&mut self) -> SCLLOC_W<'_>

Bits 8:13 - I/O Location

impl W<u32, Reg<u32, _CTRL>>

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bits 0:1 - Warm-up Mode

pub fn singledmawu(&mut self) -> SINGLEDMAWU_W<'_>

Bit 2 - SINGLEFIFO DMA Wakeup

pub fn scandmawu(&mut self) -> SCANDMAWU_W<'_>

Bit 3 - SCANFIFO DMA Wakeup

pub fn tailgate(&mut self) -> TAILGATE_W<'_>

Bit 4 - Conversion Tailgating

pub fn asyncclken(&mut self) -> ASYNCCLKEN_W<'_>

Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1

pub fn adcclkmode(&mut self) -> ADCCLKMODE_W<'_>

Bit 7 - ADC Clock Mode

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock

pub fn timebase(&mut self) -> TIMEBASE_W<'_>

Bits 16:22 - 1us Time Base

pub fn ovsrsel(&mut self) -> OVSRSEL_W<'_>

Bits 24:27 - Oversample Rate Select

pub fn dbghalt(&mut self) -> DBGHALT_W<'_>

Bit 28 - Debug Mode Halt Enable

pub fn chconmode(&mut self) -> CHCONMODE_W<'_>

Bit 29 - Channel Connect

pub fn chconrefwarmidle(&mut self) -> CHCONREFWARMIDLE_W<'_>

Bits 30:31 - Channel Connect and Reference Warm Sel When ADC is IDLE

impl W<u32, Reg<u32, _CMD>>

pub fn singlestart(&mut self) -> SINGLESTART_W<'_>

Bit 0 - Single Channel Conversion Start

pub fn singlestop(&mut self) -> SINGLESTOP_W<'_>

Bit 1 - Single Channel Conversion Stop

pub fn scanstart(&mut self) -> SCANSTART_W<'_>

Bit 2 - Scan Sequence Start

pub fn scanstop(&mut self) -> SCANSTOP_W<'_>

Bit 3 - Scan Sequence Stop

impl W<u32, Reg<u32, _SINGLECTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Single Channel Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Single Channel Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Single Channel Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Single Channel Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Single Channel Reference Selection

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 8:15 - Single Channel Positive Input Selection

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 16:23 - Single Channel Negative Input Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Single Channel Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Single Channel PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Single Channel

impl W<u32, Reg<u32, _SINGLECTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Single Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Single Channel DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Single Channel FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Single Channel PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:20 - Single Channel PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SINGLE REP Mode

impl W<u32, Reg<u32, _SCANCTRL>>

pub fn rep(&mut self) -> REP_W<'_>

Bit 0 - Scan Sequence Repetitive Mode

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 1 - Scan Sequence Differential Mode

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 2 - Scan Sequence Result Adjustment

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - Scan Sequence Resolution Select

pub fn ref_(&mut self) -> REF_W<'_>

Bits 5:7 - Scan Sequence Reference Selection

pub fn at(&mut self) -> AT_W<'_>

Bits 24:27 - Scan Acquisition Time

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 29 - Scan Sequence PRS Trigger Enable

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 31 - Compare Logic Enable for Scan

impl W<u32, Reg<u32, _SCANCTRLX>>

pub fn vrefsel(&mut self) -> VREFSEL_W<'_>

Bits 0:2 - Scan Channel Reference Selection

pub fn vrefattfix(&mut self) -> VREFATTFIX_W<'_>

Bit 3 - Enable Fixed Scaling on VREF

pub fn vrefatt(&mut self) -> VREFATT_W<'_>

Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5

pub fn vinatt(&mut self) -> VINATT_W<'_>

Bits 8:11 - Code for VIN Attenuation Factor

pub fn dvl(&mut self) -> DVL_W<'_>

Bits 12:13 - Scan DV Level Select

pub fn fifoofact(&mut self) -> FIFOOFACT_W<'_>

Bit 14 - Scan FIFO Overflow Action

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 16 - Scan PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 17:20 - Scan Sequence PRS Trigger Select

pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W<'_>

Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set

pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W<'_>

Bit 27 - Enable Delaying Next Conversion Start

pub fn repdelay(&mut self) -> REPDELAY_W<'_>

Bits 29:31 - REPDELAY Select for SCAN REP Mode

impl W<u32, Reg<u32, _SCANMASK>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Sequence Input Mask

impl W<u32, Reg<u32, _SCANINPUTSEL>>

pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W<'_>

Bits 0:4 - Inputs Chosen for ADCn_INPUT7-ADCn_INPUT0 as Referred in SCANMASK

pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W<'_>

Bits 8:12 - Inputs Chosen for ADCn_INPUT8-ADCn_INPUT15 as Referred in SCANMASK

pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W<'_>

Bits 16:20 - Inputs Chosen for ADCn_INPUT16-ADCn_INPUT23 as Referred in SCANMASK

pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W<'_>

Bits 24:28 - Inputs Chosen for ADCn_INPUT24-ADCn_INPUT31 as Referred in SCANMASK

impl W<u32, Reg<u32, _SCANNEGSEL>>

pub fn input0negsel(&mut self) -> INPUT0NEGSEL_W<'_>

Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode

pub fn input2negsel(&mut self) -> INPUT2NEGSEL_W<'_>

Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode

pub fn input4negsel(&mut self) -> INPUT4NEGSEL_W<'_>

Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode

pub fn input6negsel(&mut self) -> INPUT6NEGSEL_W<'_>

Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode

pub fn input9negsel(&mut self) -> INPUT9NEGSEL_W<'_>

Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode

pub fn input11negsel(&mut self) -> INPUT11NEGSEL_W<'_>

Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode

pub fn input13negsel(&mut self) -> INPUT13NEGSEL_W<'_>

Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode

pub fn input15negsel(&mut self) -> INPUT15NEGSEL_W<'_>

Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode

impl W<u32, Reg<u32, _CMPTHR>>

pub fn adlt(&mut self) -> ADLT_W<'_>

Bits 0:15 - Less Than Compare Threshold

pub fn adgt(&mut self) -> ADGT_W<'_>

Bits 16:31 - Greater Than Compare Threshold

impl W<u32, Reg<u32, _BIASPROG>>

pub fn adcbiasprog(&mut self) -> ADCBIASPROG_W<'_>

Bits 0:3 - Bias Programming Value of Analog ADC Block

pub fn vfaultclr(&mut self) -> VFAULTCLR_W<'_>

Bit 12 - Clear VREFOF Flag

pub fn gpbiasacc(&mut self) -> GPBIASACC_W<'_>

Bit 16 - Accuracy Setting for the System Bias During ADC Operation

impl W<u32, Reg<u32, _CAL>>

pub fn singleoffset(&mut self) -> SINGLEOFFSET_W<'_>

Bits 0:3 - Single Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn singleoffsetinv(&mut self) -> SINGLEOFFSETINV_W<'_>

Bits 4:7 - Single Mode Offset Calibration Value for Negative Single-ended Mode

pub fn singlegain(&mut self) -> SINGLEGAIN_W<'_>

Bits 8:14 - Single Mode Gain Calibration Value

pub fn offsetinvmode(&mut self) -> OFFSETINVMODE_W<'_>

Bit 15 - Negative Single-ended Offset Calibration is Enabled

pub fn scanoffset(&mut self) -> SCANOFFSET_W<'_>

Bits 16:19 - Scan Mode Offset Calibration Value for Differential or Positive Single-ended Mode

pub fn scanoffsetinv(&mut self) -> SCANOFFSETINV_W<'_>

Bits 20:23 - Scan Mode Offset Calibration Value for Negative Single-ended Mode

pub fn scangain(&mut self) -> SCANGAIN_W<'_>

Bits 24:30 - Scan Mode Gain Calibration Value

pub fn calen(&mut self) -> CALEN_W<'_>

Bit 31 - Calibration Mode is Enabled

impl W<u32, Reg<u32, _IFS>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Set SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Set SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Set SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Set SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Set SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Set SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Set VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Set PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Set SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Set SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Set PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Set EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - Clear SINGLEOF Interrupt Flag

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - Clear SCANOF Interrupt Flag

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - Clear SINGLEUF Interrupt Flag

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - Clear SCANUF Interrupt Flag

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - Clear SINGLECMP Interrupt Flag

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - Clear SCANCMP Interrupt Flag

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - Clear VREFOV Interrupt Flag

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - Clear PROGERR Interrupt Flag

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - Clear SCANEXTPEND Interrupt Flag

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - Clear SCANPEND Interrupt Flag

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - Clear PRSTIMEDERR Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - Clear EM23ERR Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn single(&mut self) -> SINGLE_W<'_>

Bit 0 - SINGLE Interrupt Enable

pub fn scan(&mut self) -> SCAN_W<'_>

Bit 1 - SCAN Interrupt Enable

pub fn singleof(&mut self) -> SINGLEOF_W<'_>

Bit 8 - SINGLEOF Interrupt Enable

pub fn scanof(&mut self) -> SCANOF_W<'_>

Bit 9 - SCANOF Interrupt Enable

pub fn singleuf(&mut self) -> SINGLEUF_W<'_>

Bit 10 - SINGLEUF Interrupt Enable

pub fn scanuf(&mut self) -> SCANUF_W<'_>

Bit 11 - SCANUF Interrupt Enable

pub fn singlecmp(&mut self) -> SINGLECMP_W<'_>

Bit 16 - SINGLECMP Interrupt Enable

pub fn scancmp(&mut self) -> SCANCMP_W<'_>

Bit 17 - SCANCMP Interrupt Enable

pub fn vrefov(&mut self) -> VREFOV_W<'_>

Bit 24 - VREFOV Interrupt Enable

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 25 - PROGERR Interrupt Enable

pub fn scanextpend(&mut self) -> SCANEXTPEND_W<'_>

Bit 26 - SCANEXTPEND Interrupt Enable

pub fn scanpend(&mut self) -> SCANPEND_W<'_>

Bit 27 - SCANPEND Interrupt Enable

pub fn prstimederr(&mut self) -> PRSTIMEDERR_W<'_>

Bit 28 - PRSTIMEDERR Interrupt Enable

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 29 - EM23ERR Interrupt Enable

impl W<u32, Reg<u32, _SINGLEFIFOCLEAR>>

pub fn singlefifoclear(&mut self) -> SINGLEFIFOCLEAR_W<'_>

Bit 0 - Clear Single FIFO Content

impl W<u32, Reg<u32, _SCANFIFOCLEAR>>

pub fn scanfifoclear(&mut self) -> SCANFIFOCLEAR_W<'_>

Bit 0 - Clear Scan FIFO Content

impl W<u32, Reg<u32, _APORTMASTERDIS>>

pub fn aport1xmasterdis(&mut self) -> APORT1XMASTERDIS_W<'_>

Bit 2 - APORT1X Master Disable

pub fn aport1ymasterdis(&mut self) -> APORT1YMASTERDIS_W<'_>

Bit 3 - APORT1Y Master Disable

pub fn aport2xmasterdis(&mut self) -> APORT2XMASTERDIS_W<'_>

Bit 4 - APORT2X Master Disable

pub fn aport2ymasterdis(&mut self) -> APORT2YMASTERDIS_W<'_>

Bit 5 - APORT2Y Master Disable

pub fn aport3xmasterdis(&mut self) -> APORT3XMASTERDIS_W<'_>

Bit 6 - APORT3X Master Disable

pub fn aport3ymasterdis(&mut self) -> APORT3YMASTERDIS_W<'_>

Bit 7 - APORT3Y Master Disable

pub fn aport4xmasterdis(&mut self) -> APORT4XMASTERDIS_W<'_>

Bit 8 - APORT4X Master Disable

pub fn aport4ymasterdis(&mut self) -> APORT4YMASTERDIS_W<'_>

Bit 9 - APORT4Y Master Disable

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Analog Comparator Enable

pub fn inactval(&mut self) -> INACTVAL_W<'_>

Bit 2 - Inactive Value

pub fn gpioinv(&mut self) -> GPIOINV_W<'_>

Bit 3 - Comparator GPIO Output Invert

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 8 - APORT Bus X Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 9 - APORT Bus Y Master Disable

pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W<'_>

Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bits 12:14 - Power Select

pub fn accuracy(&mut self) -> ACCURACY_W<'_>

Bit 15 - ACMP Accuracy Mode

pub fn inputrange(&mut self) -> INPUTRANGE_W<'_>

Bits 18:19 - Input Range

pub fn irise(&mut self) -> IRISE_W<'_>

Bit 20 - Rising Edge Interrupt Sense

pub fn ifall(&mut self) -> IFALL_W<'_>

Bit 21 - Falling Edge Interrupt Sense

pub fn biasprog(&mut self) -> BIASPROG_W<'_>

Bits 24:29 - Bias Configuration

pub fn fullbias(&mut self) -> FULLBIAS_W<'_>

Bit 31 - Full Bias Current

impl W<u32, Reg<u32, _INPUTSEL>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - Positive Input Select

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - Negative Input Select

pub fn vasel(&mut self) -> VASEL_W<'_>

Bits 16:21 - VA Selection

pub fn vbsel(&mut self) -> VBSEL_W<'_>

Bit 22 - VB Selection

pub fn vlpsel(&mut self) -> VLPSEL_W<'_>

Bit 24 - Low-Power Sampled Voltage Selection

pub fn csresen(&mut self) -> CSRESEN_W<'_>

Bit 26 - Capacitive Sense Mode Internal Resistor Enable

pub fn csressel(&mut self) -> CSRESSEL_W<'_>

Bits 28:30 - Capacitive Sense Mode Internal Resistor Select

impl W<u32, Reg<u32, _IFS>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Set EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Set WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - Clear EDGE Interrupt Flag

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - Clear WARMUP Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 0 - EDGE Interrupt Enable

pub fn warmup(&mut self) -> WARMUP_W<'_>

Bit 1 - WARMUP Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 2 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _HYSTERESIS0>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=0

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=0

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=0

impl W<u32, Reg<u32, _HYSTERESIS1>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 0:3 - Hysteresis Select When ACMPOUT=1

pub fn divva(&mut self) -> DIVVA_W<'_>

Bits 16:21 - Divider for VA Voltage When ACMPOUT=1

pub fn divvb(&mut self) -> DIVVB_W<'_>

Bits 24:29 - Divider for VB Voltage When ACMPOUT=1

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn outpen(&mut self) -> OUTPEN_W<'_>

Bit 0 - ACMP Output Pin Enable

impl W<u32, Reg<u32, _ROUTELOC0>>

pub fn outloc(&mut self) -> OUTLOC_W<'_>

Bits 0:5 - I/O Location

impl W<u32, Reg<u32, _EXTIFCTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable External Interface

pub fn aportsel(&mut self) -> APORTSEL_W<'_>

Bits 4:7 - APORT Selection for External Interface

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Current DAC Enable

pub fn cursink(&mut self) -> CURSINK_W<'_>

Bit 1 - Current Sink Enable

pub fn minouttrans(&mut self) -> MINOUTTRANS_W<'_>

Bit 2 - Minimum Output Transition Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 3 - APORT Output Enable

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 4:11 - APORT Output Select

pub fn pwrsel(&mut self) -> PWRSEL_W<'_>

Bit 12 - Power Select

pub fn em2delay(&mut self) -> EM2DELAY_W<'_>

Bit 13 - EM2 Delay

pub fn aportmasterdis(&mut self) -> APORTMASTERDIS_W<'_>

Bit 14 - APORT Bus Master Disable

pub fn aportoutenprs(&mut self) -> APORTOUTENPRS_W<'_>

Bit 16 - PRS Controlled APORT Output Enable

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 18 - Output Enable

pub fn mainoutenprs(&mut self) -> MAINOUTENPRS_W<'_>

Bit 19 - PRS Controlled Main Pad Output Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 20:23 - IDAC Output Enable PRS Channel Select

impl W<u32, Reg<u32, _CURPROG>>

pub fn rangesel(&mut self) -> RANGESEL_W<'_>

Bits 0:1 - Current Range Select

pub fn stepsel(&mut self) -> STEPSEL_W<'_>

Bits 8:12 - Current Step Size Select

pub fn tuning(&mut self) -> TUNING_W<'_>

Bits 16:23 - Tune the Current to Given Accuracy

impl W<u32, Reg<u32, _DUTYCONFIG>>

pub fn em2dutycycledis(&mut self) -> EM2DUTYCYCLEDIS_W<'_>

Bit 1 - Duty Cycle Enable

impl W<u32, Reg<u32, _IFS>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - Set CURSTABLE Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - Clear CURSTABLE Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn curstable(&mut self) -> CURSTABLE_W<'_>

Bit 0 - CURSTABLE Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 1 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 0 - Differential Mode

pub fn sinemode(&mut self) -> SINEMODE_W<'_>

Bit 4 - Sine Mode

pub fn outenprs(&mut self) -> OUTENPRS_W<'_>

Bit 5 - PRS Controlled Output Enable

pub fn ch0prescrst(&mut self) -> CH0PRESCRST_W<'_>

Bit 6 - Channel 0 Start Reset Prescaler

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 8:10 - Reference Selection

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 16:22 - Prescaler Setting for DAC Clock

pub fn refreshperiod(&mut self) -> REFRESHPERIOD_W<'_>

Bits 24:25 - Refresh Period

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bit 28 - Warm-up Mode

pub fn dacclkmode(&mut self) -> DACCLKMODE_W<'_>

Bit 31 - Clock Mode

impl W<u32, Reg<u32, _CH0CTRL>>

pub fn convmode(&mut self) -> CONVMODE_W<'_>

Bit 0 - Conversion Mode

pub fn trigmode(&mut self) -> TRIGMODE_W<'_>

Bits 4:6 - Channel 0 Trigger Mode

pub fn prsasync(&mut self) -> PRSASYNC_W<'_>

Bit 8 - Channel 0 PRS Asynchronous Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 12:15 - Channel 0 PRS Trigger Select

impl W<u32, Reg<u32, _CH1CTRL>>

pub fn convmode(&mut self) -> CONVMODE_W<'_>

Bit 0 - Conversion Mode

pub fn trigmode(&mut self) -> TRIGMODE_W<'_>

Bits 4:6 - Channel 1 Trigger Mode

pub fn prsasync(&mut self) -> PRSASYNC_W<'_>

Bit 8 - Channel 1 PRS Asynchronous Enable

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 12:15 - Channel 1 PRS Trigger Select

impl W<u32, Reg<u32, _CMD>>

pub fn ch0en(&mut self) -> CH0EN_W<'_>

Bit 0 - DAC Channel 0 Enable

pub fn ch0dis(&mut self) -> CH0DIS_W<'_>

Bit 1 - DAC Channel 0 Disable

pub fn ch1en(&mut self) -> CH1EN_W<'_>

Bit 2 - DAC Channel 1 Enable

pub fn ch1dis(&mut self) -> CH1DIS_W<'_>

Bit 3 - DAC Channel 1 Disable

pub fn opa0en(&mut self) -> OPA0EN_W<'_>

Bit 16 - OPA0 Enable

pub fn opa0dis(&mut self) -> OPA0DIS_W<'_>

Bit 17 - OPA0 Disable

pub fn opa1en(&mut self) -> OPA1EN_W<'_>

Bit 18 - OPA1 Enable

pub fn opa1dis(&mut self) -> OPA1DIS_W<'_>

Bit 19 - OPA1 Disable

pub fn opa2en(&mut self) -> OPA2EN_W<'_>

Bit 20 - OPA2 Enable

pub fn opa2dis(&mut self) -> OPA2DIS_W<'_>

Bit 21 - OPA2 Disable

impl W<u32, Reg<u32, _IFS>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - Set CH0CD Interrupt Flag

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - Set CH1CD Interrupt Flag

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - Set CH0OF Interrupt Flag

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - Set CH1OF Interrupt Flag

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - Set CH0UF Interrupt Flag

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - Set CH1UF Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - Set EM23ERR Interrupt Flag

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - Set OPA0APORTCONFLICT Interrupt Flag

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - Set OPA1APORTCONFLICT Interrupt Flag

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - Set OPA2APORTCONFLICT Interrupt Flag

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - Set OPA0PRSTIMEDERR Interrupt Flag

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - Set OPA1PRSTIMEDERR Interrupt Flag

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - Set OPA2PRSTIMEDERR Interrupt Flag

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - Set OPA0OUTVALID Interrupt Flag

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - Set OPA1OUTVALID Interrupt Flag

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - Set OPA2OUTVALID Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - Clear CH0CD Interrupt Flag

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - Clear CH1CD Interrupt Flag

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - Clear CH0OF Interrupt Flag

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - Clear CH1OF Interrupt Flag

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - Clear CH0UF Interrupt Flag

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - Clear CH1UF Interrupt Flag

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - Clear EM23ERR Interrupt Flag

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - Clear OPA0APORTCONFLICT Interrupt Flag

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - Clear OPA1APORTCONFLICT Interrupt Flag

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - Clear OPA2APORTCONFLICT Interrupt Flag

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - Clear OPA0PRSTIMEDERR Interrupt Flag

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - Clear OPA1PRSTIMEDERR Interrupt Flag

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - Clear OPA2PRSTIMEDERR Interrupt Flag

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - Clear OPA0OUTVALID Interrupt Flag

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - Clear OPA1OUTVALID Interrupt Flag

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - Clear OPA2OUTVALID Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ch0cd(&mut self) -> CH0CD_W<'_>

Bit 0 - CH0CD Interrupt Enable

pub fn ch1cd(&mut self) -> CH1CD_W<'_>

Bit 1 - CH1CD Interrupt Enable

pub fn ch0of(&mut self) -> CH0OF_W<'_>

Bit 2 - CH0OF Interrupt Enable

pub fn ch1of(&mut self) -> CH1OF_W<'_>

Bit 3 - CH1OF Interrupt Enable

pub fn ch0uf(&mut self) -> CH0UF_W<'_>

Bit 4 - CH0UF Interrupt Enable

pub fn ch1uf(&mut self) -> CH1UF_W<'_>

Bit 5 - CH1UF Interrupt Enable

pub fn ch0bl(&mut self) -> CH0BL_W<'_>

Bit 6 - CH0BL Interrupt Enable

pub fn ch1bl(&mut self) -> CH1BL_W<'_>

Bit 7 - CH1BL Interrupt Enable

pub fn em23err(&mut self) -> EM23ERR_W<'_>

Bit 15 - EM23ERR Interrupt Enable

pub fn opa0aportconflict(&mut self) -> OPA0APORTCONFLICT_W<'_>

Bit 16 - OPA0APORTCONFLICT Interrupt Enable

pub fn opa1aportconflict(&mut self) -> OPA1APORTCONFLICT_W<'_>

Bit 17 - OPA1APORTCONFLICT Interrupt Enable

pub fn opa2aportconflict(&mut self) -> OPA2APORTCONFLICT_W<'_>

Bit 18 - OPA2APORTCONFLICT Interrupt Enable

pub fn opa0prstimederr(&mut self) -> OPA0PRSTIMEDERR_W<'_>

Bit 20 - OPA0PRSTIMEDERR Interrupt Enable

pub fn opa1prstimederr(&mut self) -> OPA1PRSTIMEDERR_W<'_>

Bit 21 - OPA1PRSTIMEDERR Interrupt Enable

pub fn opa2prstimederr(&mut self) -> OPA2PRSTIMEDERR_W<'_>

Bit 22 - OPA2PRSTIMEDERR Interrupt Enable

pub fn opa0outvalid(&mut self) -> OPA0OUTVALID_W<'_>

Bit 28 - OPA0OUTVALID Interrupt Enable

pub fn opa1outvalid(&mut self) -> OPA1OUTVALID_W<'_>

Bit 29 - OPA1OUTVALID Interrupt Enable

pub fn opa2outvalid(&mut self) -> OPA2OUTVALID_W<'_>

Bit 30 - OPA2OUTVALID Interrupt Enable

impl W<u32, Reg<u32, _CH0DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:11 - Channel 0 Data

impl W<u32, Reg<u32, _CH1DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:11 - Channel 1 Data

impl W<u32, Reg<u32, _COMBDATA>>

pub fn ch0data(&mut self) -> CH0DATA_W<'_>

Bits 0:11 - Channel 0 Data

pub fn ch1data(&mut self) -> CH1DATA_W<'_>

Bits 16:27 - Channel 1 Data

impl W<u32, Reg<u32, _CAL>>

pub fn offsettrim(&mut self) -> OFFSETTRIM_W<'_>

Bits 0:2 - Input Buffer Offset Calibration Value

pub fn gainerrtrim(&mut self) -> GAINERRTRIM_W<'_>

Bits 8:13 - Gain Error Trim Value

pub fn gainerrtrimch1(&mut self) -> GAINERRTRIMCH1_W<'_>

Bits 16:19 - Gain Error Trim Value for CH1

impl W<u32, Reg<u32, _OPA0_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:13 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA0_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA0_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA0_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA0_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _OPA1_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:13 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA1_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA1_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA1_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA1_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _OPA2_CTRL>>

pub fn drivestrength(&mut self) -> DRIVESTRENGTH_W<'_>

Bits 0:1 - OPAx Operation Mode

pub fn incbw(&mut self) -> INCBW_W<'_>

Bit 2 - OPAx Unity Gain Bandwidth Scale

pub fn hcmdis(&mut self) -> HCMDIS_W<'_>

Bit 3 - High Common Mode Disable

pub fn outscale(&mut self) -> OUTSCALE_W<'_>

Bit 4 - Scale OPAx Output Driving Strength

pub fn prsen(&mut self) -> PRSEN_W<'_>

Bit 8 - OPAx PRS Trigger Enable

pub fn prsmode(&mut self) -> PRSMODE_W<'_>

Bit 9 - OPAx PRS Trigger Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 10:13 - OPAx PRS Trigger Select

pub fn prsoutmode(&mut self) -> PRSOUTMODE_W<'_>

Bit 16 - OPAx PRS Output Select

pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W<'_>

Bit 20 - APORT Bus Master Disable

pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W<'_>

Bit 21 - APORT Bus Master Disable

impl W<u32, Reg<u32, _OPA2_TIMER>>

pub fn startupdly(&mut self) -> STARTUPDLY_W<'_>

Bits 0:5 - OPAx Startup Delay Count Value

pub fn warmuptime(&mut self) -> WARMUPTIME_W<'_>

Bits 8:14 - OPAx Warmup Time Count Value

pub fn settletime(&mut self) -> SETTLETIME_W<'_>

Bits 16:25 - OPAx Output Settling Timeout Value

impl W<u32, Reg<u32, _OPA2_MUX>>

pub fn possel(&mut self) -> POSSEL_W<'_>

Bits 0:7 - OPAx Non-inverting Input Mux

pub fn negsel(&mut self) -> NEGSEL_W<'_>

Bits 8:15 - OPAx Inverting Input Mux

pub fn resinmux(&mut self) -> RESINMUX_W<'_>

Bits 16:18 - OPAx Resistor Ladder Input Mux

pub fn gain3x(&mut self) -> GAIN3X_W<'_>

Bit 20 - OPAx Dedicated 3x Gain Resistor Ladder

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 24:26 - OPAx Resistor Ladder Select

impl W<u32, Reg<u32, _OPA2_OUT>>

pub fn mainouten(&mut self) -> MAINOUTEN_W<'_>

Bit 0 - OPAx Main Output Enable

pub fn altouten(&mut self) -> ALTOUTEN_W<'_>

Bit 1 - OPAx Alternative Output Enable

pub fn aportouten(&mut self) -> APORTOUTEN_W<'_>

Bit 2 - OPAx Aport Output Enable

pub fn short(&mut self) -> SHORT_W<'_>

Bit 3 - OPAx Main and Alternative Output Short

pub fn altoutpaden(&mut self) -> ALTOUTPADEN_W<'_>

Bits 4:8 - OPAx Output Enable Value

pub fn aportoutsel(&mut self) -> APORTOUTSEL_W<'_>

Bits 16:23 - OPAx APORT Output

impl W<u32, Reg<u32, _OPA2_CAL>>

pub fn cm1(&mut self) -> CM1_W<'_>

Bits 0:3 - Compensation Cap Cm1 Trim Value

pub fn cm2(&mut self) -> CM2_W<'_>

Bits 5:8 - Compensation Cap Cm2 Trim Value

pub fn cm3(&mut self) -> CM3_W<'_>

Bits 10:11 - Compensation Cap Cm3 Trim Value

pub fn gm(&mut self) -> GM_W<'_>

Bits 13:15 - Gm Trim Value

pub fn gm3(&mut self) -> GM3_W<'_>

Bits 17:18 - Gm3 Trim Value

pub fn offsetp(&mut self) -> OFFSETP_W<'_>

Bits 20:24 - OPAx Non-Inverting Input Offset Configuration Value

pub fn offsetn(&mut self) -> OFFSETN_W<'_>

Bits 26:30 - OPAx Inverting Input Offset Configuration Value

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 1 - CSEN Enable

pub fn cmppol(&mut self) -> CMPPOL_W<'_>

Bit 2 - CSEN Digital Comparator Polarity Select

pub fn cm(&mut self) -> CM_W<'_>

Bits 4:5 - CSEN Conversion Mode Select

pub fn sarcr(&mut self) -> SARCR_W<'_>

Bits 8:9 - SAR Conversion Resolution.

pub fn acu(&mut self) -> ACU_W<'_>

Bits 12:14 - CSEN Accumulator Mode Select

pub fn mcen(&mut self) -> MCEN_W<'_>

Bit 15 - CSEN Multiple Channel Enable

pub fn stm(&mut self) -> STM_W<'_>

Bits 16:17 - Start Trigger Select

pub fn cmpen(&mut self) -> CMPEN_W<'_>

Bit 18 - CSEN Digital Comparator Enable

pub fn drsf(&mut self) -> DRSF_W<'_>

Bit 19 - CSEN Disable Right-Shift

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 20 - CSEN DMA Enable Bit

pub fn convsel(&mut self) -> CONVSEL_W<'_>

Bit 21 - CSEN Converter Select

pub fn chopen(&mut self) -> CHOPEN_W<'_>

Bit 22 - CSEN Chop Enable

pub fn autognd(&mut self) -> AUTOGND_W<'_>

Bit 23 - CSEN Automatic Ground Enable

pub fn mxuc(&mut self) -> MXUC_W<'_>

Bit 24 - CSEN Mux Disconnect

pub fn emacmpen(&mut self) -> EMACMPEN_W<'_>

Bit 25 - Greater and Less Than Comparison Using the Exponential Moving Average (EMA) is Enabled

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bit 26 - Select Warmup Mode for CSEN

pub fn localsens(&mut self) -> LOCALSENS_W<'_>

Bit 27 - Local Sensing Enable

pub fn cpaccuracy(&mut self) -> CPACCURACY_W<'_>

Bit 28 - Charge Pump Accuracy

impl W<u32, Reg<u32, _TIMCTRL>>

pub fn pcpresc(&mut self) -> PCPRESC_W<'_>

Bits 0:2 - Period Counter Prescaler

pub fn pctop(&mut self) -> PCTOP_W<'_>

Bits 8:15 - Period Counter Top Value

pub fn warmupcnt(&mut self) -> WARMUPCNT_W<'_>

Bits 16:17 - Warmup Period Counter

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Software-Triggered Conversions

impl W<u32, Reg<u32, _PRSSEL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:3 - PRS Channel Select

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Output Data

impl W<u32, Reg<u32, _SCANMASK0>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Channel Mask

impl W<u32, Reg<u32, _SCANINPUTSEL0>>

pub fn input0to7sel(&mut self) -> INPUT0TO7SEL_W<'_>

Bits 0:3 - CSEN_INPUT0-7 Select

pub fn input8to15sel(&mut self) -> INPUT8TO15SEL_W<'_>

Bits 8:11 - CSEN_INPUT8-15 Select

pub fn input16to23sel(&mut self) -> INPUT16TO23SEL_W<'_>

Bits 16:19 - CSEN_INPUT16-23 Select

pub fn input24to31sel(&mut self) -> INPUT24TO31SEL_W<'_>

Bits 24:27 - CSEN_INPUT24-31 Select

impl W<u32, Reg<u32, _SCANMASK1>>

pub fn scaninputen(&mut self) -> SCANINPUTEN_W<'_>

Bits 0:31 - Scan Channel Mask.

impl W<u32, Reg<u32, _SCANINPUTSEL1>>

pub fn input32to39sel(&mut self) -> INPUT32TO39SEL_W<'_>

Bits 0:3 - CSEN_INPUT32-39 Select

pub fn input40to47sel(&mut self) -> INPUT40TO47SEL_W<'_>

Bits 8:11 - CSEN_INPUT40-47 Select

pub fn input48to55sel(&mut self) -> INPUT48TO55SEL_W<'_>

Bits 16:19 - CSEN_INPUT48-55 Select

pub fn input56to63sel(&mut self) -> INPUT56TO63SEL_W<'_>

Bits 24:27 - CSEN_INPUT56-63 Select

impl W<u32, Reg<u32, _CMPTHR>>

pub fn cmpthr(&mut self) -> CMPTHR_W<'_>

Bits 0:15 - Comparator Threshold.

impl W<u32, Reg<u32, _EMA>>

pub fn ema(&mut self) -> EMA_W<'_>

Bits 0:21 - Calculated Exponential Moving Average

impl W<u32, Reg<u32, _EMACTRL>>

pub fn emasample(&mut self) -> EMASAMPLE_W<'_>

Bits 0:2 - EMA Sample Weight

impl W<u32, Reg<u32, _SINGLECTRL>>

pub fn singlesel(&mut self) -> SINGLESEL_W<'_>

Bits 4:10 - Single Channel Input Select

impl W<u32, Reg<u32, _DMBASELINE>>

pub fn baselineup(&mut self) -> BASELINEUP_W<'_>

Bits 0:15 - Delta Modulator Integrator Initial Value

pub fn baselinedn(&mut self) -> BASELINEDN_W<'_>

Bits 16:31 - Delta Modulator Integrator Initial Value

impl W<u32, Reg<u32, _DMCFG>>

pub fn dmg(&mut self) -> DMG_W<'_>

Bits 0:7 - Delta Modulator Gain Step

pub fn dmr(&mut self) -> DMR_W<'_>

Bits 8:11 - Delta Modulator Gain Reduction Interval

pub fn dmcr(&mut self) -> DMCR_W<'_>

Bits 16:19 - Delta Modulator Conversion Rate

pub fn crmode(&mut self) -> CRMODE_W<'_>

Bits 20:21 - Delta Modulator Conversion Resolution.

pub fn dmgrdis(&mut self) -> DMGRDIS_W<'_>

Bit 28 - Delta Modulation Gain Step Reduction Disable

impl W<u32, Reg<u32, _ANACTRL>>

pub fn irefprog(&mut self) -> IREFPROG_W<'_>

Bits 4:6 - Reference Current Control.

pub fn idacirefs(&mut self) -> IDACIREFS_W<'_>

Bits 8:10 - Current DAC and Reference Current Scale

pub fn trstprog(&mut self) -> TRSTPROG_W<'_>

Bits 20:22 - Reset Timing

impl W<u32, Reg<u32, _IFS>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - Set CMP Interrupt Flag

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - Set CONV Interrupt Flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - Set EOS Interrupt Flag

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - Set DMAOF Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - Set APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - Clear CMP Interrupt Flag

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - Clear CONV Interrupt Flag

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - Clear EOS Interrupt Flag

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - Clear DMAOF Interrupt Flag

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - Clear APORTCONFLICT Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bit 0 - CMP Interrupt Enable

pub fn conv(&mut self) -> CONV_W<'_>

Bit 1 - CONV Interrupt Enable

pub fn eos(&mut self) -> EOS_W<'_>

Bit 2 - EOS Interrupt Enable

pub fn dmaof(&mut self) -> DMAOF_W<'_>

Bit 3 - DMAOF Interrupt Enable

pub fn aportconflict(&mut self) -> APORTCONFLICT_W<'_>

Bit 4 - APORTCONFLICT Interrupt Enable

impl W<u32, Reg<u32, _CTRL>>

pub fn scanmode(&mut self) -> SCANMODE_W<'_>

Bits 0:1 - Configure Scan Mode

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 2:5 - Scan Start PRS Select

pub fn scanconf(&mut self) -> SCANCONF_W<'_>

Bits 7:8 - Select Scan Configuration

pub fn altexmap(&mut self) -> ALTEXMAP_W<'_>

Bit 11 - Alternative Excitation Map

pub fn dualsample(&mut self) -> DUALSAMPLE_W<'_>

Bit 13 - Enable Dual Sample Mode

pub fn bufow(&mut self) -> BUFOW_W<'_>

Bit 16 - Result Buffer Overwrite

pub fn strscanres(&mut self) -> STRSCANRES_W<'_>

Bit 17 - Enable Storing of SCANRES

pub fn bufidl(&mut self) -> BUFIDL_W<'_>

Bit 19 - Result Buffer Interrupt and DMA Trigger Level

pub fn dmawu(&mut self) -> DMAWU_W<'_>

Bits 20:21 - DMA Wake-up From EM2

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 22 - Debug Mode Run Enable

impl W<u32, Reg<u32, _TIMCTRL>>

pub fn auxpresc(&mut self) -> AUXPRESC_W<'_>

Bits 0:1 - Prescaling Factor for High Frequency Timer

pub fn lfpresc(&mut self) -> LFPRESC_W<'_>

Bits 4:6 - Prescaling Factor for Low Frequency Timer

pub fn pcpresc(&mut self) -> PCPRESC_W<'_>

Bits 8:10 - Period Counter Prescaling

pub fn pctop(&mut self) -> PCTOP_W<'_>

Bits 12:19 - Period Counter Top Value

pub fn startdly(&mut self) -> STARTDLY_W<'_>

Bits 22:23 - Start Delay Configuration

pub fn auxstartup(&mut self) -> AUXSTARTUP_W<'_>

Bit 28 - AUXHFRCO Startup Configuration

impl W<u32, Reg<u32, _PERCTRL>>

pub fn dacch0en(&mut self) -> DACCH0EN_W<'_>

Bit 0 - VDAC CH0 Enable

pub fn dacch1en(&mut self) -> DACCH1EN_W<'_>

Bit 1 - VDAC CH1 Enable

pub fn dacch0data(&mut self) -> DACCH0DATA_W<'_>

Bit 2 - VDAC CH0 Data Selection

pub fn dacch1data(&mut self) -> DACCH1DATA_W<'_>

Bit 3 - VDAC CH1 Data Selection

pub fn dacstartup(&mut self) -> DACSTARTUP_W<'_>

Bit 6 - VDAC Startup Configuration

pub fn dacconvtrig(&mut self) -> DACCONVTRIG_W<'_>

Bit 8 - VDAC Conversion Trigger Configuration

pub fn acmp0mode(&mut self) -> ACMP0MODE_W<'_>

Bits 20:21 - ACMP0 Mode

pub fn acmp1mode(&mut self) -> ACMP1MODE_W<'_>

Bits 22:23 - ACMP1 Mode

pub fn acmp0inv(&mut self) -> ACMP0INV_W<'_>

Bit 24 - Invert Analog Comparator 0 Output

pub fn acmp1inv(&mut self) -> ACMP1INV_W<'_>

Bit 25 - Invert Analog Comparator 1 Output

pub fn acmp0hysten(&mut self) -> ACMP0HYSTEN_W<'_>

Bit 26 - ACMP0 Hysteresis Enable

pub fn acmp1hysten(&mut self) -> ACMP1HYSTEN_W<'_>

Bit 27 - ACMP1 Hysteresis Enable

pub fn warmupmode(&mut self) -> WARMUPMODE_W<'_>

Bits 28:29 - ACMP and VDAC Duty Cycle Mode

impl W<u32, Reg<u32, _DECCTRL>>

pub fn disable(&mut self) -> DISABLE_W<'_>

Bit 0 - Disable the Decoder

pub fn errchk(&mut self) -> ERRCHK_W<'_>

Bit 1 - Enable Check of Current State

pub fn intmap(&mut self) -> INTMAP_W<'_>

Bit 2 - Enable Decoder to Channel Interrupt Mapping

pub fn hystprs0(&mut self) -> HYSTPRS0_W<'_>

Bit 3 - Enable Decoder Hysteresis on PRS0 Output

pub fn hystprs1(&mut self) -> HYSTPRS1_W<'_>

Bit 4 - Enable Decoder Hysteresis on PRS1 Output

pub fn hystprs2(&mut self) -> HYSTPRS2_W<'_>

Bit 5 - Enable Decoder Hysteresis on PRS2 Output

pub fn hystirq(&mut self) -> HYSTIRQ_W<'_>

Bit 6 - Enable Decoder Hysteresis on Interrupt Requests

pub fn prscnt(&mut self) -> PRSCNT_W<'_>

Bit 7 - Enable Count Mode on Decoder PRS Channels 0 and 1

pub fn input(&mut self) -> INPUT_W<'_>

Bit 8 - LESENSE Decoder Input Configuration

pub fn prssel0(&mut self) -> PRSSEL0_W<'_>

Bits 10:13 - LESENSE Decoder PRS Input 0 Configuration

pub fn prssel1(&mut self) -> PRSSEL1_W<'_>

Bits 15:18 - LESENSE Decoder PRS Input 1 Configuration

pub fn prssel2(&mut self) -> PRSSEL2_W<'_>

Bits 20:23 - LESENSE Decoder PRS Input 2 Configuration

pub fn prssel3(&mut self) -> PRSSEL3_W<'_>

Bits 25:28 - LESENSE Decoder PRS Input 3 Configuration

impl W<u32, Reg<u32, _BIASCTRL>>

pub fn biasmode(&mut self) -> BIASMODE_W<'_>

Bits 0:1 - Select Bias Mode

impl W<u32, Reg<u32, _EVALCTRL>>

pub fn winsize(&mut self) -> WINSIZE_W<'_>

Bits 0:15 - Sliding Window and Step Detection Size

impl W<u32, Reg<u32, _PRSCTRL>>

pub fn deccmpval(&mut self) -> DECCMPVAL_W<'_>

Bits 0:4 - Decoder State Compare Value

pub fn deccmpmask(&mut self) -> DECCMPMASK_W<'_>

Bits 8:12 - Decoder State Compare Value Mask

pub fn deccmpen(&mut self) -> DECCMPEN_W<'_>

Bit 16 - Enable PRS Output DECCMP

impl W<u32, Reg<u32, _CMD>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Scanning of Sensors

pub fn stop(&mut self) -> STOP_W<'_>

Bit 1 - Stop Scanning of Sensors

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 2 - Start Decoder

pub fn clearbuf(&mut self) -> CLEARBUF_W<'_>

Bit 3 - Clear Result Buffer

impl W<u32, Reg<u32, _CHEN>>

pub fn chen(&mut self) -> CHEN_W<'_>

Bits 0:15 - Enable Scan Channel

impl W<u32, Reg<u32, _SCANRES>>

pub fn scanres(&mut self) -> SCANRES_W<'_>

Bits 0:15 - Scan Results

pub fn stepdir(&mut self) -> STEPDIR_W<'_>

Bits 16:31 - Direction of Previous Step Detection

impl W<u32, Reg<u32, _DECSTATE>>

pub fn decstate(&mut self) -> DECSTATE_W<'_>

Bits 0:4 - Current Decoder State

impl W<u32, Reg<u32, _SENSORSTATE>>

pub fn sensorstate(&mut self) -> SENSORSTATE_W<'_>

Bits 0:3 - Decoder Input Register

impl W<u32, Reg<u32, _IDLECONF>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bits 0:1 - Channel 0 Idle Phase Configuration

pub fn ch1(&mut self) -> CH1_W<'_>

Bits 2:3 - Channel 1 Idle Phase Configuration

pub fn ch2(&mut self) -> CH2_W<'_>

Bits 4:5 - Channel 2 Idle Phase Configuration

pub fn ch3(&mut self) -> CH3_W<'_>

Bits 6:7 - Channel 3 Idle Phase Configuration

pub fn ch4(&mut self) -> CH4_W<'_>

Bits 8:9 - Channel 4 Idle Phase Configuration

pub fn ch5(&mut self) -> CH5_W<'_>

Bits 10:11 - Channel 5 Idle Phase Configuration

pub fn ch6(&mut self) -> CH6_W<'_>

Bits 12:13 - Channel 6 Idle Phase Configuration

pub fn ch7(&mut self) -> CH7_W<'_>

Bits 14:15 - Channel 7 Idle Phase Configuration

pub fn ch8(&mut self) -> CH8_W<'_>

Bits 16:17 - Channel 8 Idle Phase Configuration

pub fn ch9(&mut self) -> CH9_W<'_>

Bits 18:19 - Channel 9 Idle Phase Configuration

pub fn ch10(&mut self) -> CH10_W<'_>

Bits 20:21 - Channel 10 Idle Phase Configuration

pub fn ch11(&mut self) -> CH11_W<'_>

Bits 22:23 - Channel 11 Idle Phase Configuration

pub fn ch12(&mut self) -> CH12_W<'_>

Bits 24:25 - Channel 12 Idle Phase Configuration

pub fn ch13(&mut self) -> CH13_W<'_>

Bits 26:27 - Channel 13 Idle Phase Configuration

pub fn ch14(&mut self) -> CH14_W<'_>

Bits 28:29 - Channel 14 Idle Phase Configuration

pub fn ch15(&mut self) -> CH15_W<'_>

Bits 30:31 - Channel 15 Idle Phase Configuration

impl W<u32, Reg<u32, _ALTEXCONF>>

pub fn idleconf0(&mut self) -> IDLECONF0_W<'_>

Bits 0:1 - ALTEX0 Idle Phase Configuration

pub fn idleconf1(&mut self) -> IDLECONF1_W<'_>

Bits 2:3 - ALTEX1 Idle Phase Configuration

pub fn idleconf2(&mut self) -> IDLECONF2_W<'_>

Bits 4:5 - ALTEX2 Idle Phase Configuration

pub fn idleconf3(&mut self) -> IDLECONF3_W<'_>

Bits 6:7 - ALTEX3 Idle Phase Configuration

pub fn idleconf4(&mut self) -> IDLECONF4_W<'_>

Bits 8:9 - ALTEX4 Idle Phase Configuration

pub fn idleconf5(&mut self) -> IDLECONF5_W<'_>

Bits 10:11 - ALTEX5 Idle Phase Configuration

pub fn idleconf6(&mut self) -> IDLECONF6_W<'_>

Bits 12:13 - ALTEX6 Idle Phase Configuration

pub fn idleconf7(&mut self) -> IDLECONF7_W<'_>

Bits 14:15 - ALTEX7 Idle Phase Configuration

pub fn aex0(&mut self) -> AEX0_W<'_>

Bit 16 - ALTEX0 Always Excite Enable

pub fn aex1(&mut self) -> AEX1_W<'_>

Bit 17 - ALTEX1 Always Excite Enable

pub fn aex2(&mut self) -> AEX2_W<'_>

Bit 18 - ALTEX2 Always Excite Enable

pub fn aex3(&mut self) -> AEX3_W<'_>

Bit 19 - ALTEX3 Always Excite Enable

pub fn aex4(&mut self) -> AEX4_W<'_>

Bit 20 - ALTEX4 Always Excite Enable

pub fn aex5(&mut self) -> AEX5_W<'_>

Bit 21 - ALTEX5 Always Excite Enable

pub fn aex6(&mut self) -> AEX6_W<'_>

Bit 22 - ALTEX6 Always Excite Enable

pub fn aex7(&mut self) -> AEX7_W<'_>

Bit 23 - ALTEX7 Always Excite Enable

impl W<u32, Reg<u32, _IFS>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Set CH0 Interrupt Flag

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Set CH1 Interrupt Flag

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Set CH2 Interrupt Flag

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Set CH3 Interrupt Flag

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Set CH4 Interrupt Flag

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Set CH5 Interrupt Flag

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Set CH6 Interrupt Flag

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Set CH7 Interrupt Flag

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Set CH8 Interrupt Flag

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Set CH9 Interrupt Flag

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Set CH10 Interrupt Flag

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Set CH11 Interrupt Flag

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Set CH12 Interrupt Flag

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Set CH13 Interrupt Flag

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Set CH14 Interrupt Flag

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Set CH15 Interrupt Flag

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - Set SCANCOMPLETE Interrupt Flag

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - Set DEC Interrupt Flag

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - Set DECERR Interrupt Flag

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - Set BUFDATAV Interrupt Flag

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - Set BUFLEVEL Interrupt Flag

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - Set BUFOF Interrupt Flag

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - Set CNTOF Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Clear CH0 Interrupt Flag

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Clear CH1 Interrupt Flag

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Clear CH2 Interrupt Flag

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Clear CH3 Interrupt Flag

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Clear CH4 Interrupt Flag

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Clear CH5 Interrupt Flag

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Clear CH6 Interrupt Flag

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Clear CH7 Interrupt Flag

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Clear CH8 Interrupt Flag

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Clear CH9 Interrupt Flag

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Clear CH10 Interrupt Flag

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Clear CH11 Interrupt Flag

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Clear CH12 Interrupt Flag

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Clear CH13 Interrupt Flag

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Clear CH14 Interrupt Flag

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Clear CH15 Interrupt Flag

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - Clear SCANCOMPLETE Interrupt Flag

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - Clear DEC Interrupt Flag

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - Clear DECERR Interrupt Flag

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - Clear BUFDATAV Interrupt Flag

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - Clear BUFLEVEL Interrupt Flag

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - Clear BUFOF Interrupt Flag

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - Clear CNTOF Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - CH0 Interrupt Enable

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - CH1 Interrupt Enable

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - CH2 Interrupt Enable

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - CH3 Interrupt Enable

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - CH4 Interrupt Enable

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - CH5 Interrupt Enable

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - CH6 Interrupt Enable

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - CH7 Interrupt Enable

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - CH8 Interrupt Enable

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - CH9 Interrupt Enable

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - CH10 Interrupt Enable

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - CH11 Interrupt Enable

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - CH12 Interrupt Enable

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - CH13 Interrupt Enable

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - CH14 Interrupt Enable

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - CH15 Interrupt Enable

pub fn scancomplete(&mut self) -> SCANCOMPLETE_W<'_>

Bit 16 - SCANCOMPLETE Interrupt Enable

pub fn dec(&mut self) -> DEC_W<'_>

Bit 17 - DEC Interrupt Enable

pub fn decerr(&mut self) -> DECERR_W<'_>

Bit 18 - DECERR Interrupt Enable

pub fn bufdatav(&mut self) -> BUFDATAV_W<'_>

Bit 19 - BUFDATAV Interrupt Enable

pub fn buflevel(&mut self) -> BUFLEVEL_W<'_>

Bit 20 - BUFLEVEL Interrupt Enable

pub fn bufof(&mut self) -> BUFOF_W<'_>

Bit 21 - BUFOF Interrupt Enable

pub fn cntof(&mut self) -> CNTOF_W<'_>

Bit 22 - CNTOF Interrupt Enable

impl W<u32, Reg<u32, _ROUTEPEN>>

pub fn ch0pen(&mut self) -> CH0PEN_W<'_>

Bit 0 - CH0 Pin Enable

pub fn ch1pen(&mut self) -> CH1PEN_W<'_>

Bit 1 - CH1 Pin Enable

pub fn ch2pen(&mut self) -> CH2PEN_W<'_>

Bit 2 - CH2 Pin Enable

pub fn ch3pen(&mut self) -> CH3PEN_W<'_>

Bit 3 - CH3 Pin Enable

pub fn ch4pen(&mut self) -> CH4PEN_W<'_>

Bit 4 - CH4 Pin Enable

pub fn ch5pen(&mut self) -> CH5PEN_W<'_>

Bit 5 - CH5 Pin Enable

pub fn ch6pen(&mut self) -> CH6PEN_W<'_>

Bit 6 - CH6 Pin Enable

pub fn ch7pen(&mut self) -> CH7PEN_W<'_>

Bit 7 - CH7 Pin Enable

pub fn ch8pen(&mut self) -> CH8PEN_W<'_>

Bit 8 - CH8 Pin Enable

pub fn ch9pen(&mut self) -> CH9PEN_W<'_>

Bit 9 - CH9 Pin Enable

pub fn ch10pen(&mut self) -> CH10PEN_W<'_>

Bit 10 - CH10 Pin Enable

pub fn ch11pen(&mut self) -> CH11PEN_W<'_>

Bit 11 - CH11 Pin Enable

pub fn ch12pen(&mut self) -> CH12PEN_W<'_>

Bit 12 - CH12 Pin Enable

pub fn ch13pen(&mut self) -> CH13PEN_W<'_>

Bit 13 - CH13 Pin Enable

pub fn ch14pen(&mut self) -> CH14PEN_W<'_>

Bit 14 - CH14 Pin Enable

pub fn ch15pen(&mut self) -> CH15PEN_W<'_>

Bit 15 - CH15 Pin Enable

pub fn altex0pen(&mut self) -> ALTEX0PEN_W<'_>

Bit 16 - ALTEX0 Pin Enable

pub fn altex1pen(&mut self) -> ALTEX1PEN_W<'_>

Bit 17 - ALTEX1 Pin Enable

pub fn altex2pen(&mut self) -> ALTEX2PEN_W<'_>

Bit 18 - ALTEX2 Pin Enable

pub fn altex3pen(&mut self) -> ALTEX3PEN_W<'_>

Bit 19 - ALTEX3 Pin Enable

pub fn altex4pen(&mut self) -> ALTEX4PEN_W<'_>

Bit 20 - ALTEX4 Pin Enable

pub fn altex5pen(&mut self) -> ALTEX5PEN_W<'_>

Bit 21 - ALTEX5 Pin Enable

pub fn altex6pen(&mut self) -> ALTEX6PEN_W<'_>

Bit 22 - ALTEX6 Pin Enable

pub fn altex7pen(&mut self) -> ALTEX7PEN_W<'_>

Bit 23 - ALTEX7 Pin Enable

impl W<u32, Reg<u32, _ST0_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST0_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST1_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST1_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST2_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST2_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST3_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST3_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST4_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST4_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST5_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST5_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST6_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST6_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST7_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST7_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST8_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST8_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST9_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST9_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST10_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST10_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST11_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST11_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST12_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST12_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST13_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST13_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST14_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST14_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST15_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST15_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST16_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST16_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST17_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST17_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST18_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST18_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST19_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST19_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST20_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST20_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST21_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST21_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST22_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST22_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST23_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST23_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST24_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST24_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST25_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST25_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST26_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST26_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST27_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST27_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST28_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST28_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST29_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST29_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST30_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST30_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST31_TCONFA>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn chain(&mut self) -> CHAIN_W<'_>

Bit 14 - Enable State Descriptor Chaining

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag Enable

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _ST31_TCONFB>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:3 - Sensor Compare Value

pub fn mask(&mut self) -> MASK_W<'_>

Bits 4:7 - Sensor Mask

pub fn nextstate(&mut self) -> NEXTSTATE_W<'_>

Bits 8:12 - Next State Index

pub fn setif(&mut self) -> SETIF_W<'_>

Bit 15 - Set Interrupt Flag

pub fn prsact(&mut self) -> PRSACT_W<'_>

Bits 16:18 - Configure Transition Action

impl W<u32, Reg<u32, _BUF0_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF1_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF2_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF3_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF4_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF5_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF6_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF7_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF8_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF9_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF10_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF11_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF12_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF13_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF14_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _BUF15_DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Scan Result Buffer

impl W<u32, Reg<u32, _CH0_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH0_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH0_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH1_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH1_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH1_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH2_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH2_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH2_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH3_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH3_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH3_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH4_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH4_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH4_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH5_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH5_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH5_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH6_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH6_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH6_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH7_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH7_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH7_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH8_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH8_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH8_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH9_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH9_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH9_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH10_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH10_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH10_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH11_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH11_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH11_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH12_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH12_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH12_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH13_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH13_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH13_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH14_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH14_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH14_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CH15_TIMING>>

pub fn extime(&mut self) -> EXTIME_W<'_>

Bits 0:5 - Set Excitation Time

pub fn sampledly(&mut self) -> SAMPLEDLY_W<'_>

Bits 6:13 - Set Sample Delay

pub fn measuredly(&mut self) -> MEASUREDLY_W<'_>

Bits 14:23 - Set Measure Delay

impl W<u32, Reg<u32, _CH15_INTERACT>>

pub fn thres(&mut self) -> THRES_W<'_>

Bits 0:11 - ACMP Threshold or VDAC Data

pub fn sample(&mut self) -> SAMPLE_W<'_>

Bits 12:13 - Select Sample Mode

pub fn setif(&mut self) -> SETIF_W<'_>

Bits 14:16 - Enable Interrupt Generation

pub fn exmode(&mut self) -> EXMODE_W<'_>

Bits 17:18 - Set GPIO Mode

pub fn exclk(&mut self) -> EXCLK_W<'_>

Bit 19 - Select Clock Used for Excitation Timing

pub fn sampleclk(&mut self) -> SAMPLECLK_W<'_>

Bit 20 - Select Clock Used for Timing of Sample Delay

pub fn altex(&mut self) -> ALTEX_W<'_>

Bit 21 - Use Alternative Excite Pin

impl W<u32, Reg<u32, _CH15_EVAL>>

pub fn compthres(&mut self) -> COMPTHRES_W<'_>

Bits 0:15 - Decision Threshold for Sensor Data

pub fn comp(&mut self) -> COMP_W<'_>

Bit 16 - Select Mode for Threshold Comparison

pub fn decode(&mut self) -> DECODE_W<'_>

Bit 17 - Send Result to Decoder

pub fn strsample(&mut self) -> STRSAMPLE_W<'_>

Bits 18:19 - Enable Storing of Sensor Sample in Result Buffer

pub fn scanresinv(&mut self) -> SCANRESINV_W<'_>

Bit 20 - Enable Inversion of Result

pub fn mode(&mut self) -> MODE_W<'_>

Bits 21:22 - Configure Evaluation Mode

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - RTCC Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 2 - Debug Mode Run Enable

pub fn preccv0top(&mut self) -> PRECCV0TOP_W<'_>

Bit 4 - Pre-counter CCV0 Top Value Enable

pub fn ccv1top(&mut self) -> CCV1TOP_W<'_>

Bit 5 - CCV1 Top Value Enable

pub fn cntpresc(&mut self) -> CNTPRESC_W<'_>

Bits 8:11 - Counter Prescaler Value

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 12 - Counter Prescaler Mode

pub fn oscfdeten(&mut self) -> OSCFDETEN_W<'_>

Bit 15 - Oscillator Failure Detection Enable

pub fn cntmode(&mut self) -> CNTMODE_W<'_>

Bit 16 - Main Counter Mode

pub fn lyearcorrdis(&mut self) -> LYEARCORRDIS_W<'_>

Bit 17 - Leap Year Correction Disabled

impl W<u32, Reg<u32, _PRECNT>>

pub fn precnt(&mut self) -> PRECNT_W<'_>

Bits 0:14 - Pre-Counter Value

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _DATE>>

pub fn dayomu(&mut self) -> DAYOMU_W<'_>

Bits 0:3 - Day of Month, Units

pub fn dayomt(&mut self) -> DAYOMT_W<'_>

Bits 4:5 - Day of Month, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

pub fn yearu(&mut self) -> YEARU_W<'_>

Bits 16:19 - Year, Units

pub fn yeart(&mut self) -> YEART_W<'_>

Bits 20:23 - Year, Tens

pub fn dayow(&mut self) -> DAYOW_W<'_>

Bits 24:26 - Day of Week

impl W<u32, Reg<u32, _IFS>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Set OF Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - Set CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - Set CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - Set CC2 Interrupt Flag

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - Set OSCFAIL Interrupt Flag

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - Set CNTTICK Interrupt Flag

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - Set MINTICK Interrupt Flag

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - Set HOURTICK Interrupt Flag

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - Set DAYTICK Interrupt Flag

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - Set DAYOWOF Interrupt Flag

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - Set MONTHTICK Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - Clear OF Interrupt Flag

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - Clear CC0 Interrupt Flag

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - Clear CC1 Interrupt Flag

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - Clear CC2 Interrupt Flag

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - Clear OSCFAIL Interrupt Flag

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - Clear CNTTICK Interrupt Flag

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - Clear MINTICK Interrupt Flag

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - Clear HOURTICK Interrupt Flag

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - Clear DAYTICK Interrupt Flag

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - Clear DAYOWOF Interrupt Flag

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - Clear MONTHTICK Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn of(&mut self) -> OF_W<'_>

Bit 0 - OF Interrupt Enable

pub fn cc0(&mut self) -> CC0_W<'_>

Bit 1 - CC0 Interrupt Enable

pub fn cc1(&mut self) -> CC1_W<'_>

Bit 2 - CC1 Interrupt Enable

pub fn cc2(&mut self) -> CC2_W<'_>

Bit 3 - CC2 Interrupt Enable

pub fn oscfail(&mut self) -> OSCFAIL_W<'_>

Bit 4 - OSCFAIL Interrupt Enable

pub fn cnttick(&mut self) -> CNTTICK_W<'_>

Bit 5 - CNTTICK Interrupt Enable

pub fn mintick(&mut self) -> MINTICK_W<'_>

Bit 6 - MINTICK Interrupt Enable

pub fn hourtick(&mut self) -> HOURTICK_W<'_>

Bit 7 - HOURTICK Interrupt Enable

pub fn daytick(&mut self) -> DAYTICK_W<'_>

Bit 8 - DAYTICK Interrupt Enable

pub fn dayowof(&mut self) -> DAYOWOF_W<'_>

Bit 9 - DAYOWOF Interrupt Enable

pub fn monthtick(&mut self) -> MONTHTICK_W<'_>

Bit 10 - MONTHTICK Interrupt Enable

impl W<u32, Reg<u32, _CMD>>

pub fn clrstatus(&mut self) -> CLRSTATUS_W<'_>

Bit 0 - Clear RTCC_STATUS Register

impl W<u32, Reg<u32, _POWERDOWN>>

pub fn ram(&mut self) -> RAM_W<'_>

Bit 0 - Retention RAM Power-down

impl W<u32, Reg<u32, _LOCK>>

pub fn lockkey(&mut self) -> LOCKKEY_W<'_>

Bits 0:15 - Configuration Lock Key

impl W<u32, Reg<u32, _EM4WUEN>>

pub fn em4wu(&mut self) -> EM4WU_W<'_>

Bit 0 - EM4 Wake-up Enable

impl W<u32, Reg<u32, _CC0_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC0_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC0_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC0_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _CC1_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC1_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC1_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC1_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _CC2_CTRL>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - CC Channel Mode

pub fn cmoa(&mut self) -> CMOA_W<'_>

Bits 2:3 - Compare Match Output Action

pub fn icedge(&mut self) -> ICEDGE_W<'_>

Bits 4:5 - Input Capture Edge Select

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 6:9 - Compare/Capture Channel PRS Input Channel Selection

pub fn compbase(&mut self) -> COMPBASE_W<'_>

Bit 11 - Capture Compare Channel Comparison Base

pub fn compmask(&mut self) -> COMPMASK_W<'_>

Bits 12:16 - Capture Compare Channel Comparison Mask

pub fn daycc(&mut self) -> DAYCC_W<'_>

Bit 17 - Day Capture/Compare Selection

impl W<u32, Reg<u32, _CC2_CCV>>

pub fn ccv(&mut self) -> CCV_W<'_>

Bits 0:31 - Capture/Compare Value

impl W<u32, Reg<u32, _CC2_TIME>>

pub fn secu(&mut self) -> SECU_W<'_>

Bits 0:3 - Seconds, Units

pub fn sect(&mut self) -> SECT_W<'_>

Bits 4:6 - Seconds, Tens

pub fn minu(&mut self) -> MINU_W<'_>

Bits 8:11 - Minutes, Units

pub fn mint(&mut self) -> MINT_W<'_>

Bits 12:14 - Minutes, Tens

pub fn houru(&mut self) -> HOURU_W<'_>

Bits 16:19 - Hours, Units

pub fn hourt(&mut self) -> HOURT_W<'_>

Bits 20:21 - Hours, Tens

impl W<u32, Reg<u32, _CC2_DATE>>

pub fn dayu(&mut self) -> DAYU_W<'_>

Bits 0:3 - Day of Month/week, Units

pub fn dayt(&mut self) -> DAYT_W<'_>

Bits 4:5 - Day of Month/week, Tens

pub fn monthu(&mut self) -> MONTHU_W<'_>

Bits 8:11 - Month, Units

pub fn montht(&mut self) -> MONTHT_W<'_>

Bit 12 - Month, Tens

impl W<u32, Reg<u32, _RET0_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET1_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET2_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET3_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET4_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET5_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET6_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET7_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET8_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET9_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET10_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET11_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET12_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET13_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET14_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET15_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET16_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET17_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET18_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET19_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET20_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET21_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET22_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET23_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET24_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET25_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET26_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET27_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET28_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET29_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET30_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _RET31_REG>>

pub fn reg(&mut self) -> REG_W<'_>

Bits 0:31 - General Purpose Retention Register

impl W<u32, Reg<u32, _CTRL>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Watchdog Timer Enable

pub fn debugrun(&mut self) -> DEBUGRUN_W<'_>

Bit 1 - Debug Mode Run Enable

pub fn em2run(&mut self) -> EM2RUN_W<'_>

Bit 2 - Energy Mode 2 Run Enable

pub fn em3run(&mut self) -> EM3RUN_W<'_>

Bit 3 - Energy Mode 3 Run Enable

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 4 - Configuration Lock

pub fn em4block(&mut self) -> EM4BLOCK_W<'_>

Bit 5 - Energy Mode 4 Block

pub fn swoscblock(&mut self) -> SWOSCBLOCK_W<'_>

Bit 6 - Software Oscillator Disable Block

pub fn persel(&mut self) -> PERSEL_W<'_>

Bits 8:11 - Watchdog Timeout Period Select

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bits 12:13 - Watchdog Clock Select

pub fn warnsel(&mut self) -> WARNSEL_W<'_>

Bits 16:17 - Watchdog Timeout Period Select

pub fn winsel(&mut self) -> WINSEL_W<'_>

Bits 24:26 - Watchdog Illegal Window Select

pub fn clrsrc(&mut self) -> CLRSRC_W<'_>

Bit 30 - Watchdog Clear Source

pub fn wdogrstdis(&mut self) -> WDOGRSTDIS_W<'_>

Bit 31 - Watchdog Reset Disable

impl W<u32, Reg<u32, _CMD>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bit 0 - Watchdog Timer Clear

impl W<u32, Reg<u32, _PCH0_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:3 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _PCH1_PRSCTRL>>

pub fn prssel(&mut self) -> PRSSEL_W<'_>

Bits 0:3 - PRS Channel PRS Select

pub fn prsmissrsten(&mut self) -> PRSMISSRSTEN_W<'_>

Bit 8 - PRS Missing Event Will Trigger a Watchdog Reset

impl W<u32, Reg<u32, _IFS>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Set TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Set WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Set WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Set PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Set PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - Clear TOUT Interrupt Flag

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - Clear WARN Interrupt Flag

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - Clear WIN Interrupt Flag

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - Clear PEM0 Interrupt Flag

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - Clear PEM1 Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn tout(&mut self) -> TOUT_W<'_>

Bit 0 - TOUT Interrupt Enable

pub fn warn(&mut self) -> WARN_W<'_>

Bit 1 - WARN Interrupt Enable

pub fn win(&mut self) -> WIN_W<'_>

Bit 2 - WIN Interrupt Enable

pub fn pem0(&mut self) -> PEM0_W<'_>

Bit 3 - PEM0 Interrupt Enable

pub fn pem1(&mut self) -> PEM1_W<'_>

Bit 4 - PEM1 Interrupt Enable

impl W<u32, Reg<u32, _ETMCR>>

pub fn powerdwn(&mut self) -> POWERDWN_W<'_>

Bit 0 - ETM Control in low power mode

pub fn portsize(&mut self) -> PORTSIZE_W<'_>

Bits 4:6 - ETM Port Size

pub fn stall(&mut self) -> STALL_W<'_>

Bit 7 - Stall Processor

pub fn branchoutput(&mut self) -> BRANCHOUTPUT_W<'_>

Bit 8 - Branch Output

pub fn dbgreqctrl(&mut self) -> DBGREQCTRL_W<'_>

Bit 9 - Debug Request Control

pub fn etmprog(&mut self) -> ETMPROG_W<'_>

Bit 10 - ETM Programming

pub fn etmportsel(&mut self) -> ETMPORTSEL_W<'_>

Bit 11 - ETM Port Selection

pub fn portmode2(&mut self) -> PORTMODE2_W<'_>

Bit 13 - Port Mode[2]

pub fn portmode(&mut self) -> PORTMODE_W<'_>

Bits 16:17 - Port Mode Control

pub fn eportsize(&mut self) -> EPORTSIZE_W<'_>

Bits 21:22 - Port Size[3]

pub fn tstampen(&mut self) -> TSTAMPEN_W<'_>

Bit 28 - Time Stamp Enable

impl W<u32, Reg<u32, _ETMTRIGGER>>

pub fn resa(&mut self) -> RESA_W<'_>

Bits 0:6 - ETM Resource A

pub fn resb(&mut self) -> RESB_W<'_>

Bits 7:13 - ETM Resource B

pub fn etmfcn(&mut self) -> ETMFCN_W<'_>

Bits 14:16 - ETM Function

impl W<u32, Reg<u32, _ETMSR>>

pub fn tracestat(&mut self) -> TRACESTAT_W<'_>

Bit 2 - Trace Start/Stop Status

pub fn trigbit(&mut self) -> TRIGBIT_W<'_>

Bit 3 - Trigger Bit

impl W<u32, Reg<u32, _ETMTEEVR>>

pub fn resa(&mut self) -> RESA_W<'_>

Bits 0:6 - ETM Resource A Trace Enable

pub fn resb(&mut self) -> RESB_W<'_>

Bits 7:13 - ETM Resource B Trace Enable

pub fn etmfcnen(&mut self) -> ETMFCNEN_W<'_>

Bits 14:16 - ETM Function Trace Enable

impl W<u32, Reg<u32, _ETMTECR1>>

pub fn adrcmp(&mut self) -> ADRCMP_W<'_>

Bits 0:7 - Address Comparator

pub fn memmap(&mut self) -> MEMMAP_W<'_>

Bits 8:23 - Memmap

pub fn incexctl(&mut self) -> INCEXCTL_W<'_>

Bit 24 - Trace Include/Exclude Flag

pub fn tce(&mut self) -> TCE_W<'_>

Bit 25 - Trace Control Enable

impl W<u32, Reg<u32, _ETMFFLR>>

pub fn bytenum(&mut self) -> BYTENUM_W<'_>

Bits 0:7 - Bytes left in FIFO

impl W<u32, Reg<u32, _ETMCNTRLDVR1>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Free running counter reload value

impl W<u32, Reg<u32, _ETMSYNCFR>>

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:11 - Synchronisation Frequency Value

impl W<u32, Reg<u32, _ETMTESSEICR>>

pub fn startrsel(&mut self) -> STARTRSEL_W<'_>

Bits 0:3 - Stop Resource Selection

pub fn stoprsel(&mut self) -> STOPRSEL_W<'_>

Bits 16:19 - Stop Resource Selection

impl W<u32, Reg<u32, _ETMTSEVR>>

pub fn resaevt(&mut self) -> RESAEVT_W<'_>

Bits 0:6 - ETM Resource A Event

pub fn resbevt(&mut self) -> RESBEVT_W<'_>

Bits 7:13 - ETM Resource B Event

pub fn etmfcnevt(&mut self) -> ETMFCNEVT_W<'_>

Bits 14:16 - ETM Function Event

impl W<u32, Reg<u32, _ETMTRACEIDR>>

pub fn traceid(&mut self) -> TRACEID_W<'_>

Bits 0:6 - Trace ID

impl W<u32, Reg<u32, _ETMISCIN>>

pub fn extin(&mut self) -> EXTIN_W<'_>

Bits 0:1 - EXTIN Value

pub fn corehalt(&mut self) -> COREHALT_W<'_>

Bit 4 - Core Halt

impl W<u32, Reg<u32, _ITTRIGOUT>>

pub fn triggerout(&mut self) -> TRIGGEROUT_W<'_>

Bit 0 - Trigger output value

impl W<u32, Reg<u32, _ETMITATBCTR0>>

pub fn atvalid(&mut self) -> ATVALID_W<'_>

Bit 0 - ATVALID Output Value

impl W<u32, Reg<u32, _ETMITCTRL>>

pub fn iten(&mut self) -> ITEN_W<'_>

Bit 0 - Integration Mode Enable

impl W<u32, Reg<u32, _ETMCLAIMSET>>

pub fn settag(&mut self) -> SETTAG_W<'_>

Bits 0:7 - Tag Bits

impl W<u32, Reg<u32, _ETMCLAIMCLR>>

pub fn clrtag(&mut self) -> CLRTAG_W<'_>

Bit 0 - Tag Bits

impl W<u32, Reg<u32, _ETMLAR>>

pub fn key(&mut self) -> KEY_W<'_>

Bit 0 - Key Value

impl W<u32, Reg<u32, _IFS>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - Set PPUPRIV Interrupt Flag

impl W<u32, Reg<u32, _IFC>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - Clear PPUPRIV Interrupt Flag

impl W<u32, Reg<u32, _IEN>>

pub fn ppupriv(&mut self) -> PPUPRIV_W<'_>

Bit 0 - PPUPRIV Interrupt Enable

impl W<u32, Reg<u32, _PPUCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0

impl W<u32, Reg<u32, _PPUPATD0>>

pub fn acmp0(&mut self) -> ACMP0_W<'_>

Bit 0 - Analog Comparator 0 access control bit

pub fn acmp1(&mut self) -> ACMP1_W<'_>

Bit 1 - Analog Comparator 1 access control bit

pub fn adc0(&mut self) -> ADC0_W<'_>

Bit 2 - Analog to Digital Converter 0 access control bit

pub fn cmu(&mut self) -> CMU_W<'_>

Bit 5 - Clock Management Unit access control bit

pub fn cryotimer(&mut self) -> CRYOTIMER_W<'_>

Bit 7 - CRYOTIMER access control bit

pub fn crypto0(&mut self) -> CRYPTO0_W<'_>

Bit 8 - Advanced Encryption Standard Accelerator 0 access control bit

pub fn crypto1(&mut self) -> CRYPTO1_W<'_>

Bit 9 - Advanced Encryption Standard Accelerator 1 access control bit

pub fn csen(&mut self) -> CSEN_W<'_>

Bit 10 - Capacitive touch sense module access control bit

pub fn vdac0(&mut self) -> VDAC0_W<'_>

Bit 11 - Digital to Analog Converter 0 access control bit

pub fn prs(&mut self) -> PRS_W<'_>

Bit 12 - Peripheral Reflex System access control bit

pub fn emu(&mut self) -> EMU_W<'_>

Bit 13 - Energy Management Unit access control bit

pub fn fpueh(&mut self) -> FPUEH_W<'_>

Bit 14 - FPU Exception Handler access control bit

pub fn gpcrc(&mut self) -> GPCRC_W<'_>

Bit 16 - General Purpose CRC access control bit

pub fn gpio(&mut self) -> GPIO_W<'_>

Bit 17 - General purpose Input/Output access control bit

pub fn i2c0(&mut self) -> I2C0_W<'_>

Bit 18 - I2C 0 access control bit

pub fn i2c1(&mut self) -> I2C1_W<'_>

Bit 19 - I2C 1 access control bit

pub fn idac0(&mut self) -> IDAC0_W<'_>

Bit 20 - Current Digital to Analog Converter 0 access control bit

pub fn msc(&mut self) -> MSC_W<'_>

Bit 21 - Memory System Controller access control bit

pub fn ldma(&mut self) -> LDMA_W<'_>

Bit 22 - Linked Direct Memory Access Controller access control bit

pub fn lesense(&mut self) -> LESENSE_W<'_>

Bit 23 - Low Energy Sensor Interface access control bit

pub fn letimer0(&mut self) -> LETIMER0_W<'_>

Bit 24 - Low Energy Timer 0 access control bit

pub fn leuart0(&mut self) -> LEUART0_W<'_>

Bit 25 - Low Energy UART 0 access control bit

pub fn pcnt0(&mut self) -> PCNT0_W<'_>

Bit 27 - Pulse Counter 0 access control bit

pub fn pcnt1(&mut self) -> PCNT1_W<'_>

Bit 28 - Pulse Counter 1 access control bit

pub fn pcnt2(&mut self) -> PCNT2_W<'_>

Bit 29 - Pulse Counter 2 access control bit

impl W<u32, Reg<u32, _PPUPATD1>>

pub fn rmu(&mut self) -> RMU_W<'_>

Bit 1 - Reset Management Unit access control bit

pub fn rtcc(&mut self) -> RTCC_W<'_>

Bit 2 - Real-Time Counter and Calendar access control bit

pub fn smu(&mut self) -> SMU_W<'_>

Bit 3 - Security Management Unit access control bit

pub fn timer0(&mut self) -> TIMER0_W<'_>

Bit 5 - Timer 0 access control bit

pub fn timer1(&mut self) -> TIMER1_W<'_>

Bit 6 - Timer 1 access control bit

pub fn trng0(&mut self) -> TRNG0_W<'_>

Bit 7 - True Random Number Generator 0 access control bit

pub fn usart0(&mut self) -> USART0_W<'_>

Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit

pub fn usart1(&mut self) -> USART1_W<'_>

Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit

pub fn usart2(&mut self) -> USART2_W<'_>

Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit

pub fn usart3(&mut self) -> USART3_W<'_>

Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit

pub fn wdog0(&mut self) -> WDOG0_W<'_>

Bit 12 - Watchdog 0 access control bit

pub fn wdog1(&mut self) -> WDOG1_W<'_>

Bit 13 - Watchdog 1 access control bit

pub fn wtimer0(&mut self) -> WTIMER0_W<'_>

Bit 14 - Wide Timer 0 access control bit

pub fn wtimer1(&mut self) -> WTIMER1_W<'_>

Bit 15 - Wide Timer 1 access control bit

impl W<u32, Reg<u32, _CONTROL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - TRNG Module Enable

pub fn testen(&mut self) -> TESTEN_W<'_>

Bit 2 - Test Enable

pub fn condbypass(&mut self) -> CONDBYPASS_W<'_>

Bit 3 - Conditioning Bypass

pub fn repcountien(&mut self) -> REPCOUNTIEN_W<'_>

Bit 4 - Interrupt Enable for Repetition Count Test Failure

pub fn apt64ien(&mut self) -> APT64IEN_W<'_>

Bit 5 - Interrupt Enable for Adaptive Proportion Test Failure (64-sample Window)

pub fn apt4096ien(&mut self) -> APT4096IEN_W<'_>

Bit 6 - Interrupt Enable for Adaptive Proportion Test Failure (4096-sample Window)

pub fn fullien(&mut self) -> FULLIEN_W<'_>

Bit 7 - Interrupt Enable for FIFO Full

pub fn softreset(&mut self) -> SOFTRESET_W<'_>

Bit 8 - Software Reset

pub fn preien(&mut self) -> PREIEN_W<'_>

Bit 9 - Interrupt enable for AIS31 preliminary noise alarm

pub fn almien(&mut self) -> ALMIEN_W<'_>

Bit 10 - Interrupt enable for AIS31 noise alarm

pub fn forcerun(&mut self) -> FORCERUN_W<'_>

Bit 11 - Oscillator Force Run

pub fn bypnist(&mut self) -> BYPNIST_W<'_>

Bit 12 - NIST Start-up Test Bypass.

pub fn bypais31(&mut self) -> BYPAIS31_W<'_>

Bit 13 - AIS31 Start-up Test Bypass.

impl W<u32, Reg<u32, _KEY0>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 0

impl W<u32, Reg<u32, _KEY1>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 1

impl W<u32, Reg<u32, _KEY2>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 2

impl W<u32, Reg<u32, _KEY3>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Key 3

impl W<u32, Reg<u32, _TESTDATA>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - Test data input to conditioning function or to the continuous tests

impl W<u32, Reg<u32, _STATUS>>

pub fn preif(&mut self) -> PREIF_W<'_>

Bit 8 - AIS31 Preliminary Noise Alarm interrupt status

impl W<u32, Reg<u32, _INITWAITVAL>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:7 - Wait counter value