efm32pg12_pac/gpio/
insense.rs

1#[doc = "Reader of register INSENSE"]
2pub type R = crate::R<u32, super::INSENSE>;
3#[doc = "Writer for register INSENSE"]
4pub type W = crate::W<u32, super::INSENSE>;
5#[doc = "Register INSENSE `reset()`'s with value 0x03"]
6impl crate::ResetValue for super::INSENSE {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x03
11    }
12}
13#[doc = "Reader of field `INT`"]
14pub type INT_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `INT`"]
16pub struct INT_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> INT_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `EM4WU`"]
38pub type EM4WU_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `EM4WU`"]
40pub struct EM4WU_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> EM4WU_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61impl R {
62    #[doc = "Bit 0 - Interrupt Sense Enable"]
63    #[inline(always)]
64    pub fn int(&self) -> INT_R {
65        INT_R::new((self.bits & 0x01) != 0)
66    }
67    #[doc = "Bit 1 - EM4WU Interrupt Sense Enable"]
68    #[inline(always)]
69    pub fn em4wu(&self) -> EM4WU_R {
70        EM4WU_R::new(((self.bits >> 1) & 0x01) != 0)
71    }
72}
73impl W {
74    #[doc = "Bit 0 - Interrupt Sense Enable"]
75    #[inline(always)]
76    pub fn int(&mut self) -> INT_W {
77        INT_W { w: self }
78    }
79    #[doc = "Bit 1 - EM4WU Interrupt Sense Enable"]
80    #[inline(always)]
81    pub fn em4wu(&mut self) -> EM4WU_W {
82        EM4WU_W { w: self }
83    }
84}
efm32pg12_pac/gpio/insense.rs

efm32pg12_pac/gpio/
insense.rs
