efm32pg12_pac/cmu/
adcctrl.rs

1#[doc = "Reader of register ADCCTRL"]
2pub type R = crate::R<u32, super::ADCCTRL>;
3#[doc = "Writer for register ADCCTRL"]
4pub type W = crate::W<u32, super::ADCCTRL>;
5#[doc = "Register ADCCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::ADCCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "ADC0 Clock Select\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum ADC0CLKSEL_A {
17    #[doc = "0: ADC0 is not clocked"]
18    DISABLED = 0,
19    #[doc = "1: AUXHFRCO is clocking ADC0"]
20    AUXHFRCO = 1,
21    #[doc = "2: HFXO is clocking ADC0"]
22    HFXO = 2,
23    #[doc = "3: HFSRCCLK is clocking ADC0"]
24    HFSRCCLK = 3,
25}
26impl From<ADC0CLKSEL_A> for u8 {
27    #[inline(always)]
28    fn from(variant: ADC0CLKSEL_A) -> Self {
29        variant as _
30    }
31}
32#[doc = "Reader of field `ADC0CLKSEL`"]
33pub type ADC0CLKSEL_R = crate::R<u8, ADC0CLKSEL_A>;
34impl ADC0CLKSEL_R {
35    #[doc = r"Get enumerated values variant"]
36    #[inline(always)]
37    pub fn variant(&self) -> ADC0CLKSEL_A {
38        match self.bits {
39            0 => ADC0CLKSEL_A::DISABLED,
40            1 => ADC0CLKSEL_A::AUXHFRCO,
41            2 => ADC0CLKSEL_A::HFXO,
42            3 => ADC0CLKSEL_A::HFSRCCLK,
43            _ => unreachable!(),
44        }
45    }
46    #[doc = "Checks if the value of the field is `DISABLED`"]
47    #[inline(always)]
48    pub fn is_disabled(&self) -> bool {
49        *self == ADC0CLKSEL_A::DISABLED
50    }
51    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
52    #[inline(always)]
53    pub fn is_auxhfrco(&self) -> bool {
54        *self == ADC0CLKSEL_A::AUXHFRCO
55    }
56    #[doc = "Checks if the value of the field is `HFXO`"]
57    #[inline(always)]
58    pub fn is_hfxo(&self) -> bool {
59        *self == ADC0CLKSEL_A::HFXO
60    }
61    #[doc = "Checks if the value of the field is `HFSRCCLK`"]
62    #[inline(always)]
63    pub fn is_hfsrcclk(&self) -> bool {
64        *self == ADC0CLKSEL_A::HFSRCCLK
65    }
66}
67#[doc = "Write proxy for field `ADC0CLKSEL`"]
68pub struct ADC0CLKSEL_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> ADC0CLKSEL_W<'a> {
72    #[doc = r"Writes `variant` to the field"]
73    #[inline(always)]
74    pub fn variant(self, variant: ADC0CLKSEL_A) -> &'a mut W {
75        {
76            self.bits(variant.into())
77        }
78    }
79    #[doc = "ADC0 is not clocked"]
80    #[inline(always)]
81    pub fn disabled(self) -> &'a mut W {
82        self.variant(ADC0CLKSEL_A::DISABLED)
83    }
84    #[doc = "AUXHFRCO is clocking ADC0"]
85    #[inline(always)]
86    pub fn auxhfrco(self) -> &'a mut W {
87        self.variant(ADC0CLKSEL_A::AUXHFRCO)
88    }
89    #[doc = "HFXO is clocking ADC0"]
90    #[inline(always)]
91    pub fn hfxo(self) -> &'a mut W {
92        self.variant(ADC0CLKSEL_A::HFXO)
93    }
94    #[doc = "HFSRCCLK is clocking ADC0"]
95    #[inline(always)]
96    pub fn hfsrcclk(self) -> &'a mut W {
97        self.variant(ADC0CLKSEL_A::HFSRCCLK)
98    }
99    #[doc = r"Writes raw bits to the field"]
100    #[inline(always)]
101    pub fn bits(self, value: u8) -> &'a mut W {
102        self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
103        self.w
104    }
105}
106#[doc = "Reader of field `ADC0CLKINV`"]
107pub type ADC0CLKINV_R = crate::R<bool, bool>;
108#[doc = "Write proxy for field `ADC0CLKINV`"]
109pub struct ADC0CLKINV_W<'a> {
110    w: &'a mut W,
111}
112impl<'a> ADC0CLKINV_W<'a> {
113    #[doc = r"Sets the field bit"]
114    #[inline(always)]
115    pub fn set_bit(self) -> &'a mut W {
116        self.bit(true)
117    }
118    #[doc = r"Clears the field bit"]
119    #[inline(always)]
120    pub fn clear_bit(self) -> &'a mut W {
121        self.bit(false)
122    }
123    #[doc = r"Writes raw bits to the field"]
124    #[inline(always)]
125    pub fn bit(self, value: bool) -> &'a mut W {
126        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
127        self.w
128    }
129}
130impl R {
131    #[doc = "Bits 4:5 - ADC0 Clock Select"]
132    #[inline(always)]
133    pub fn adc0clksel(&self) -> ADC0CLKSEL_R {
134        ADC0CLKSEL_R::new(((self.bits >> 4) & 0x03) as u8)
135    }
136    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
137    #[inline(always)]
138    pub fn adc0clkinv(&self) -> ADC0CLKINV_R {
139        ADC0CLKINV_R::new(((self.bits >> 8) & 0x01) != 0)
140    }
141}
142impl W {
143    #[doc = "Bits 4:5 - ADC0 Clock Select"]
144    #[inline(always)]
145    pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W {
146        ADC0CLKSEL_W { w: self }
147    }
148    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
149    #[inline(always)]
150    pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W {
151        ADC0CLKINV_W { w: self }
152    }
153}
efm32pg12_pac/cmu/adcctrl.rs

efm32pg12_pac/cmu/
adcctrl.rs
