1#[doc = "Reader of register CH5_CTRL"]
2pub type R = crate::R<u32, super::CH5_CTRL>;
3#[doc = "Writer for register CH5_CTRL"]
4pub type W = crate::W<u32, super::CH5_CTRL>;
5#[doc = "Register CH5_CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CH5_CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `SIGSEL`"]
14pub type SIGSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `SIGSEL`"]
16pub struct SIGSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> SIGSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
24 self.w
25 }
26}
27#[doc = "Source Select\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29#[repr(u8)]
30pub enum SOURCESEL_A {
31 #[doc = "0: No source selected"]
32 NONE = 0,
33 #[doc = "1: Peripheral Reflex System"]
34 PRSL = 1,
35 #[doc = "2: Peripheral Reflex System"]
36 PRSH = 2,
37 #[doc = "3: Analog Comparator 0"]
38 ACMP0 = 3,
39 #[doc = "4: Analog Comparator 1"]
40 ACMP1 = 4,
41 #[doc = "5: Analog to Digital Converter 0"]
42 ADC0 = 5,
43 #[doc = "7: Low Energy Sensor Interface"]
44 LESENSEL = 7,
45 #[doc = "8: Low Energy Sensor Interface"]
46 LESENSEH = 8,
47 #[doc = "9: Low Energy Sensor Interface"]
48 LESENSED = 9,
49 #[doc = "10: Low Energy Sensor Interface"]
50 LESENSE = 10,
51 #[doc = "11: Real-Time Counter and Calendar"]
52 RTCC = 11,
53 #[doc = "12: General purpose Input/Output"]
54 GPIOL = 12,
55 #[doc = "13: General purpose Input/Output"]
56 GPIOH = 13,
57 #[doc = "14: Low Energy Timer 0"]
58 LETIMER0 = 14,
59 #[doc = "15: Pulse Counter 0"]
60 PCNT0 = 15,
61 #[doc = "16: Pulse Counter 1"]
62 PCNT1 = 16,
63 #[doc = "17: Pulse Counter 2"]
64 PCNT2 = 17,
65 #[doc = "18: Clock Management Unit"]
66 CMU = 18,
67 #[doc = "24: Digital to Analog Converter 0"]
68 VDAC0 = 24,
69 #[doc = "26: CRYOTIMER"]
70 CRYOTIMER = 26,
71 #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
72 USART0 = 48,
73 #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
74 USART1 = 49,
75 #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
76 USART2 = 50,
77 #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
78 USART3 = 51,
79 #[doc = "60: Timer 0"]
80 TIMER0 = 60,
81 #[doc = "61: Timer 1"]
82 TIMER1 = 61,
83 #[doc = "62: Wide Timer 0"]
84 WTIMER0 = 62,
85 #[doc = "63: Wide Timer 1"]
86 WTIMER1 = 63,
87 #[doc = "67: `1000011`"]
88 CM4 = 67,
89}
90impl From<SOURCESEL_A> for u8 {
91 #[inline(always)]
92 fn from(variant: SOURCESEL_A) -> Self {
93 variant as _
94 }
95}
96#[doc = "Reader of field `SOURCESEL`"]
97pub type SOURCESEL_R = crate::R<u8, SOURCESEL_A>;
98impl SOURCESEL_R {
99 #[doc = r"Get enumerated values variant"]
100 #[inline(always)]
101 pub fn variant(&self) -> crate::Variant<u8, SOURCESEL_A> {
102 use crate::Variant::*;
103 match self.bits {
104 0 => Val(SOURCESEL_A::NONE),
105 1 => Val(SOURCESEL_A::PRSL),
106 2 => Val(SOURCESEL_A::PRSH),
107 3 => Val(SOURCESEL_A::ACMP0),
108 4 => Val(SOURCESEL_A::ACMP1),
109 5 => Val(SOURCESEL_A::ADC0),
110 7 => Val(SOURCESEL_A::LESENSEL),
111 8 => Val(SOURCESEL_A::LESENSEH),
112 9 => Val(SOURCESEL_A::LESENSED),
113 10 => Val(SOURCESEL_A::LESENSE),
114 11 => Val(SOURCESEL_A::RTCC),
115 12 => Val(SOURCESEL_A::GPIOL),
116 13 => Val(SOURCESEL_A::GPIOH),
117 14 => Val(SOURCESEL_A::LETIMER0),
118 15 => Val(SOURCESEL_A::PCNT0),
119 16 => Val(SOURCESEL_A::PCNT1),
120 17 => Val(SOURCESEL_A::PCNT2),
121 18 => Val(SOURCESEL_A::CMU),
122 24 => Val(SOURCESEL_A::VDAC0),
123 26 => Val(SOURCESEL_A::CRYOTIMER),
124 48 => Val(SOURCESEL_A::USART0),
125 49 => Val(SOURCESEL_A::USART1),
126 50 => Val(SOURCESEL_A::USART2),
127 51 => Val(SOURCESEL_A::USART3),
128 60 => Val(SOURCESEL_A::TIMER0),
129 61 => Val(SOURCESEL_A::TIMER1),
130 62 => Val(SOURCESEL_A::WTIMER0),
131 63 => Val(SOURCESEL_A::WTIMER1),
132 67 => Val(SOURCESEL_A::CM4),
133 i => Res(i),
134 }
135 }
136 #[doc = "Checks if the value of the field is `NONE`"]
137 #[inline(always)]
138 pub fn is_none(&self) -> bool {
139 *self == SOURCESEL_A::NONE
140 }
141 #[doc = "Checks if the value of the field is `PRSL`"]
142 #[inline(always)]
143 pub fn is_prsl(&self) -> bool {
144 *self == SOURCESEL_A::PRSL
145 }
146 #[doc = "Checks if the value of the field is `PRSH`"]
147 #[inline(always)]
148 pub fn is_prsh(&self) -> bool {
149 *self == SOURCESEL_A::PRSH
150 }
151 #[doc = "Checks if the value of the field is `ACMP0`"]
152 #[inline(always)]
153 pub fn is_acmp0(&self) -> bool {
154 *self == SOURCESEL_A::ACMP0
155 }
156 #[doc = "Checks if the value of the field is `ACMP1`"]
157 #[inline(always)]
158 pub fn is_acmp1(&self) -> bool {
159 *self == SOURCESEL_A::ACMP1
160 }
161 #[doc = "Checks if the value of the field is `ADC0`"]
162 #[inline(always)]
163 pub fn is_adc0(&self) -> bool {
164 *self == SOURCESEL_A::ADC0
165 }
166 #[doc = "Checks if the value of the field is `LESENSEL`"]
167 #[inline(always)]
168 pub fn is_lesensel(&self) -> bool {
169 *self == SOURCESEL_A::LESENSEL
170 }
171 #[doc = "Checks if the value of the field is `LESENSEH`"]
172 #[inline(always)]
173 pub fn is_lesenseh(&self) -> bool {
174 *self == SOURCESEL_A::LESENSEH
175 }
176 #[doc = "Checks if the value of the field is `LESENSED`"]
177 #[inline(always)]
178 pub fn is_lesensed(&self) -> bool {
179 *self == SOURCESEL_A::LESENSED
180 }
181 #[doc = "Checks if the value of the field is `LESENSE`"]
182 #[inline(always)]
183 pub fn is_lesense(&self) -> bool {
184 *self == SOURCESEL_A::LESENSE
185 }
186 #[doc = "Checks if the value of the field is `RTCC`"]
187 #[inline(always)]
188 pub fn is_rtcc(&self) -> bool {
189 *self == SOURCESEL_A::RTCC
190 }
191 #[doc = "Checks if the value of the field is `GPIOL`"]
192 #[inline(always)]
193 pub fn is_gpiol(&self) -> bool {
194 *self == SOURCESEL_A::GPIOL
195 }
196 #[doc = "Checks if the value of the field is `GPIOH`"]
197 #[inline(always)]
198 pub fn is_gpioh(&self) -> bool {
199 *self == SOURCESEL_A::GPIOH
200 }
201 #[doc = "Checks if the value of the field is `LETIMER0`"]
202 #[inline(always)]
203 pub fn is_letimer0(&self) -> bool {
204 *self == SOURCESEL_A::LETIMER0
205 }
206 #[doc = "Checks if the value of the field is `PCNT0`"]
207 #[inline(always)]
208 pub fn is_pcnt0(&self) -> bool {
209 *self == SOURCESEL_A::PCNT0
210 }
211 #[doc = "Checks if the value of the field is `PCNT1`"]
212 #[inline(always)]
213 pub fn is_pcnt1(&self) -> bool {
214 *self == SOURCESEL_A::PCNT1
215 }
216 #[doc = "Checks if the value of the field is `PCNT2`"]
217 #[inline(always)]
218 pub fn is_pcnt2(&self) -> bool {
219 *self == SOURCESEL_A::PCNT2
220 }
221 #[doc = "Checks if the value of the field is `CMU`"]
222 #[inline(always)]
223 pub fn is_cmu(&self) -> bool {
224 *self == SOURCESEL_A::CMU
225 }
226 #[doc = "Checks if the value of the field is `VDAC0`"]
227 #[inline(always)]
228 pub fn is_vdac0(&self) -> bool {
229 *self == SOURCESEL_A::VDAC0
230 }
231 #[doc = "Checks if the value of the field is `CRYOTIMER`"]
232 #[inline(always)]
233 pub fn is_cryotimer(&self) -> bool {
234 *self == SOURCESEL_A::CRYOTIMER
235 }
236 #[doc = "Checks if the value of the field is `USART0`"]
237 #[inline(always)]
238 pub fn is_usart0(&self) -> bool {
239 *self == SOURCESEL_A::USART0
240 }
241 #[doc = "Checks if the value of the field is `USART1`"]
242 #[inline(always)]
243 pub fn is_usart1(&self) -> bool {
244 *self == SOURCESEL_A::USART1
245 }
246 #[doc = "Checks if the value of the field is `USART2`"]
247 #[inline(always)]
248 pub fn is_usart2(&self) -> bool {
249 *self == SOURCESEL_A::USART2
250 }
251 #[doc = "Checks if the value of the field is `USART3`"]
252 #[inline(always)]
253 pub fn is_usart3(&self) -> bool {
254 *self == SOURCESEL_A::USART3
255 }
256 #[doc = "Checks if the value of the field is `TIMER0`"]
257 #[inline(always)]
258 pub fn is_timer0(&self) -> bool {
259 *self == SOURCESEL_A::TIMER0
260 }
261 #[doc = "Checks if the value of the field is `TIMER1`"]
262 #[inline(always)]
263 pub fn is_timer1(&self) -> bool {
264 *self == SOURCESEL_A::TIMER1
265 }
266 #[doc = "Checks if the value of the field is `WTIMER0`"]
267 #[inline(always)]
268 pub fn is_wtimer0(&self) -> bool {
269 *self == SOURCESEL_A::WTIMER0
270 }
271 #[doc = "Checks if the value of the field is `WTIMER1`"]
272 #[inline(always)]
273 pub fn is_wtimer1(&self) -> bool {
274 *self == SOURCESEL_A::WTIMER1
275 }
276 #[doc = "Checks if the value of the field is `CM4`"]
277 #[inline(always)]
278 pub fn is_cm4(&self) -> bool {
279 *self == SOURCESEL_A::CM4
280 }
281}
282#[doc = "Write proxy for field `SOURCESEL`"]
283pub struct SOURCESEL_W<'a> {
284 w: &'a mut W,
285}
286impl<'a> SOURCESEL_W<'a> {
287 #[doc = r"Writes `variant` to the field"]
288 #[inline(always)]
289 pub fn variant(self, variant: SOURCESEL_A) -> &'a mut W {
290 unsafe { self.bits(variant.into()) }
291 }
292 #[doc = "No source selected"]
293 #[inline(always)]
294 pub fn none(self) -> &'a mut W {
295 self.variant(SOURCESEL_A::NONE)
296 }
297 #[doc = "Peripheral Reflex System"]
298 #[inline(always)]
299 pub fn prsl(self) -> &'a mut W {
300 self.variant(SOURCESEL_A::PRSL)
301 }
302 #[doc = "Peripheral Reflex System"]
303 #[inline(always)]
304 pub fn prsh(self) -> &'a mut W {
305 self.variant(SOURCESEL_A::PRSH)
306 }
307 #[doc = "Analog Comparator 0"]
308 #[inline(always)]
309 pub fn acmp0(self) -> &'a mut W {
310 self.variant(SOURCESEL_A::ACMP0)
311 }
312 #[doc = "Analog Comparator 1"]
313 #[inline(always)]
314 pub fn acmp1(self) -> &'a mut W {
315 self.variant(SOURCESEL_A::ACMP1)
316 }
317 #[doc = "Analog to Digital Converter 0"]
318 #[inline(always)]
319 pub fn adc0(self) -> &'a mut W {
320 self.variant(SOURCESEL_A::ADC0)
321 }
322 #[doc = "Low Energy Sensor Interface"]
323 #[inline(always)]
324 pub fn lesensel(self) -> &'a mut W {
325 self.variant(SOURCESEL_A::LESENSEL)
326 }
327 #[doc = "Low Energy Sensor Interface"]
328 #[inline(always)]
329 pub fn lesenseh(self) -> &'a mut W {
330 self.variant(SOURCESEL_A::LESENSEH)
331 }
332 #[doc = "Low Energy Sensor Interface"]
333 #[inline(always)]
334 pub fn lesensed(self) -> &'a mut W {
335 self.variant(SOURCESEL_A::LESENSED)
336 }
337 #[doc = "Low Energy Sensor Interface"]
338 #[inline(always)]
339 pub fn lesense(self) -> &'a mut W {
340 self.variant(SOURCESEL_A::LESENSE)
341 }
342 #[doc = "Real-Time Counter and Calendar"]
343 #[inline(always)]
344 pub fn rtcc(self) -> &'a mut W {
345 self.variant(SOURCESEL_A::RTCC)
346 }
347 #[doc = "General purpose Input/Output"]
348 #[inline(always)]
349 pub fn gpiol(self) -> &'a mut W {
350 self.variant(SOURCESEL_A::GPIOL)
351 }
352 #[doc = "General purpose Input/Output"]
353 #[inline(always)]
354 pub fn gpioh(self) -> &'a mut W {
355 self.variant(SOURCESEL_A::GPIOH)
356 }
357 #[doc = "Low Energy Timer 0"]
358 #[inline(always)]
359 pub fn letimer0(self) -> &'a mut W {
360 self.variant(SOURCESEL_A::LETIMER0)
361 }
362 #[doc = "Pulse Counter 0"]
363 #[inline(always)]
364 pub fn pcnt0(self) -> &'a mut W {
365 self.variant(SOURCESEL_A::PCNT0)
366 }
367 #[doc = "Pulse Counter 1"]
368 #[inline(always)]
369 pub fn pcnt1(self) -> &'a mut W {
370 self.variant(SOURCESEL_A::PCNT1)
371 }
372 #[doc = "Pulse Counter 2"]
373 #[inline(always)]
374 pub fn pcnt2(self) -> &'a mut W {
375 self.variant(SOURCESEL_A::PCNT2)
376 }
377 #[doc = "Clock Management Unit"]
378 #[inline(always)]
379 pub fn cmu(self) -> &'a mut W {
380 self.variant(SOURCESEL_A::CMU)
381 }
382 #[doc = "Digital to Analog Converter 0"]
383 #[inline(always)]
384 pub fn vdac0(self) -> &'a mut W {
385 self.variant(SOURCESEL_A::VDAC0)
386 }
387 #[doc = "CRYOTIMER"]
388 #[inline(always)]
389 pub fn cryotimer(self) -> &'a mut W {
390 self.variant(SOURCESEL_A::CRYOTIMER)
391 }
392 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
393 #[inline(always)]
394 pub fn usart0(self) -> &'a mut W {
395 self.variant(SOURCESEL_A::USART0)
396 }
397 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
398 #[inline(always)]
399 pub fn usart1(self) -> &'a mut W {
400 self.variant(SOURCESEL_A::USART1)
401 }
402 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
403 #[inline(always)]
404 pub fn usart2(self) -> &'a mut W {
405 self.variant(SOURCESEL_A::USART2)
406 }
407 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
408 #[inline(always)]
409 pub fn usart3(self) -> &'a mut W {
410 self.variant(SOURCESEL_A::USART3)
411 }
412 #[doc = "Timer 0"]
413 #[inline(always)]
414 pub fn timer0(self) -> &'a mut W {
415 self.variant(SOURCESEL_A::TIMER0)
416 }
417 #[doc = "Timer 1"]
418 #[inline(always)]
419 pub fn timer1(self) -> &'a mut W {
420 self.variant(SOURCESEL_A::TIMER1)
421 }
422 #[doc = "Wide Timer 0"]
423 #[inline(always)]
424 pub fn wtimer0(self) -> &'a mut W {
425 self.variant(SOURCESEL_A::WTIMER0)
426 }
427 #[doc = "Wide Timer 1"]
428 #[inline(always)]
429 pub fn wtimer1(self) -> &'a mut W {
430 self.variant(SOURCESEL_A::WTIMER1)
431 }
432 #[doc = "`1000011`"]
433 #[inline(always)]
434 pub fn cm4(self) -> &'a mut W {
435 self.variant(SOURCESEL_A::CM4)
436 }
437 #[doc = r"Writes raw bits to the field"]
438 #[inline(always)]
439 pub unsafe fn bits(self, value: u8) -> &'a mut W {
440 self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
441 self.w
442 }
443}
444#[doc = "Edge Detect Select\n\nValue on reset: 0"]
445#[derive(Clone, Copy, Debug, PartialEq)]
446#[repr(u8)]
447pub enum EDSEL_A {
448 #[doc = "0: Signal is left as it is"]
449 OFF = 0,
450 #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
451 POSEDGE = 1,
452 #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
453 NEGEDGE = 2,
454 #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
455 BOTHEDGES = 3,
456}
457impl From<EDSEL_A> for u8 {
458 #[inline(always)]
459 fn from(variant: EDSEL_A) -> Self {
460 variant as _
461 }
462}
463#[doc = "Reader of field `EDSEL`"]
464pub type EDSEL_R = crate::R<u8, EDSEL_A>;
465impl EDSEL_R {
466 #[doc = r"Get enumerated values variant"]
467 #[inline(always)]
468 pub fn variant(&self) -> EDSEL_A {
469 match self.bits {
470 0 => EDSEL_A::OFF,
471 1 => EDSEL_A::POSEDGE,
472 2 => EDSEL_A::NEGEDGE,
473 3 => EDSEL_A::BOTHEDGES,
474 _ => unreachable!(),
475 }
476 }
477 #[doc = "Checks if the value of the field is `OFF`"]
478 #[inline(always)]
479 pub fn is_off(&self) -> bool {
480 *self == EDSEL_A::OFF
481 }
482 #[doc = "Checks if the value of the field is `POSEDGE`"]
483 #[inline(always)]
484 pub fn is_posedge(&self) -> bool {
485 *self == EDSEL_A::POSEDGE
486 }
487 #[doc = "Checks if the value of the field is `NEGEDGE`"]
488 #[inline(always)]
489 pub fn is_negedge(&self) -> bool {
490 *self == EDSEL_A::NEGEDGE
491 }
492 #[doc = "Checks if the value of the field is `BOTHEDGES`"]
493 #[inline(always)]
494 pub fn is_bothedges(&self) -> bool {
495 *self == EDSEL_A::BOTHEDGES
496 }
497}
498#[doc = "Write proxy for field `EDSEL`"]
499pub struct EDSEL_W<'a> {
500 w: &'a mut W,
501}
502impl<'a> EDSEL_W<'a> {
503 #[doc = r"Writes `variant` to the field"]
504 #[inline(always)]
505 pub fn variant(self, variant: EDSEL_A) -> &'a mut W {
506 {
507 self.bits(variant.into())
508 }
509 }
510 #[doc = "Signal is left as it is"]
511 #[inline(always)]
512 pub fn off(self) -> &'a mut W {
513 self.variant(EDSEL_A::OFF)
514 }
515 #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
516 #[inline(always)]
517 pub fn posedge(self) -> &'a mut W {
518 self.variant(EDSEL_A::POSEDGE)
519 }
520 #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
521 #[inline(always)]
522 pub fn negedge(self) -> &'a mut W {
523 self.variant(EDSEL_A::NEGEDGE)
524 }
525 #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
526 #[inline(always)]
527 pub fn bothedges(self) -> &'a mut W {
528 self.variant(EDSEL_A::BOTHEDGES)
529 }
530 #[doc = r"Writes raw bits to the field"]
531 #[inline(always)]
532 pub fn bits(self, value: u8) -> &'a mut W {
533 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
534 self.w
535 }
536}
537#[doc = "Reader of field `STRETCH`"]
538pub type STRETCH_R = crate::R<bool, bool>;
539#[doc = "Write proxy for field `STRETCH`"]
540pub struct STRETCH_W<'a> {
541 w: &'a mut W,
542}
543impl<'a> STRETCH_W<'a> {
544 #[doc = r"Sets the field bit"]
545 #[inline(always)]
546 pub fn set_bit(self) -> &'a mut W {
547 self.bit(true)
548 }
549 #[doc = r"Clears the field bit"]
550 #[inline(always)]
551 pub fn clear_bit(self) -> &'a mut W {
552 self.bit(false)
553 }
554 #[doc = r"Writes raw bits to the field"]
555 #[inline(always)]
556 pub fn bit(self, value: bool) -> &'a mut W {
557 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
558 self.w
559 }
560}
561#[doc = "Reader of field `INV`"]
562pub type INV_R = crate::R<bool, bool>;
563#[doc = "Write proxy for field `INV`"]
564pub struct INV_W<'a> {
565 w: &'a mut W,
566}
567impl<'a> INV_W<'a> {
568 #[doc = r"Sets the field bit"]
569 #[inline(always)]
570 pub fn set_bit(self) -> &'a mut W {
571 self.bit(true)
572 }
573 #[doc = r"Clears the field bit"]
574 #[inline(always)]
575 pub fn clear_bit(self) -> &'a mut W {
576 self.bit(false)
577 }
578 #[doc = r"Writes raw bits to the field"]
579 #[inline(always)]
580 pub fn bit(self, value: bool) -> &'a mut W {
581 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
582 self.w
583 }
584}
585#[doc = "Reader of field `ORPREV`"]
586pub type ORPREV_R = crate::R<bool, bool>;
587#[doc = "Write proxy for field `ORPREV`"]
588pub struct ORPREV_W<'a> {
589 w: &'a mut W,
590}
591impl<'a> ORPREV_W<'a> {
592 #[doc = r"Sets the field bit"]
593 #[inline(always)]
594 pub fn set_bit(self) -> &'a mut W {
595 self.bit(true)
596 }
597 #[doc = r"Clears the field bit"]
598 #[inline(always)]
599 pub fn clear_bit(self) -> &'a mut W {
600 self.bit(false)
601 }
602 #[doc = r"Writes raw bits to the field"]
603 #[inline(always)]
604 pub fn bit(self, value: bool) -> &'a mut W {
605 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
606 self.w
607 }
608}
609#[doc = "Reader of field `ANDNEXT`"]
610pub type ANDNEXT_R = crate::R<bool, bool>;
611#[doc = "Write proxy for field `ANDNEXT`"]
612pub struct ANDNEXT_W<'a> {
613 w: &'a mut W,
614}
615impl<'a> ANDNEXT_W<'a> {
616 #[doc = r"Sets the field bit"]
617 #[inline(always)]
618 pub fn set_bit(self) -> &'a mut W {
619 self.bit(true)
620 }
621 #[doc = r"Clears the field bit"]
622 #[inline(always)]
623 pub fn clear_bit(self) -> &'a mut W {
624 self.bit(false)
625 }
626 #[doc = r"Writes raw bits to the field"]
627 #[inline(always)]
628 pub fn bit(self, value: bool) -> &'a mut W {
629 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
630 self.w
631 }
632}
633#[doc = "Reader of field `ASYNC`"]
634pub type ASYNC_R = crate::R<bool, bool>;
635#[doc = "Write proxy for field `ASYNC`"]
636pub struct ASYNC_W<'a> {
637 w: &'a mut W,
638}
639impl<'a> ASYNC_W<'a> {
640 #[doc = r"Sets the field bit"]
641 #[inline(always)]
642 pub fn set_bit(self) -> &'a mut W {
643 self.bit(true)
644 }
645 #[doc = r"Clears the field bit"]
646 #[inline(always)]
647 pub fn clear_bit(self) -> &'a mut W {
648 self.bit(false)
649 }
650 #[doc = r"Writes raw bits to the field"]
651 #[inline(always)]
652 pub fn bit(self, value: bool) -> &'a mut W {
653 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
654 self.w
655 }
656}
657impl R {
658 #[doc = "Bits 0:2 - Signal Select"]
659 #[inline(always)]
660 pub fn sigsel(&self) -> SIGSEL_R {
661 SIGSEL_R::new((self.bits & 0x07) as u8)
662 }
663 #[doc = "Bits 8:14 - Source Select"]
664 #[inline(always)]
665 pub fn sourcesel(&self) -> SOURCESEL_R {
666 SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
667 }
668 #[doc = "Bits 20:21 - Edge Detect Select"]
669 #[inline(always)]
670 pub fn edsel(&self) -> EDSEL_R {
671 EDSEL_R::new(((self.bits >> 20) & 0x03) as u8)
672 }
673 #[doc = "Bit 25 - Stretch Channel Output"]
674 #[inline(always)]
675 pub fn stretch(&self) -> STRETCH_R {
676 STRETCH_R::new(((self.bits >> 25) & 0x01) != 0)
677 }
678 #[doc = "Bit 26 - Invert Channel"]
679 #[inline(always)]
680 pub fn inv(&self) -> INV_R {
681 INV_R::new(((self.bits >> 26) & 0x01) != 0)
682 }
683 #[doc = "Bit 27 - Or Previous"]
684 #[inline(always)]
685 pub fn orprev(&self) -> ORPREV_R {
686 ORPREV_R::new(((self.bits >> 27) & 0x01) != 0)
687 }
688 #[doc = "Bit 28 - And Next"]
689 #[inline(always)]
690 pub fn andnext(&self) -> ANDNEXT_R {
691 ANDNEXT_R::new(((self.bits >> 28) & 0x01) != 0)
692 }
693 #[doc = "Bit 30 - Asynchronous Reflex"]
694 #[inline(always)]
695 pub fn async_(&self) -> ASYNC_R {
696 ASYNC_R::new(((self.bits >> 30) & 0x01) != 0)
697 }
698}
699impl W {
700 #[doc = "Bits 0:2 - Signal Select"]
701 #[inline(always)]
702 pub fn sigsel(&mut self) -> SIGSEL_W {
703 SIGSEL_W { w: self }
704 }
705 #[doc = "Bits 8:14 - Source Select"]
706 #[inline(always)]
707 pub fn sourcesel(&mut self) -> SOURCESEL_W {
708 SOURCESEL_W { w: self }
709 }
710 #[doc = "Bits 20:21 - Edge Detect Select"]
711 #[inline(always)]
712 pub fn edsel(&mut self) -> EDSEL_W {
713 EDSEL_W { w: self }
714 }
715 #[doc = "Bit 25 - Stretch Channel Output"]
716 #[inline(always)]
717 pub fn stretch(&mut self) -> STRETCH_W {
718 STRETCH_W { w: self }
719 }
720 #[doc = "Bit 26 - Invert Channel"]
721 #[inline(always)]
722 pub fn inv(&mut self) -> INV_W {
723 INV_W { w: self }
724 }
725 #[doc = "Bit 27 - Or Previous"]
726 #[inline(always)]
727 pub fn orprev(&mut self) -> ORPREV_W {
728 ORPREV_W { w: self }
729 }
730 #[doc = "Bit 28 - And Next"]
731 #[inline(always)]
732 pub fn andnext(&mut self) -> ANDNEXT_W {
733 ANDNEXT_W { w: self }
734 }
735 #[doc = "Bit 30 - Asynchronous Reflex"]
736 #[inline(always)]
737 pub fn async_(&mut self) -> ASYNC_W {
738 ASYNC_W { w: self }
739 }
740}