efm32pg12_pac/emu/
vmonio0ctrl.rs1#[doc = "Reader of register VMONIO0CTRL"]
2pub type R = crate::R<u32, super::VMONIO0CTRL>;
3#[doc = "Writer for register VMONIO0CTRL"]
4pub type W = crate::W<u32, super::VMONIO0CTRL>;
5#[doc = "Register VMONIO0CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::VMONIO0CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `EN`"]
14pub type EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `EN`"]
16pub struct EN_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> EN_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `RISEWU`"]
38pub type RISEWU_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `RISEWU`"]
40pub struct RISEWU_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> RISEWU_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
58 self.w
59 }
60}
61#[doc = "Reader of field `FALLWU`"]
62pub type FALLWU_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `FALLWU`"]
64pub struct FALLWU_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> FALLWU_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
82 self.w
83 }
84}
85#[doc = "Reader of field `RETDIS`"]
86pub type RETDIS_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `RETDIS`"]
88pub struct RETDIS_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> RETDIS_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
106 self.w
107 }
108}
109#[doc = "Reader of field `THRESFINE`"]
110pub type THRESFINE_R = crate::R<u8, u8>;
111#[doc = "Write proxy for field `THRESFINE`"]
112pub struct THRESFINE_W<'a> {
113 w: &'a mut W,
114}
115impl<'a> THRESFINE_W<'a> {
116 #[doc = r"Writes raw bits to the field"]
117 #[inline(always)]
118 pub unsafe fn bits(self, value: u8) -> &'a mut W {
119 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
120 self.w
121 }
122}
123#[doc = "Reader of field `THRESCOARSE`"]
124pub type THRESCOARSE_R = crate::R<u8, u8>;
125#[doc = "Write proxy for field `THRESCOARSE`"]
126pub struct THRESCOARSE_W<'a> {
127 w: &'a mut W,
128}
129impl<'a> THRESCOARSE_W<'a> {
130 #[doc = r"Writes raw bits to the field"]
131 #[inline(always)]
132 pub unsafe fn bits(self, value: u8) -> &'a mut W {
133 self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
134 self.w
135 }
136}
137impl R {
138 #[doc = "Bit 0 - Enable"]
139 #[inline(always)]
140 pub fn en(&self) -> EN_R {
141 EN_R::new((self.bits & 0x01) != 0)
142 }
143 #[doc = "Bit 2 - Rise Wakeup"]
144 #[inline(always)]
145 pub fn risewu(&self) -> RISEWU_R {
146 RISEWU_R::new(((self.bits >> 2) & 0x01) != 0)
147 }
148 #[doc = "Bit 3 - Fall Wakeup"]
149 #[inline(always)]
150 pub fn fallwu(&self) -> FALLWU_R {
151 FALLWU_R::new(((self.bits >> 3) & 0x01) != 0)
152 }
153 #[doc = "Bit 4 - EM4 IO0 Retention Disable"]
154 #[inline(always)]
155 pub fn retdis(&self) -> RETDIS_R {
156 RETDIS_R::new(((self.bits >> 4) & 0x01) != 0)
157 }
158 #[doc = "Bits 8:11 - Threshold Fine Adjust"]
159 #[inline(always)]
160 pub fn thresfine(&self) -> THRESFINE_R {
161 THRESFINE_R::new(((self.bits >> 8) & 0x0f) as u8)
162 }
163 #[doc = "Bits 12:15 - Threshold Coarse Adjust"]
164 #[inline(always)]
165 pub fn threscoarse(&self) -> THRESCOARSE_R {
166 THRESCOARSE_R::new(((self.bits >> 12) & 0x0f) as u8)
167 }
168}
169impl W {
170 #[doc = "Bit 0 - Enable"]
171 #[inline(always)]
172 pub fn en(&mut self) -> EN_W {
173 EN_W { w: self }
174 }
175 #[doc = "Bit 2 - Rise Wakeup"]
176 #[inline(always)]
177 pub fn risewu(&mut self) -> RISEWU_W {
178 RISEWU_W { w: self }
179 }
180 #[doc = "Bit 3 - Fall Wakeup"]
181 #[inline(always)]
182 pub fn fallwu(&mut self) -> FALLWU_W {
183 FALLWU_W { w: self }
184 }
185 #[doc = "Bit 4 - EM4 IO0 Retention Disable"]
186 #[inline(always)]
187 pub fn retdis(&mut self) -> RETDIS_W {
188 RETDIS_W { w: self }
189 }
190 #[doc = "Bits 8:11 - Threshold Fine Adjust"]
191 #[inline(always)]
192 pub fn thresfine(&mut self) -> THRESFINE_W {
193 THRESFINE_W { w: self }
194 }
195 #[doc = "Bits 12:15 - Threshold Coarse Adjust"]
196 #[inline(always)]
197 pub fn threscoarse(&mut self) -> THRESCOARSE_W {
198 THRESCOARSE_W { w: self }
199 }
200}