efm32pg12_pac/csen/
ien.rs

1#[doc = "Reader of register IEN"]
2pub type R = crate::R<u32, super::IEN>;
3#[doc = "Writer for register IEN"]
4pub type W = crate::W<u32, super::IEN>;
5#[doc = "Register IEN `reset()`'s with value 0"]
6impl crate::ResetValue for super::IEN {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CMP`"]
14pub type CMP_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `CMP`"]
16pub struct CMP_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CMP_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `CONV`"]
38pub type CONV_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `CONV`"]
40pub struct CONV_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> CONV_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `EOS`"]
62pub type EOS_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `EOS`"]
64pub struct EOS_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> EOS_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `DMAOF`"]
86pub type DMAOF_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DMAOF`"]
88pub struct DMAOF_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DMAOF_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `APORTCONFLICT`"]
110pub type APORTCONFLICT_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `APORTCONFLICT`"]
112pub struct APORTCONFLICT_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> APORTCONFLICT_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133impl R {
134    #[doc = "Bit 0 - CMP Interrupt Enable"]
135    #[inline(always)]
136    pub fn cmp(&self) -> CMP_R {
137        CMP_R::new((self.bits & 0x01) != 0)
138    }
139    #[doc = "Bit 1 - CONV Interrupt Enable"]
140    #[inline(always)]
141    pub fn conv(&self) -> CONV_R {
142        CONV_R::new(((self.bits >> 1) & 0x01) != 0)
143    }
144    #[doc = "Bit 2 - EOS Interrupt Enable"]
145    #[inline(always)]
146    pub fn eos(&self) -> EOS_R {
147        EOS_R::new(((self.bits >> 2) & 0x01) != 0)
148    }
149    #[doc = "Bit 3 - DMAOF Interrupt Enable"]
150    #[inline(always)]
151    pub fn dmaof(&self) -> DMAOF_R {
152        DMAOF_R::new(((self.bits >> 3) & 0x01) != 0)
153    }
154    #[doc = "Bit 4 - APORTCONFLICT Interrupt Enable"]
155    #[inline(always)]
156    pub fn aportconflict(&self) -> APORTCONFLICT_R {
157        APORTCONFLICT_R::new(((self.bits >> 4) & 0x01) != 0)
158    }
159}
160impl W {
161    #[doc = "Bit 0 - CMP Interrupt Enable"]
162    #[inline(always)]
163    pub fn cmp(&mut self) -> CMP_W {
164        CMP_W { w: self }
165    }
166    #[doc = "Bit 1 - CONV Interrupt Enable"]
167    #[inline(always)]
168    pub fn conv(&mut self) -> CONV_W {
169        CONV_W { w: self }
170    }
171    #[doc = "Bit 2 - EOS Interrupt Enable"]
172    #[inline(always)]
173    pub fn eos(&mut self) -> EOS_W {
174        EOS_W { w: self }
175    }
176    #[doc = "Bit 3 - DMAOF Interrupt Enable"]
177    #[inline(always)]
178    pub fn dmaof(&mut self) -> DMAOF_W {
179        DMAOF_W { w: self }
180    }
181    #[doc = "Bit 4 - APORTCONFLICT Interrupt Enable"]
182    #[inline(always)]
183    pub fn aportconflict(&mut self) -> APORTCONFLICT_W {
184        APORTCONFLICT_W { w: self }
185    }
186}
efm32pg12_pac/csen/ien.rs

efm32pg12_pac/csen/
ien.rs
