efm32pg12_pac/msc/
readctrl.rs

1#[doc = "Reader of register READCTRL"]
2pub type R = crate::R<u32, super::READCTRL>;
3#[doc = "Writer for register READCTRL"]
4pub type W = crate::W<u32, super::READCTRL>;
5#[doc = "Register READCTRL `reset()`'s with value 0x0100_0100"]
6impl crate::ResetValue for super::READCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0100_0100
11    }
12}
13#[doc = "Reader of field `IFCDIS`"]
14pub type IFCDIS_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `IFCDIS`"]
16pub struct IFCDIS_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> IFCDIS_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
34        self.w
35    }
36}
37#[doc = "Reader of field `AIDIS`"]
38pub type AIDIS_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `AIDIS`"]
40pub struct AIDIS_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> AIDIS_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
58        self.w
59    }
60}
61#[doc = "Reader of field `ICCDIS`"]
62pub type ICCDIS_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `ICCDIS`"]
64pub struct ICCDIS_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> ICCDIS_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
82        self.w
83    }
84}
85#[doc = "Reader of field `PREFETCH`"]
86pub type PREFETCH_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `PREFETCH`"]
88pub struct PREFETCH_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> PREFETCH_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
106        self.w
107    }
108}
109#[doc = "Reader of field `USEHPROT`"]
110pub type USEHPROT_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `USEHPROT`"]
112pub struct USEHPROT_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> USEHPROT_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
130        self.w
131    }
132}
133#[doc = "Read Mode\n\nValue on reset: 1"]
134#[derive(Clone, Copy, Debug, PartialEq)]
135#[repr(u8)]
136pub enum MODE_A {
137    #[doc = "0: Zero wait-states inserted in fetch or read transfers"]
138    WS0 = 0,
139    #[doc = "1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
140    WS1 = 1,
141    #[doc = "2: Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
142    WS2 = 2,
143    #[doc = "3: Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
144    WS3 = 3,
145}
146impl From<MODE_A> for u8 {
147    #[inline(always)]
148    fn from(variant: MODE_A) -> Self {
149        variant as _
150    }
151}
152#[doc = "Reader of field `MODE`"]
153pub type MODE_R = crate::R<u8, MODE_A>;
154impl MODE_R {
155    #[doc = r"Get enumerated values variant"]
156    #[inline(always)]
157    pub fn variant(&self) -> MODE_A {
158        match self.bits {
159            0 => MODE_A::WS0,
160            1 => MODE_A::WS1,
161            2 => MODE_A::WS2,
162            3 => MODE_A::WS3,
163            _ => unreachable!(),
164        }
165    }
166    #[doc = "Checks if the value of the field is `WS0`"]
167    #[inline(always)]
168    pub fn is_ws0(&self) -> bool {
169        *self == MODE_A::WS0
170    }
171    #[doc = "Checks if the value of the field is `WS1`"]
172    #[inline(always)]
173    pub fn is_ws1(&self) -> bool {
174        *self == MODE_A::WS1
175    }
176    #[doc = "Checks if the value of the field is `WS2`"]
177    #[inline(always)]
178    pub fn is_ws2(&self) -> bool {
179        *self == MODE_A::WS2
180    }
181    #[doc = "Checks if the value of the field is `WS3`"]
182    #[inline(always)]
183    pub fn is_ws3(&self) -> bool {
184        *self == MODE_A::WS3
185    }
186}
187#[doc = "Write proxy for field `MODE`"]
188pub struct MODE_W<'a> {
189    w: &'a mut W,
190}
191impl<'a> MODE_W<'a> {
192    #[doc = r"Writes `variant` to the field"]
193    #[inline(always)]
194    pub fn variant(self, variant: MODE_A) -> &'a mut W {
195        {
196            self.bits(variant.into())
197        }
198    }
199    #[doc = "Zero wait-states inserted in fetch or read transfers"]
200    #[inline(always)]
201    pub fn ws0(self) -> &'a mut W {
202        self.variant(MODE_A::WS0)
203    }
204    #[doc = "One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
205    #[inline(always)]
206    pub fn ws1(self) -> &'a mut W {
207        self.variant(MODE_A::WS1)
208    }
209    #[doc = "Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
210    #[inline(always)]
211    pub fn ws2(self) -> &'a mut W {
212        self.variant(MODE_A::WS2)
213    }
214    #[doc = "Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
215    #[inline(always)]
216    pub fn ws3(self) -> &'a mut W {
217        self.variant(MODE_A::WS3)
218    }
219    #[doc = r"Writes raw bits to the field"]
220    #[inline(always)]
221    pub fn bits(self, value: u8) -> &'a mut W {
222        self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
223        self.w
224    }
225}
226#[doc = "Reader of field `SCBTP`"]
227pub type SCBTP_R = crate::R<bool, bool>;
228#[doc = "Write proxy for field `SCBTP`"]
229pub struct SCBTP_W<'a> {
230    w: &'a mut W,
231}
232impl<'a> SCBTP_W<'a> {
233    #[doc = r"Sets the field bit"]
234    #[inline(always)]
235    pub fn set_bit(self) -> &'a mut W {
236        self.bit(true)
237    }
238    #[doc = r"Clears the field bit"]
239    #[inline(always)]
240    pub fn clear_bit(self) -> &'a mut W {
241        self.bit(false)
242    }
243    #[doc = r"Writes raw bits to the field"]
244    #[inline(always)]
245    pub fn bit(self, value: bool) -> &'a mut W {
246        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
247        self.w
248    }
249}
250impl R {
251    #[doc = "Bit 3 - Internal Flash Cache Disable"]
252    #[inline(always)]
253    pub fn ifcdis(&self) -> IFCDIS_R {
254        IFCDIS_R::new(((self.bits >> 3) & 0x01) != 0)
255    }
256    #[doc = "Bit 4 - Automatic Invalidate Disable"]
257    #[inline(always)]
258    pub fn aidis(&self) -> AIDIS_R {
259        AIDIS_R::new(((self.bits >> 4) & 0x01) != 0)
260    }
261    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
262    #[inline(always)]
263    pub fn iccdis(&self) -> ICCDIS_R {
264        ICCDIS_R::new(((self.bits >> 5) & 0x01) != 0)
265    }
266    #[doc = "Bit 8 - Prefetch Mode"]
267    #[inline(always)]
268    pub fn prefetch(&self) -> PREFETCH_R {
269        PREFETCH_R::new(((self.bits >> 8) & 0x01) != 0)
270    }
271    #[doc = "Bit 9 - AHB_HPROT Mode"]
272    #[inline(always)]
273    pub fn usehprot(&self) -> USEHPROT_R {
274        USEHPROT_R::new(((self.bits >> 9) & 0x01) != 0)
275    }
276    #[doc = "Bits 24:25 - Read Mode"]
277    #[inline(always)]
278    pub fn mode(&self) -> MODE_R {
279        MODE_R::new(((self.bits >> 24) & 0x03) as u8)
280    }
281    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
282    #[inline(always)]
283    pub fn scbtp(&self) -> SCBTP_R {
284        SCBTP_R::new(((self.bits >> 28) & 0x01) != 0)
285    }
286}
287impl W {
288    #[doc = "Bit 3 - Internal Flash Cache Disable"]
289    #[inline(always)]
290    pub fn ifcdis(&mut self) -> IFCDIS_W {
291        IFCDIS_W { w: self }
292    }
293    #[doc = "Bit 4 - Automatic Invalidate Disable"]
294    #[inline(always)]
295    pub fn aidis(&mut self) -> AIDIS_W {
296        AIDIS_W { w: self }
297    }
298    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
299    #[inline(always)]
300    pub fn iccdis(&mut self) -> ICCDIS_W {
301        ICCDIS_W { w: self }
302    }
303    #[doc = "Bit 8 - Prefetch Mode"]
304    #[inline(always)]
305    pub fn prefetch(&mut self) -> PREFETCH_W {
306        PREFETCH_W { w: self }
307    }
308    #[doc = "Bit 9 - AHB_HPROT Mode"]
309    #[inline(always)]
310    pub fn usehprot(&mut self) -> USEHPROT_W {
311        USEHPROT_W { w: self }
312    }
313    #[doc = "Bits 24:25 - Read Mode"]
314    #[inline(always)]
315    pub fn mode(&mut self) -> MODE_W {
316        MODE_W { w: self }
317    }
318    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
319    #[inline(always)]
320    pub fn scbtp(&mut self) -> SCBTP_W {
321        SCBTP_W { w: self }
322    }
323}
efm32pg12_pac/msc/readctrl.rs

efm32pg12_pac/msc/
readctrl.rs
