efm32pg12_pac/wtimer0/
routepen.rs

1#[doc = "Reader of register ROUTEPEN"]
2pub type R = crate::R<u32, super::ROUTEPEN>;
3#[doc = "Writer for register ROUTEPEN"]
4pub type W = crate::W<u32, super::ROUTEPEN>;
5#[doc = "Register ROUTEPEN `reset()`'s with value 0"]
6impl crate::ResetValue for super::ROUTEPEN {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CC0PEN`"]
14pub type CC0PEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `CC0PEN`"]
16pub struct CC0PEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CC0PEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `CC1PEN`"]
38pub type CC1PEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `CC1PEN`"]
40pub struct CC1PEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> CC1PEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `CC2PEN`"]
62pub type CC2PEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `CC2PEN`"]
64pub struct CC2PEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> CC2PEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `CC3PEN`"]
86pub type CC3PEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `CC3PEN`"]
88pub struct CC3PEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> CC3PEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `CDTI0PEN`"]
110pub type CDTI0PEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `CDTI0PEN`"]
112pub struct CDTI0PEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> CDTI0PEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
130        self.w
131    }
132}
133#[doc = "Reader of field `CDTI1PEN`"]
134pub type CDTI1PEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `CDTI1PEN`"]
136pub struct CDTI1PEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> CDTI1PEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
154        self.w
155    }
156}
157#[doc = "Reader of field `CDTI2PEN`"]
158pub type CDTI2PEN_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `CDTI2PEN`"]
160pub struct CDTI2PEN_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> CDTI2PEN_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
178        self.w
179    }
180}
181impl R {
182    #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
183    #[inline(always)]
184    pub fn cc0pen(&self) -> CC0PEN_R {
185        CC0PEN_R::new((self.bits & 0x01) != 0)
186    }
187    #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
188    #[inline(always)]
189    pub fn cc1pen(&self) -> CC1PEN_R {
190        CC1PEN_R::new(((self.bits >> 1) & 0x01) != 0)
191    }
192    #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
193    #[inline(always)]
194    pub fn cc2pen(&self) -> CC2PEN_R {
195        CC2PEN_R::new(((self.bits >> 2) & 0x01) != 0)
196    }
197    #[doc = "Bit 3 - CC Channel 3 Pin Enable"]
198    #[inline(always)]
199    pub fn cc3pen(&self) -> CC3PEN_R {
200        CC3PEN_R::new(((self.bits >> 3) & 0x01) != 0)
201    }
202    #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
203    #[inline(always)]
204    pub fn cdti0pen(&self) -> CDTI0PEN_R {
205        CDTI0PEN_R::new(((self.bits >> 8) & 0x01) != 0)
206    }
207    #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
208    #[inline(always)]
209    pub fn cdti1pen(&self) -> CDTI1PEN_R {
210        CDTI1PEN_R::new(((self.bits >> 9) & 0x01) != 0)
211    }
212    #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
213    #[inline(always)]
214    pub fn cdti2pen(&self) -> CDTI2PEN_R {
215        CDTI2PEN_R::new(((self.bits >> 10) & 0x01) != 0)
216    }
217}
218impl W {
219    #[doc = "Bit 0 - CC Channel 0 Pin Enable"]
220    #[inline(always)]
221    pub fn cc0pen(&mut self) -> CC0PEN_W {
222        CC0PEN_W { w: self }
223    }
224    #[doc = "Bit 1 - CC Channel 1 Pin Enable"]
225    #[inline(always)]
226    pub fn cc1pen(&mut self) -> CC1PEN_W {
227        CC1PEN_W { w: self }
228    }
229    #[doc = "Bit 2 - CC Channel 2 Pin Enable"]
230    #[inline(always)]
231    pub fn cc2pen(&mut self) -> CC2PEN_W {
232        CC2PEN_W { w: self }
233    }
234    #[doc = "Bit 3 - CC Channel 3 Pin Enable"]
235    #[inline(always)]
236    pub fn cc3pen(&mut self) -> CC3PEN_W {
237        CC3PEN_W { w: self }
238    }
239    #[doc = "Bit 8 - CC Channel 0 Complementary Dead-Time Insertion Pin Enable"]
240    #[inline(always)]
241    pub fn cdti0pen(&mut self) -> CDTI0PEN_W {
242        CDTI0PEN_W { w: self }
243    }
244    #[doc = "Bit 9 - CC Channel 1 Complementary Dead-Time Insertion Pin Enable"]
245    #[inline(always)]
246    pub fn cdti1pen(&mut self) -> CDTI1PEN_W {
247        CDTI1PEN_W { w: self }
248    }
249    #[doc = "Bit 10 - CC Channel 2 Complementary Dead-Time Insertion Pin Enable"]
250    #[inline(always)]
251    pub fn cdti2pen(&mut self) -> CDTI2PEN_W {
252        CDTI2PEN_W { w: self }
253    }
254}
efm32pg12_pac/wtimer0/routepen.rs

efm32pg12_pac/wtimer0/
routepen.rs
