1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `AES`"]
14pub type AES_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `AES`"]
16pub struct AES_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> AES_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `KEYBUFDIS`"]
38pub type KEYBUFDIS_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `KEYBUFDIS`"]
40pub struct KEYBUFDIS_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> KEYBUFDIS_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `SHA`"]
62pub type SHA_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `SHA`"]
64pub struct SHA_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> SHA_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82 self.w
83 }
84}
85#[doc = "Reader of field `NOBUSYSTALL`"]
86pub type NOBUSYSTALL_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `NOBUSYSTALL`"]
88pub struct NOBUSYSTALL_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> NOBUSYSTALL_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
106 self.w
107 }
108}
109#[doc = "Increment Width\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq)]
111#[repr(u8)]
112pub enum INCWIDTH_A {
113 #[doc = "0: Byte 15 in DATA1 is used for the increment function."]
114 INCWIDTH1 = 0,
115 #[doc = "1: Bytes 14 and 15 in DATA1 are used for the increment function."]
116 INCWIDTH2 = 1,
117 #[doc = "2: Bytes 13 to 15 in DATA1 are used for the increment function."]
118 INCWIDTH3 = 2,
119 #[doc = "3: Bytes 12 to 15 in DATA1 are used for the increment function."]
120 INCWIDTH4 = 3,
121}
122impl From<INCWIDTH_A> for u8 {
123 #[inline(always)]
124 fn from(variant: INCWIDTH_A) -> Self {
125 variant as _
126 }
127}
128#[doc = "Reader of field `INCWIDTH`"]
129pub type INCWIDTH_R = crate::R<u8, INCWIDTH_A>;
130impl INCWIDTH_R {
131 #[doc = r"Get enumerated values variant"]
132 #[inline(always)]
133 pub fn variant(&self) -> INCWIDTH_A {
134 match self.bits {
135 0 => INCWIDTH_A::INCWIDTH1,
136 1 => INCWIDTH_A::INCWIDTH2,
137 2 => INCWIDTH_A::INCWIDTH3,
138 3 => INCWIDTH_A::INCWIDTH4,
139 _ => unreachable!(),
140 }
141 }
142 #[doc = "Checks if the value of the field is `INCWIDTH1`"]
143 #[inline(always)]
144 pub fn is_incwidth1(&self) -> bool {
145 *self == INCWIDTH_A::INCWIDTH1
146 }
147 #[doc = "Checks if the value of the field is `INCWIDTH2`"]
148 #[inline(always)]
149 pub fn is_incwidth2(&self) -> bool {
150 *self == INCWIDTH_A::INCWIDTH2
151 }
152 #[doc = "Checks if the value of the field is `INCWIDTH3`"]
153 #[inline(always)]
154 pub fn is_incwidth3(&self) -> bool {
155 *self == INCWIDTH_A::INCWIDTH3
156 }
157 #[doc = "Checks if the value of the field is `INCWIDTH4`"]
158 #[inline(always)]
159 pub fn is_incwidth4(&self) -> bool {
160 *self == INCWIDTH_A::INCWIDTH4
161 }
162}
163#[doc = "Write proxy for field `INCWIDTH`"]
164pub struct INCWIDTH_W<'a> {
165 w: &'a mut W,
166}
167impl<'a> INCWIDTH_W<'a> {
168 #[doc = r"Writes `variant` to the field"]
169 #[inline(always)]
170 pub fn variant(self, variant: INCWIDTH_A) -> &'a mut W {
171 {
172 self.bits(variant.into())
173 }
174 }
175 #[doc = "Byte 15 in DATA1 is used for the increment function."]
176 #[inline(always)]
177 pub fn incwidth1(self) -> &'a mut W {
178 self.variant(INCWIDTH_A::INCWIDTH1)
179 }
180 #[doc = "Bytes 14 and 15 in DATA1 are used for the increment function."]
181 #[inline(always)]
182 pub fn incwidth2(self) -> &'a mut W {
183 self.variant(INCWIDTH_A::INCWIDTH2)
184 }
185 #[doc = "Bytes 13 to 15 in DATA1 are used for the increment function."]
186 #[inline(always)]
187 pub fn incwidth3(self) -> &'a mut W {
188 self.variant(INCWIDTH_A::INCWIDTH3)
189 }
190 #[doc = "Bytes 12 to 15 in DATA1 are used for the increment function."]
191 #[inline(always)]
192 pub fn incwidth4(self) -> &'a mut W {
193 self.variant(INCWIDTH_A::INCWIDTH4)
194 }
195 #[doc = r"Writes raw bits to the field"]
196 #[inline(always)]
197 pub fn bits(self, value: u8) -> &'a mut W {
198 self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
199 self.w
200 }
201}
202#[doc = "DMA0 Read Mode\n\nValue on reset: 0"]
203#[derive(Clone, Copy, Debug, PartialEq)]
204#[repr(u8)]
205pub enum DMA0MODE_A {
206 #[doc = "0: Target register is fully read/written during every DMA transaction"]
207 FULL = 0,
208 #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
209 LENLIMIT = 1,
210 #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
211 FULLBYTE = 2,
212 #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
213 LENLIMITBYTE = 3,
214}
215impl From<DMA0MODE_A> for u8 {
216 #[inline(always)]
217 fn from(variant: DMA0MODE_A) -> Self {
218 variant as _
219 }
220}
221#[doc = "Reader of field `DMA0MODE`"]
222pub type DMA0MODE_R = crate::R<u8, DMA0MODE_A>;
223impl DMA0MODE_R {
224 #[doc = r"Get enumerated values variant"]
225 #[inline(always)]
226 pub fn variant(&self) -> DMA0MODE_A {
227 match self.bits {
228 0 => DMA0MODE_A::FULL,
229 1 => DMA0MODE_A::LENLIMIT,
230 2 => DMA0MODE_A::FULLBYTE,
231 3 => DMA0MODE_A::LENLIMITBYTE,
232 _ => unreachable!(),
233 }
234 }
235 #[doc = "Checks if the value of the field is `FULL`"]
236 #[inline(always)]
237 pub fn is_full(&self) -> bool {
238 *self == DMA0MODE_A::FULL
239 }
240 #[doc = "Checks if the value of the field is `LENLIMIT`"]
241 #[inline(always)]
242 pub fn is_lenlimit(&self) -> bool {
243 *self == DMA0MODE_A::LENLIMIT
244 }
245 #[doc = "Checks if the value of the field is `FULLBYTE`"]
246 #[inline(always)]
247 pub fn is_fullbyte(&self) -> bool {
248 *self == DMA0MODE_A::FULLBYTE
249 }
250 #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
251 #[inline(always)]
252 pub fn is_lenlimitbyte(&self) -> bool {
253 *self == DMA0MODE_A::LENLIMITBYTE
254 }
255}
256#[doc = "Write proxy for field `DMA0MODE`"]
257pub struct DMA0MODE_W<'a> {
258 w: &'a mut W,
259}
260impl<'a> DMA0MODE_W<'a> {
261 #[doc = r"Writes `variant` to the field"]
262 #[inline(always)]
263 pub fn variant(self, variant: DMA0MODE_A) -> &'a mut W {
264 {
265 self.bits(variant.into())
266 }
267 }
268 #[doc = "Target register is fully read/written during every DMA transaction"]
269 #[inline(always)]
270 pub fn full(self) -> &'a mut W {
271 self.variant(DMA0MODE_A::FULL)
272 }
273 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Zero padding is automatically added when writing."]
274 #[inline(always)]
275 pub fn lenlimit(self) -> &'a mut W {
276 self.variant(DMA0MODE_A::LENLIMIT)
277 }
278 #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
279 #[inline(always)]
280 pub fn fullbyte(self) -> &'a mut W {
281 self.variant(DMA0MODE_A::FULLBYTE)
282 }
283 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
284 #[inline(always)]
285 pub fn lenlimitbyte(self) -> &'a mut W {
286 self.variant(DMA0MODE_A::LENLIMITBYTE)
287 }
288 #[doc = r"Writes raw bits to the field"]
289 #[inline(always)]
290 pub fn bits(self, value: u8) -> &'a mut W {
291 self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
292 self.w
293 }
294}
295#[doc = "DMA0 Read Register Select\n\nValue on reset: 0"]
296#[derive(Clone, Copy, Debug, PartialEq)]
297#[repr(u8)]
298pub enum DMA0RSEL_A {
299 #[doc = "0: `0`"]
300 DATA0 = 0,
301 #[doc = "1: `1`"]
302 DDATA0 = 1,
303 #[doc = "2: `10`"]
304 DDATA0BIG = 2,
305 #[doc = "3: `11`"]
306 QDATA0 = 3,
307}
308impl From<DMA0RSEL_A> for u8 {
309 #[inline(always)]
310 fn from(variant: DMA0RSEL_A) -> Self {
311 variant as _
312 }
313}
314#[doc = "Reader of field `DMA0RSEL`"]
315pub type DMA0RSEL_R = crate::R<u8, DMA0RSEL_A>;
316impl DMA0RSEL_R {
317 #[doc = r"Get enumerated values variant"]
318 #[inline(always)]
319 pub fn variant(&self) -> DMA0RSEL_A {
320 match self.bits {
321 0 => DMA0RSEL_A::DATA0,
322 1 => DMA0RSEL_A::DDATA0,
323 2 => DMA0RSEL_A::DDATA0BIG,
324 3 => DMA0RSEL_A::QDATA0,
325 _ => unreachable!(),
326 }
327 }
328 #[doc = "Checks if the value of the field is `DATA0`"]
329 #[inline(always)]
330 pub fn is_data0(&self) -> bool {
331 *self == DMA0RSEL_A::DATA0
332 }
333 #[doc = "Checks if the value of the field is `DDATA0`"]
334 #[inline(always)]
335 pub fn is_ddata0(&self) -> bool {
336 *self == DMA0RSEL_A::DDATA0
337 }
338 #[doc = "Checks if the value of the field is `DDATA0BIG`"]
339 #[inline(always)]
340 pub fn is_ddata0big(&self) -> bool {
341 *self == DMA0RSEL_A::DDATA0BIG
342 }
343 #[doc = "Checks if the value of the field is `QDATA0`"]
344 #[inline(always)]
345 pub fn is_qdata0(&self) -> bool {
346 *self == DMA0RSEL_A::QDATA0
347 }
348}
349#[doc = "Write proxy for field `DMA0RSEL`"]
350pub struct DMA0RSEL_W<'a> {
351 w: &'a mut W,
352}
353impl<'a> DMA0RSEL_W<'a> {
354 #[doc = r"Writes `variant` to the field"]
355 #[inline(always)]
356 pub fn variant(self, variant: DMA0RSEL_A) -> &'a mut W {
357 {
358 self.bits(variant.into())
359 }
360 }
361 #[doc = "`0`"]
362 #[inline(always)]
363 pub fn data0(self) -> &'a mut W {
364 self.variant(DMA0RSEL_A::DATA0)
365 }
366 #[doc = "`1`"]
367 #[inline(always)]
368 pub fn ddata0(self) -> &'a mut W {
369 self.variant(DMA0RSEL_A::DDATA0)
370 }
371 #[doc = "`10`"]
372 #[inline(always)]
373 pub fn ddata0big(self) -> &'a mut W {
374 self.variant(DMA0RSEL_A::DDATA0BIG)
375 }
376 #[doc = "`11`"]
377 #[inline(always)]
378 pub fn qdata0(self) -> &'a mut W {
379 self.variant(DMA0RSEL_A::QDATA0)
380 }
381 #[doc = r"Writes raw bits to the field"]
382 #[inline(always)]
383 pub fn bits(self, value: u8) -> &'a mut W {
384 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
385 self.w
386 }
387}
388#[doc = "DMA1 Read Mode\n\nValue on reset: 0"]
389#[derive(Clone, Copy, Debug, PartialEq)]
390#[repr(u8)]
391pub enum DMA1MODE_A {
392 #[doc = "0: Target register is fully read/written during every DMA transaction"]
393 FULL = 0,
394 #[doc = "1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
395 LENLIMIT = 1,
396 #[doc = "2: Target register is fully read/written during every DMA transaction. Bytewise DMA."]
397 FULLBYTE = 2,
398 #[doc = "3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
399 LENLIMITBYTE = 3,
400}
401impl From<DMA1MODE_A> for u8 {
402 #[inline(always)]
403 fn from(variant: DMA1MODE_A) -> Self {
404 variant as _
405 }
406}
407#[doc = "Reader of field `DMA1MODE`"]
408pub type DMA1MODE_R = crate::R<u8, DMA1MODE_A>;
409impl DMA1MODE_R {
410 #[doc = r"Get enumerated values variant"]
411 #[inline(always)]
412 pub fn variant(&self) -> DMA1MODE_A {
413 match self.bits {
414 0 => DMA1MODE_A::FULL,
415 1 => DMA1MODE_A::LENLIMIT,
416 2 => DMA1MODE_A::FULLBYTE,
417 3 => DMA1MODE_A::LENLIMITBYTE,
418 _ => unreachable!(),
419 }
420 }
421 #[doc = "Checks if the value of the field is `FULL`"]
422 #[inline(always)]
423 pub fn is_full(&self) -> bool {
424 *self == DMA1MODE_A::FULL
425 }
426 #[doc = "Checks if the value of the field is `LENLIMIT`"]
427 #[inline(always)]
428 pub fn is_lenlimit(&self) -> bool {
429 *self == DMA1MODE_A::LENLIMIT
430 }
431 #[doc = "Checks if the value of the field is `FULLBYTE`"]
432 #[inline(always)]
433 pub fn is_fullbyte(&self) -> bool {
434 *self == DMA1MODE_A::FULLBYTE
435 }
436 #[doc = "Checks if the value of the field is `LENLIMITBYTE`"]
437 #[inline(always)]
438 pub fn is_lenlimitbyte(&self) -> bool {
439 *self == DMA1MODE_A::LENLIMITBYTE
440 }
441}
442#[doc = "Write proxy for field `DMA1MODE`"]
443pub struct DMA1MODE_W<'a> {
444 w: &'a mut W,
445}
446impl<'a> DMA1MODE_W<'a> {
447 #[doc = r"Writes `variant` to the field"]
448 #[inline(always)]
449 pub fn variant(self, variant: DMA1MODE_A) -> &'a mut W {
450 {
451 self.bits(variant.into())
452 }
453 }
454 #[doc = "Target register is fully read/written during every DMA transaction"]
455 #[inline(always)]
456 pub fn full(self) -> &'a mut W {
457 self.variant(DMA1MODE_A::FULL)
458 }
459 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing."]
460 #[inline(always)]
461 pub fn lenlimit(self) -> &'a mut W {
462 self.variant(DMA1MODE_A::LENLIMIT)
463 }
464 #[doc = "Target register is fully read/written during every DMA transaction. Bytewise DMA."]
465 #[inline(always)]
466 pub fn fullbyte(self) -> &'a mut W {
467 self.variant(DMA1MODE_A::FULLBYTE)
468 }
469 #[doc = "Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing."]
470 #[inline(always)]
471 pub fn lenlimitbyte(self) -> &'a mut W {
472 self.variant(DMA1MODE_A::LENLIMITBYTE)
473 }
474 #[doc = r"Writes raw bits to the field"]
475 #[inline(always)]
476 pub fn bits(self, value: u8) -> &'a mut W {
477 self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
478 self.w
479 }
480}
481#[doc = "DATA0 DMA Unaligned Read Register Select\n\nValue on reset: 0"]
482#[derive(Clone, Copy, Debug, PartialEq)]
483#[repr(u8)]
484pub enum DMA1RSEL_A {
485 #[doc = "0: `0`"]
486 DATA1 = 0,
487 #[doc = "1: `1`"]
488 DDATA1 = 1,
489 #[doc = "2: `10`"]
490 QDATA1 = 2,
491 #[doc = "3: `11`"]
492 QDATA1BIG = 3,
493}
494impl From<DMA1RSEL_A> for u8 {
495 #[inline(always)]
496 fn from(variant: DMA1RSEL_A) -> Self {
497 variant as _
498 }
499}
500#[doc = "Reader of field `DMA1RSEL`"]
501pub type DMA1RSEL_R = crate::R<u8, DMA1RSEL_A>;
502impl DMA1RSEL_R {
503 #[doc = r"Get enumerated values variant"]
504 #[inline(always)]
505 pub fn variant(&self) -> DMA1RSEL_A {
506 match self.bits {
507 0 => DMA1RSEL_A::DATA1,
508 1 => DMA1RSEL_A::DDATA1,
509 2 => DMA1RSEL_A::QDATA1,
510 3 => DMA1RSEL_A::QDATA1BIG,
511 _ => unreachable!(),
512 }
513 }
514 #[doc = "Checks if the value of the field is `DATA1`"]
515 #[inline(always)]
516 pub fn is_data1(&self) -> bool {
517 *self == DMA1RSEL_A::DATA1
518 }
519 #[doc = "Checks if the value of the field is `DDATA1`"]
520 #[inline(always)]
521 pub fn is_ddata1(&self) -> bool {
522 *self == DMA1RSEL_A::DDATA1
523 }
524 #[doc = "Checks if the value of the field is `QDATA1`"]
525 #[inline(always)]
526 pub fn is_qdata1(&self) -> bool {
527 *self == DMA1RSEL_A::QDATA1
528 }
529 #[doc = "Checks if the value of the field is `QDATA1BIG`"]
530 #[inline(always)]
531 pub fn is_qdata1big(&self) -> bool {
532 *self == DMA1RSEL_A::QDATA1BIG
533 }
534}
535#[doc = "Write proxy for field `DMA1RSEL`"]
536pub struct DMA1RSEL_W<'a> {
537 w: &'a mut W,
538}
539impl<'a> DMA1RSEL_W<'a> {
540 #[doc = r"Writes `variant` to the field"]
541 #[inline(always)]
542 pub fn variant(self, variant: DMA1RSEL_A) -> &'a mut W {
543 {
544 self.bits(variant.into())
545 }
546 }
547 #[doc = "`0`"]
548 #[inline(always)]
549 pub fn data1(self) -> &'a mut W {
550 self.variant(DMA1RSEL_A::DATA1)
551 }
552 #[doc = "`1`"]
553 #[inline(always)]
554 pub fn ddata1(self) -> &'a mut W {
555 self.variant(DMA1RSEL_A::DDATA1)
556 }
557 #[doc = "`10`"]
558 #[inline(always)]
559 pub fn qdata1(self) -> &'a mut W {
560 self.variant(DMA1RSEL_A::QDATA1)
561 }
562 #[doc = "`11`"]
563 #[inline(always)]
564 pub fn qdata1big(self) -> &'a mut W {
565 self.variant(DMA1RSEL_A::QDATA1BIG)
566 }
567 #[doc = r"Writes raw bits to the field"]
568 #[inline(always)]
569 pub fn bits(self, value: u8) -> &'a mut W {
570 self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
571 self.w
572 }
573}
574#[doc = "Reader of field `COMBDMA0WEREQ`"]
575pub type COMBDMA0WEREQ_R = crate::R<bool, bool>;
576#[doc = "Write proxy for field `COMBDMA0WEREQ`"]
577pub struct COMBDMA0WEREQ_W<'a> {
578 w: &'a mut W,
579}
580impl<'a> COMBDMA0WEREQ_W<'a> {
581 #[doc = r"Sets the field bit"]
582 #[inline(always)]
583 pub fn set_bit(self) -> &'a mut W {
584 self.bit(true)
585 }
586 #[doc = r"Clears the field bit"]
587 #[inline(always)]
588 pub fn clear_bit(self) -> &'a mut W {
589 self.bit(false)
590 }
591 #[doc = r"Writes raw bits to the field"]
592 #[inline(always)]
593 pub fn bit(self, value: bool) -> &'a mut W {
594 self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
595 self.w
596 }
597}
598impl R {
599 #[doc = "Bit 0 - AES Mode"]
600 #[inline(always)]
601 pub fn aes(&self) -> AES_R {
602 AES_R::new((self.bits & 0x01) != 0)
603 }
604 #[doc = "Bit 1 - Key Buffer Disable"]
605 #[inline(always)]
606 pub fn keybufdis(&self) -> KEYBUFDIS_R {
607 KEYBUFDIS_R::new(((self.bits >> 1) & 0x01) != 0)
608 }
609 #[doc = "Bit 2 - SHA Mode"]
610 #[inline(always)]
611 pub fn sha(&self) -> SHA_R {
612 SHA_R::new(((self.bits >> 2) & 0x01) != 0)
613 }
614 #[doc = "Bit 10 - No Stalling of Bus When Busy"]
615 #[inline(always)]
616 pub fn nobusystall(&self) -> NOBUSYSTALL_R {
617 NOBUSYSTALL_R::new(((self.bits >> 10) & 0x01) != 0)
618 }
619 #[doc = "Bits 14:15 - Increment Width"]
620 #[inline(always)]
621 pub fn incwidth(&self) -> INCWIDTH_R {
622 INCWIDTH_R::new(((self.bits >> 14) & 0x03) as u8)
623 }
624 #[doc = "Bits 16:17 - DMA0 Read Mode"]
625 #[inline(always)]
626 pub fn dma0mode(&self) -> DMA0MODE_R {
627 DMA0MODE_R::new(((self.bits >> 16) & 0x03) as u8)
628 }
629 #[doc = "Bits 20:21 - DMA0 Read Register Select"]
630 #[inline(always)]
631 pub fn dma0rsel(&self) -> DMA0RSEL_R {
632 DMA0RSEL_R::new(((self.bits >> 20) & 0x03) as u8)
633 }
634 #[doc = "Bits 24:25 - DMA1 Read Mode"]
635 #[inline(always)]
636 pub fn dma1mode(&self) -> DMA1MODE_R {
637 DMA1MODE_R::new(((self.bits >> 24) & 0x03) as u8)
638 }
639 #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
640 #[inline(always)]
641 pub fn dma1rsel(&self) -> DMA1RSEL_R {
642 DMA1RSEL_R::new(((self.bits >> 28) & 0x03) as u8)
643 }
644 #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
645 #[inline(always)]
646 pub fn combdma0wereq(&self) -> COMBDMA0WEREQ_R {
647 COMBDMA0WEREQ_R::new(((self.bits >> 31) & 0x01) != 0)
648 }
649}
650impl W {
651 #[doc = "Bit 0 - AES Mode"]
652 #[inline(always)]
653 pub fn aes(&mut self) -> AES_W {
654 AES_W { w: self }
655 }
656 #[doc = "Bit 1 - Key Buffer Disable"]
657 #[inline(always)]
658 pub fn keybufdis(&mut self) -> KEYBUFDIS_W {
659 KEYBUFDIS_W { w: self }
660 }
661 #[doc = "Bit 2 - SHA Mode"]
662 #[inline(always)]
663 pub fn sha(&mut self) -> SHA_W {
664 SHA_W { w: self }
665 }
666 #[doc = "Bit 10 - No Stalling of Bus When Busy"]
667 #[inline(always)]
668 pub fn nobusystall(&mut self) -> NOBUSYSTALL_W {
669 NOBUSYSTALL_W { w: self }
670 }
671 #[doc = "Bits 14:15 - Increment Width"]
672 #[inline(always)]
673 pub fn incwidth(&mut self) -> INCWIDTH_W {
674 INCWIDTH_W { w: self }
675 }
676 #[doc = "Bits 16:17 - DMA0 Read Mode"]
677 #[inline(always)]
678 pub fn dma0mode(&mut self) -> DMA0MODE_W {
679 DMA0MODE_W { w: self }
680 }
681 #[doc = "Bits 20:21 - DMA0 Read Register Select"]
682 #[inline(always)]
683 pub fn dma0rsel(&mut self) -> DMA0RSEL_W {
684 DMA0RSEL_W { w: self }
685 }
686 #[doc = "Bits 24:25 - DMA1 Read Mode"]
687 #[inline(always)]
688 pub fn dma1mode(&mut self) -> DMA1MODE_W {
689 DMA1MODE_W { w: self }
690 }
691 #[doc = "Bits 28:29 - DATA0 DMA Unaligned Read Register Select"]
692 #[inline(always)]
693 pub fn dma1rsel(&mut self) -> DMA1RSEL_W {
694 DMA1RSEL_W { w: self }
695 }
696 #[doc = "Bit 31 - Combined Data0 Write DMA Request"]
697 #[inline(always)]
698 pub fn combdma0wereq(&mut self) -> COMBDMA0WEREQ_W {
699 COMBDMA0WEREQ_W { w: self }
700 }
701}