efm32pg12_pac/msc/
cachecmd.rs

1#[doc = "Writer for register CACHECMD"]
2pub type W = crate::W<u32, super::CACHECMD>;
3#[doc = "Register CACHECMD `reset()`'s with value 0"]
4impl crate::ResetValue for super::CACHECMD {
5    type Type = u32;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `INVCACHE`"]
12pub struct INVCACHE_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> INVCACHE_W<'a> {
16    #[doc = r"Sets the field bit"]
17    #[inline(always)]
18    pub fn set_bit(self) -> &'a mut W {
19        self.bit(true)
20    }
21    #[doc = r"Clears the field bit"]
22    #[inline(always)]
23    pub fn clear_bit(self) -> &'a mut W {
24        self.bit(false)
25    }
26    #[doc = r"Writes raw bits to the field"]
27    #[inline(always)]
28    pub fn bit(self, value: bool) -> &'a mut W {
29        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
30        self.w
31    }
32}
33#[doc = "Write proxy for field `STARTPC`"]
34pub struct STARTPC_W<'a> {
35    w: &'a mut W,
36}
37impl<'a> STARTPC_W<'a> {
38    #[doc = r"Sets the field bit"]
39    #[inline(always)]
40    pub fn set_bit(self) -> &'a mut W {
41        self.bit(true)
42    }
43    #[doc = r"Clears the field bit"]
44    #[inline(always)]
45    pub fn clear_bit(self) -> &'a mut W {
46        self.bit(false)
47    }
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub fn bit(self, value: bool) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
52        self.w
53    }
54}
55#[doc = "Write proxy for field `STOPPC`"]
56pub struct STOPPC_W<'a> {
57    w: &'a mut W,
58}
59impl<'a> STOPPC_W<'a> {
60    #[doc = r"Sets the field bit"]
61    #[inline(always)]
62    pub fn set_bit(self) -> &'a mut W {
63        self.bit(true)
64    }
65    #[doc = r"Clears the field bit"]
66    #[inline(always)]
67    pub fn clear_bit(self) -> &'a mut W {
68        self.bit(false)
69    }
70    #[doc = r"Writes raw bits to the field"]
71    #[inline(always)]
72    pub fn bit(self, value: bool) -> &'a mut W {
73        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
74        self.w
75    }
76}
77impl W {
78    #[doc = "Bit 0 - Invalidate Instruction Cache"]
79    #[inline(always)]
80    pub fn invcache(&mut self) -> INVCACHE_W {
81        INVCACHE_W { w: self }
82    }
83    #[doc = "Bit 1 - Start Performance Counters"]
84    #[inline(always)]
85    pub fn startpc(&mut self) -> STARTPC_W {
86        STARTPC_W { w: self }
87    }
88    #[doc = "Bit 2 - Stop Performance Counters"]
89    #[inline(always)]
90    pub fn stoppc(&mut self) -> STOPPC_W {
91        STOPPC_W { w: self }
92    }
93}
efm32pg12_pac/msc/cachecmd.rs

efm32pg12_pac/msc/
cachecmd.rs
