1#[doc = "Reader of register SCANCTRLX"]
2pub type R = crate::R<u32, super::SCANCTRLX>;
3#[doc = "Writer for register SCANCTRLX"]
4pub type W = crate::W<u32, super::SCANCTRLX>;
5#[doc = "Register SCANCTRLX `reset()`'s with value 0"]
6impl crate::ResetValue for super::SCANCTRLX {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Scan Channel Reference Selection\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum VREFSEL_A {
17 #[doc = "0: Internal 0.83V Bandgap reference"]
18 VBGR = 0,
19 #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
20 VDDXWATT = 1,
21 #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
22 VREFPWATT = 2,
23 #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
24 VREFP = 3,
25 #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
26 VREFPNWATT = 5,
27 #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
28 VREFPN = 6,
29 #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
30 VBGRLOW = 7,
31}
32impl From<VREFSEL_A> for u8 {
33 #[inline(always)]
34 fn from(variant: VREFSEL_A) -> Self {
35 variant as _
36 }
37}
38#[doc = "Reader of field `VREFSEL`"]
39pub type VREFSEL_R = crate::R<u8, VREFSEL_A>;
40impl VREFSEL_R {
41 #[doc = r"Get enumerated values variant"]
42 #[inline(always)]
43 pub fn variant(&self) -> crate::Variant<u8, VREFSEL_A> {
44 use crate::Variant::*;
45 match self.bits {
46 0 => Val(VREFSEL_A::VBGR),
47 1 => Val(VREFSEL_A::VDDXWATT),
48 2 => Val(VREFSEL_A::VREFPWATT),
49 3 => Val(VREFSEL_A::VREFP),
50 5 => Val(VREFSEL_A::VREFPNWATT),
51 6 => Val(VREFSEL_A::VREFPN),
52 7 => Val(VREFSEL_A::VBGRLOW),
53 i => Res(i),
54 }
55 }
56 #[doc = "Checks if the value of the field is `VBGR`"]
57 #[inline(always)]
58 pub fn is_vbgr(&self) -> bool {
59 *self == VREFSEL_A::VBGR
60 }
61 #[doc = "Checks if the value of the field is `VDDXWATT`"]
62 #[inline(always)]
63 pub fn is_vddxwatt(&self) -> bool {
64 *self == VREFSEL_A::VDDXWATT
65 }
66 #[doc = "Checks if the value of the field is `VREFPWATT`"]
67 #[inline(always)]
68 pub fn is_vrefpwatt(&self) -> bool {
69 *self == VREFSEL_A::VREFPWATT
70 }
71 #[doc = "Checks if the value of the field is `VREFP`"]
72 #[inline(always)]
73 pub fn is_vrefp(&self) -> bool {
74 *self == VREFSEL_A::VREFP
75 }
76 #[doc = "Checks if the value of the field is `VREFPNWATT`"]
77 #[inline(always)]
78 pub fn is_vrefpnwatt(&self) -> bool {
79 *self == VREFSEL_A::VREFPNWATT
80 }
81 #[doc = "Checks if the value of the field is `VREFPN`"]
82 #[inline(always)]
83 pub fn is_vrefpn(&self) -> bool {
84 *self == VREFSEL_A::VREFPN
85 }
86 #[doc = "Checks if the value of the field is `VBGRLOW`"]
87 #[inline(always)]
88 pub fn is_vbgrlow(&self) -> bool {
89 *self == VREFSEL_A::VBGRLOW
90 }
91}
92#[doc = "Write proxy for field `VREFSEL`"]
93pub struct VREFSEL_W<'a> {
94 w: &'a mut W,
95}
96impl<'a> VREFSEL_W<'a> {
97 #[doc = r"Writes `variant` to the field"]
98 #[inline(always)]
99 pub fn variant(self, variant: VREFSEL_A) -> &'a mut W {
100 unsafe { self.bits(variant.into()) }
101 }
102 #[doc = "Internal 0.83V Bandgap reference"]
103 #[inline(always)]
104 pub fn vbgr(self) -> &'a mut W {
105 self.variant(VREFSEL_A::VBGR)
106 }
107 #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
108 #[inline(always)]
109 pub fn vddxwatt(self) -> &'a mut W {
110 self.variant(VREFSEL_A::VDDXWATT)
111 }
112 #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
113 #[inline(always)]
114 pub fn vrefpwatt(self) -> &'a mut W {
115 self.variant(VREFSEL_A::VREFPWATT)
116 }
117 #[doc = "Raw single ended external Vref: ADCn_EXTP"]
118 #[inline(always)]
119 pub fn vrefp(self) -> &'a mut W {
120 self.variant(VREFSEL_A::VREFP)
121 }
122 #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
123 #[inline(always)]
124 pub fn vrefpnwatt(self) -> &'a mut W {
125 self.variant(VREFSEL_A::VREFPNWATT)
126 }
127 #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
128 #[inline(always)]
129 pub fn vrefpn(self) -> &'a mut W {
130 self.variant(VREFSEL_A::VREFPN)
131 }
132 #[doc = "Internal Bandgap reference at low setting 0.78V"]
133 #[inline(always)]
134 pub fn vbgrlow(self) -> &'a mut W {
135 self.variant(VREFSEL_A::VBGRLOW)
136 }
137 #[doc = r"Writes raw bits to the field"]
138 #[inline(always)]
139 pub unsafe fn bits(self, value: u8) -> &'a mut W {
140 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
141 self.w
142 }
143}
144#[doc = "Reader of field `VREFATTFIX`"]
145pub type VREFATTFIX_R = crate::R<bool, bool>;
146#[doc = "Write proxy for field `VREFATTFIX`"]
147pub struct VREFATTFIX_W<'a> {
148 w: &'a mut W,
149}
150impl<'a> VREFATTFIX_W<'a> {
151 #[doc = r"Sets the field bit"]
152 #[inline(always)]
153 pub fn set_bit(self) -> &'a mut W {
154 self.bit(true)
155 }
156 #[doc = r"Clears the field bit"]
157 #[inline(always)]
158 pub fn clear_bit(self) -> &'a mut W {
159 self.bit(false)
160 }
161 #[doc = r"Writes raw bits to the field"]
162 #[inline(always)]
163 pub fn bit(self, value: bool) -> &'a mut W {
164 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
165 self.w
166 }
167}
168#[doc = "Reader of field `VREFATT`"]
169pub type VREFATT_R = crate::R<u8, u8>;
170#[doc = "Write proxy for field `VREFATT`"]
171pub struct VREFATT_W<'a> {
172 w: &'a mut W,
173}
174impl<'a> VREFATT_W<'a> {
175 #[doc = r"Writes raw bits to the field"]
176 #[inline(always)]
177 pub unsafe fn bits(self, value: u8) -> &'a mut W {
178 self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
179 self.w
180 }
181}
182#[doc = "Reader of field `VINATT`"]
183pub type VINATT_R = crate::R<u8, u8>;
184#[doc = "Write proxy for field `VINATT`"]
185pub struct VINATT_W<'a> {
186 w: &'a mut W,
187}
188impl<'a> VINATT_W<'a> {
189 #[doc = r"Writes raw bits to the field"]
190 #[inline(always)]
191 pub unsafe fn bits(self, value: u8) -> &'a mut W {
192 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
193 self.w
194 }
195}
196#[doc = "Reader of field `DVL`"]
197pub type DVL_R = crate::R<u8, u8>;
198#[doc = "Write proxy for field `DVL`"]
199pub struct DVL_W<'a> {
200 w: &'a mut W,
201}
202impl<'a> DVL_W<'a> {
203 #[doc = r"Writes raw bits to the field"]
204 #[inline(always)]
205 pub unsafe fn bits(self, value: u8) -> &'a mut W {
206 self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
207 self.w
208 }
209}
210#[doc = "Reader of field `FIFOOFACT`"]
211pub type FIFOOFACT_R = crate::R<bool, bool>;
212#[doc = "Write proxy for field `FIFOOFACT`"]
213pub struct FIFOOFACT_W<'a> {
214 w: &'a mut W,
215}
216impl<'a> FIFOOFACT_W<'a> {
217 #[doc = r"Sets the field bit"]
218 #[inline(always)]
219 pub fn set_bit(self) -> &'a mut W {
220 self.bit(true)
221 }
222 #[doc = r"Clears the field bit"]
223 #[inline(always)]
224 pub fn clear_bit(self) -> &'a mut W {
225 self.bit(false)
226 }
227 #[doc = r"Writes raw bits to the field"]
228 #[inline(always)]
229 pub fn bit(self, value: bool) -> &'a mut W {
230 self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
231 self.w
232 }
233}
234#[doc = "Reader of field `PRSMODE`"]
235pub type PRSMODE_R = crate::R<bool, bool>;
236#[doc = "Write proxy for field `PRSMODE`"]
237pub struct PRSMODE_W<'a> {
238 w: &'a mut W,
239}
240impl<'a> PRSMODE_W<'a> {
241 #[doc = r"Sets the field bit"]
242 #[inline(always)]
243 pub fn set_bit(self) -> &'a mut W {
244 self.bit(true)
245 }
246 #[doc = r"Clears the field bit"]
247 #[inline(always)]
248 pub fn clear_bit(self) -> &'a mut W {
249 self.bit(false)
250 }
251 #[doc = r"Writes raw bits to the field"]
252 #[inline(always)]
253 pub fn bit(self, value: bool) -> &'a mut W {
254 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
255 self.w
256 }
257}
258#[doc = "Scan Sequence PRS Trigger Select\n\nValue on reset: 0"]
259#[derive(Clone, Copy, Debug, PartialEq)]
260#[repr(u8)]
261pub enum PRSSEL_A {
262 #[doc = "0: PRS ch 0 triggers scan sequence"]
263 PRSCH0 = 0,
264 #[doc = "1: PRS ch 1 triggers scan sequence"]
265 PRSCH1 = 1,
266 #[doc = "2: PRS ch 2 triggers scan sequence"]
267 PRSCH2 = 2,
268 #[doc = "3: PRS ch 3 triggers scan sequence"]
269 PRSCH3 = 3,
270 #[doc = "4: PRS ch 4 triggers scan sequence"]
271 PRSCH4 = 4,
272 #[doc = "5: PRS ch 5 triggers scan sequence"]
273 PRSCH5 = 5,
274 #[doc = "6: PRS ch 6 triggers scan sequence"]
275 PRSCH6 = 6,
276 #[doc = "7: PRS ch 7 triggers scan sequence"]
277 PRSCH7 = 7,
278 #[doc = "8: PRS ch 8 triggers scan sequence"]
279 PRSCH8 = 8,
280 #[doc = "9: PRS ch 9 triggers scan sequence"]
281 PRSCH9 = 9,
282 #[doc = "10: PRS ch 10 triggers scan sequence"]
283 PRSCH10 = 10,
284 #[doc = "11: PRS ch 11 triggers scan sequence"]
285 PRSCH11 = 11,
286}
287impl From<PRSSEL_A> for u8 {
288 #[inline(always)]
289 fn from(variant: PRSSEL_A) -> Self {
290 variant as _
291 }
292}
293#[doc = "Reader of field `PRSSEL`"]
294pub type PRSSEL_R = crate::R<u8, PRSSEL_A>;
295impl PRSSEL_R {
296 #[doc = r"Get enumerated values variant"]
297 #[inline(always)]
298 pub fn variant(&self) -> crate::Variant<u8, PRSSEL_A> {
299 use crate::Variant::*;
300 match self.bits {
301 0 => Val(PRSSEL_A::PRSCH0),
302 1 => Val(PRSSEL_A::PRSCH1),
303 2 => Val(PRSSEL_A::PRSCH2),
304 3 => Val(PRSSEL_A::PRSCH3),
305 4 => Val(PRSSEL_A::PRSCH4),
306 5 => Val(PRSSEL_A::PRSCH5),
307 6 => Val(PRSSEL_A::PRSCH6),
308 7 => Val(PRSSEL_A::PRSCH7),
309 8 => Val(PRSSEL_A::PRSCH8),
310 9 => Val(PRSSEL_A::PRSCH9),
311 10 => Val(PRSSEL_A::PRSCH10),
312 11 => Val(PRSSEL_A::PRSCH11),
313 i => Res(i),
314 }
315 }
316 #[doc = "Checks if the value of the field is `PRSCH0`"]
317 #[inline(always)]
318 pub fn is_prsch0(&self) -> bool {
319 *self == PRSSEL_A::PRSCH0
320 }
321 #[doc = "Checks if the value of the field is `PRSCH1`"]
322 #[inline(always)]
323 pub fn is_prsch1(&self) -> bool {
324 *self == PRSSEL_A::PRSCH1
325 }
326 #[doc = "Checks if the value of the field is `PRSCH2`"]
327 #[inline(always)]
328 pub fn is_prsch2(&self) -> bool {
329 *self == PRSSEL_A::PRSCH2
330 }
331 #[doc = "Checks if the value of the field is `PRSCH3`"]
332 #[inline(always)]
333 pub fn is_prsch3(&self) -> bool {
334 *self == PRSSEL_A::PRSCH3
335 }
336 #[doc = "Checks if the value of the field is `PRSCH4`"]
337 #[inline(always)]
338 pub fn is_prsch4(&self) -> bool {
339 *self == PRSSEL_A::PRSCH4
340 }
341 #[doc = "Checks if the value of the field is `PRSCH5`"]
342 #[inline(always)]
343 pub fn is_prsch5(&self) -> bool {
344 *self == PRSSEL_A::PRSCH5
345 }
346 #[doc = "Checks if the value of the field is `PRSCH6`"]
347 #[inline(always)]
348 pub fn is_prsch6(&self) -> bool {
349 *self == PRSSEL_A::PRSCH6
350 }
351 #[doc = "Checks if the value of the field is `PRSCH7`"]
352 #[inline(always)]
353 pub fn is_prsch7(&self) -> bool {
354 *self == PRSSEL_A::PRSCH7
355 }
356 #[doc = "Checks if the value of the field is `PRSCH8`"]
357 #[inline(always)]
358 pub fn is_prsch8(&self) -> bool {
359 *self == PRSSEL_A::PRSCH8
360 }
361 #[doc = "Checks if the value of the field is `PRSCH9`"]
362 #[inline(always)]
363 pub fn is_prsch9(&self) -> bool {
364 *self == PRSSEL_A::PRSCH9
365 }
366 #[doc = "Checks if the value of the field is `PRSCH10`"]
367 #[inline(always)]
368 pub fn is_prsch10(&self) -> bool {
369 *self == PRSSEL_A::PRSCH10
370 }
371 #[doc = "Checks if the value of the field is `PRSCH11`"]
372 #[inline(always)]
373 pub fn is_prsch11(&self) -> bool {
374 *self == PRSSEL_A::PRSCH11
375 }
376}
377#[doc = "Write proxy for field `PRSSEL`"]
378pub struct PRSSEL_W<'a> {
379 w: &'a mut W,
380}
381impl<'a> PRSSEL_W<'a> {
382 #[doc = r"Writes `variant` to the field"]
383 #[inline(always)]
384 pub fn variant(self, variant: PRSSEL_A) -> &'a mut W {
385 unsafe { self.bits(variant.into()) }
386 }
387 #[doc = "PRS ch 0 triggers scan sequence"]
388 #[inline(always)]
389 pub fn prsch0(self) -> &'a mut W {
390 self.variant(PRSSEL_A::PRSCH0)
391 }
392 #[doc = "PRS ch 1 triggers scan sequence"]
393 #[inline(always)]
394 pub fn prsch1(self) -> &'a mut W {
395 self.variant(PRSSEL_A::PRSCH1)
396 }
397 #[doc = "PRS ch 2 triggers scan sequence"]
398 #[inline(always)]
399 pub fn prsch2(self) -> &'a mut W {
400 self.variant(PRSSEL_A::PRSCH2)
401 }
402 #[doc = "PRS ch 3 triggers scan sequence"]
403 #[inline(always)]
404 pub fn prsch3(self) -> &'a mut W {
405 self.variant(PRSSEL_A::PRSCH3)
406 }
407 #[doc = "PRS ch 4 triggers scan sequence"]
408 #[inline(always)]
409 pub fn prsch4(self) -> &'a mut W {
410 self.variant(PRSSEL_A::PRSCH4)
411 }
412 #[doc = "PRS ch 5 triggers scan sequence"]
413 #[inline(always)]
414 pub fn prsch5(self) -> &'a mut W {
415 self.variant(PRSSEL_A::PRSCH5)
416 }
417 #[doc = "PRS ch 6 triggers scan sequence"]
418 #[inline(always)]
419 pub fn prsch6(self) -> &'a mut W {
420 self.variant(PRSSEL_A::PRSCH6)
421 }
422 #[doc = "PRS ch 7 triggers scan sequence"]
423 #[inline(always)]
424 pub fn prsch7(self) -> &'a mut W {
425 self.variant(PRSSEL_A::PRSCH7)
426 }
427 #[doc = "PRS ch 8 triggers scan sequence"]
428 #[inline(always)]
429 pub fn prsch8(self) -> &'a mut W {
430 self.variant(PRSSEL_A::PRSCH8)
431 }
432 #[doc = "PRS ch 9 triggers scan sequence"]
433 #[inline(always)]
434 pub fn prsch9(self) -> &'a mut W {
435 self.variant(PRSSEL_A::PRSCH9)
436 }
437 #[doc = "PRS ch 10 triggers scan sequence"]
438 #[inline(always)]
439 pub fn prsch10(self) -> &'a mut W {
440 self.variant(PRSSEL_A::PRSCH10)
441 }
442 #[doc = "PRS ch 11 triggers scan sequence"]
443 #[inline(always)]
444 pub fn prsch11(self) -> &'a mut W {
445 self.variant(PRSSEL_A::PRSCH11)
446 }
447 #[doc = r"Writes raw bits to the field"]
448 #[inline(always)]
449 pub unsafe fn bits(self, value: u8) -> &'a mut W {
450 self.w.bits = (self.w.bits & !(0x0f << 17)) | (((value as u32) & 0x0f) << 17);
451 self.w
452 }
453}
454#[doc = "Reader of field `CONVSTARTDELAY`"]
455pub type CONVSTARTDELAY_R = crate::R<u8, u8>;
456#[doc = "Write proxy for field `CONVSTARTDELAY`"]
457pub struct CONVSTARTDELAY_W<'a> {
458 w: &'a mut W,
459}
460impl<'a> CONVSTARTDELAY_W<'a> {
461 #[doc = r"Writes raw bits to the field"]
462 #[inline(always)]
463 pub unsafe fn bits(self, value: u8) -> &'a mut W {
464 self.w.bits = (self.w.bits & !(0x1f << 22)) | (((value as u32) & 0x1f) << 22);
465 self.w
466 }
467}
468#[doc = "Reader of field `CONVSTARTDELAYEN`"]
469pub type CONVSTARTDELAYEN_R = crate::R<bool, bool>;
470#[doc = "Write proxy for field `CONVSTARTDELAYEN`"]
471pub struct CONVSTARTDELAYEN_W<'a> {
472 w: &'a mut W,
473}
474impl<'a> CONVSTARTDELAYEN_W<'a> {
475 #[doc = r"Sets the field bit"]
476 #[inline(always)]
477 pub fn set_bit(self) -> &'a mut W {
478 self.bit(true)
479 }
480 #[doc = r"Clears the field bit"]
481 #[inline(always)]
482 pub fn clear_bit(self) -> &'a mut W {
483 self.bit(false)
484 }
485 #[doc = r"Writes raw bits to the field"]
486 #[inline(always)]
487 pub fn bit(self, value: bool) -> &'a mut W {
488 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
489 self.w
490 }
491}
492#[doc = "REPDELAY Select for SCAN REP Mode\n\nValue on reset: 0"]
493#[derive(Clone, Copy, Debug, PartialEq)]
494#[repr(u8)]
495pub enum REPDELAY_A {
496 #[doc = "0: No delay"]
497 NODELAY = 0,
498 #[doc = "1: 4 conversion clock cycles"]
499 _4CYCLES = 1,
500 #[doc = "2: 8 conversion clock cycles"]
501 _8CYCLES = 2,
502 #[doc = "3: 16 conversion clock cycles"]
503 _16CYCLES = 3,
504 #[doc = "4: 32 conversion clock cycles"]
505 _32CYCLES = 4,
506 #[doc = "5: 64 conversion clock cycles"]
507 _64CYCLES = 5,
508 #[doc = "6: 128 conversion clock cycles"]
509 _128CYCLES = 6,
510 #[doc = "7: 256 conversion clock cycles"]
511 _256CYCLES = 7,
512}
513impl From<REPDELAY_A> for u8 {
514 #[inline(always)]
515 fn from(variant: REPDELAY_A) -> Self {
516 variant as _
517 }
518}
519#[doc = "Reader of field `REPDELAY`"]
520pub type REPDELAY_R = crate::R<u8, REPDELAY_A>;
521impl REPDELAY_R {
522 #[doc = r"Get enumerated values variant"]
523 #[inline(always)]
524 pub fn variant(&self) -> REPDELAY_A {
525 match self.bits {
526 0 => REPDELAY_A::NODELAY,
527 1 => REPDELAY_A::_4CYCLES,
528 2 => REPDELAY_A::_8CYCLES,
529 3 => REPDELAY_A::_16CYCLES,
530 4 => REPDELAY_A::_32CYCLES,
531 5 => REPDELAY_A::_64CYCLES,
532 6 => REPDELAY_A::_128CYCLES,
533 7 => REPDELAY_A::_256CYCLES,
534 _ => unreachable!(),
535 }
536 }
537 #[doc = "Checks if the value of the field is `NODELAY`"]
538 #[inline(always)]
539 pub fn is_nodelay(&self) -> bool {
540 *self == REPDELAY_A::NODELAY
541 }
542 #[doc = "Checks if the value of the field is `_4CYCLES`"]
543 #[inline(always)]
544 pub fn is_4cycles(&self) -> bool {
545 *self == REPDELAY_A::_4CYCLES
546 }
547 #[doc = "Checks if the value of the field is `_8CYCLES`"]
548 #[inline(always)]
549 pub fn is_8cycles(&self) -> bool {
550 *self == REPDELAY_A::_8CYCLES
551 }
552 #[doc = "Checks if the value of the field is `_16CYCLES`"]
553 #[inline(always)]
554 pub fn is_16cycles(&self) -> bool {
555 *self == REPDELAY_A::_16CYCLES
556 }
557 #[doc = "Checks if the value of the field is `_32CYCLES`"]
558 #[inline(always)]
559 pub fn is_32cycles(&self) -> bool {
560 *self == REPDELAY_A::_32CYCLES
561 }
562 #[doc = "Checks if the value of the field is `_64CYCLES`"]
563 #[inline(always)]
564 pub fn is_64cycles(&self) -> bool {
565 *self == REPDELAY_A::_64CYCLES
566 }
567 #[doc = "Checks if the value of the field is `_128CYCLES`"]
568 #[inline(always)]
569 pub fn is_128cycles(&self) -> bool {
570 *self == REPDELAY_A::_128CYCLES
571 }
572 #[doc = "Checks if the value of the field is `_256CYCLES`"]
573 #[inline(always)]
574 pub fn is_256cycles(&self) -> bool {
575 *self == REPDELAY_A::_256CYCLES
576 }
577}
578#[doc = "Write proxy for field `REPDELAY`"]
579pub struct REPDELAY_W<'a> {
580 w: &'a mut W,
581}
582impl<'a> REPDELAY_W<'a> {
583 #[doc = r"Writes `variant` to the field"]
584 #[inline(always)]
585 pub fn variant(self, variant: REPDELAY_A) -> &'a mut W {
586 {
587 self.bits(variant.into())
588 }
589 }
590 #[doc = "No delay"]
591 #[inline(always)]
592 pub fn nodelay(self) -> &'a mut W {
593 self.variant(REPDELAY_A::NODELAY)
594 }
595 #[doc = "4 conversion clock cycles"]
596 #[inline(always)]
597 pub fn _4cycles(self) -> &'a mut W {
598 self.variant(REPDELAY_A::_4CYCLES)
599 }
600 #[doc = "8 conversion clock cycles"]
601 #[inline(always)]
602 pub fn _8cycles(self) -> &'a mut W {
603 self.variant(REPDELAY_A::_8CYCLES)
604 }
605 #[doc = "16 conversion clock cycles"]
606 #[inline(always)]
607 pub fn _16cycles(self) -> &'a mut W {
608 self.variant(REPDELAY_A::_16CYCLES)
609 }
610 #[doc = "32 conversion clock cycles"]
611 #[inline(always)]
612 pub fn _32cycles(self) -> &'a mut W {
613 self.variant(REPDELAY_A::_32CYCLES)
614 }
615 #[doc = "64 conversion clock cycles"]
616 #[inline(always)]
617 pub fn _64cycles(self) -> &'a mut W {
618 self.variant(REPDELAY_A::_64CYCLES)
619 }
620 #[doc = "128 conversion clock cycles"]
621 #[inline(always)]
622 pub fn _128cycles(self) -> &'a mut W {
623 self.variant(REPDELAY_A::_128CYCLES)
624 }
625 #[doc = "256 conversion clock cycles"]
626 #[inline(always)]
627 pub fn _256cycles(self) -> &'a mut W {
628 self.variant(REPDELAY_A::_256CYCLES)
629 }
630 #[doc = r"Writes raw bits to the field"]
631 #[inline(always)]
632 pub fn bits(self, value: u8) -> &'a mut W {
633 self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
634 self.w
635 }
636}
637impl R {
638 #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
639 #[inline(always)]
640 pub fn vrefsel(&self) -> VREFSEL_R {
641 VREFSEL_R::new((self.bits & 0x07) as u8)
642 }
643 #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
644 #[inline(always)]
645 pub fn vrefattfix(&self) -> VREFATTFIX_R {
646 VREFATTFIX_R::new(((self.bits >> 3) & 0x01) != 0)
647 }
648 #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
649 #[inline(always)]
650 pub fn vrefatt(&self) -> VREFATT_R {
651 VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
652 }
653 #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
654 #[inline(always)]
655 pub fn vinatt(&self) -> VINATT_R {
656 VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
657 }
658 #[doc = "Bits 12:13 - Scan DV Level Select"]
659 #[inline(always)]
660 pub fn dvl(&self) -> DVL_R {
661 DVL_R::new(((self.bits >> 12) & 0x03) as u8)
662 }
663 #[doc = "Bit 14 - Scan FIFO Overflow Action"]
664 #[inline(always)]
665 pub fn fifoofact(&self) -> FIFOOFACT_R {
666 FIFOOFACT_R::new(((self.bits >> 14) & 0x01) != 0)
667 }
668 #[doc = "Bit 16 - Scan PRS Trigger Mode"]
669 #[inline(always)]
670 pub fn prsmode(&self) -> PRSMODE_R {
671 PRSMODE_R::new(((self.bits >> 16) & 0x01) != 0)
672 }
673 #[doc = "Bits 17:20 - Scan Sequence PRS Trigger Select"]
674 #[inline(always)]
675 pub fn prssel(&self) -> PRSSEL_R {
676 PRSSEL_R::new(((self.bits >> 17) & 0x0f) as u8)
677 }
678 #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
679 #[inline(always)]
680 pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
681 CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
682 }
683 #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
684 #[inline(always)]
685 pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
686 CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 0x01) != 0)
687 }
688 #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
689 #[inline(always)]
690 pub fn repdelay(&self) -> REPDELAY_R {
691 REPDELAY_R::new(((self.bits >> 29) & 0x07) as u8)
692 }
693}
694impl W {
695 #[doc = "Bits 0:2 - Scan Channel Reference Selection"]
696 #[inline(always)]
697 pub fn vrefsel(&mut self) -> VREFSEL_W {
698 VREFSEL_W { w: self }
699 }
700 #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
701 #[inline(always)]
702 pub fn vrefattfix(&mut self) -> VREFATTFIX_W {
703 VREFATTFIX_W { w: self }
704 }
705 #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
706 #[inline(always)]
707 pub fn vrefatt(&mut self) -> VREFATT_W {
708 VREFATT_W { w: self }
709 }
710 #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
711 #[inline(always)]
712 pub fn vinatt(&mut self) -> VINATT_W {
713 VINATT_W { w: self }
714 }
715 #[doc = "Bits 12:13 - Scan DV Level Select"]
716 #[inline(always)]
717 pub fn dvl(&mut self) -> DVL_W {
718 DVL_W { w: self }
719 }
720 #[doc = "Bit 14 - Scan FIFO Overflow Action"]
721 #[inline(always)]
722 pub fn fifoofact(&mut self) -> FIFOOFACT_W {
723 FIFOOFACT_W { w: self }
724 }
725 #[doc = "Bit 16 - Scan PRS Trigger Mode"]
726 #[inline(always)]
727 pub fn prsmode(&mut self) -> PRSMODE_W {
728 PRSMODE_W { w: self }
729 }
730 #[doc = "Bits 17:20 - Scan Sequence PRS Trigger Select"]
731 #[inline(always)]
732 pub fn prssel(&mut self) -> PRSSEL_W {
733 PRSSEL_W { w: self }
734 }
735 #[doc = "Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set"]
736 #[inline(always)]
737 pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W {
738 CONVSTARTDELAY_W { w: self }
739 }
740 #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
741 #[inline(always)]
742 pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W {
743 CONVSTARTDELAYEN_W { w: self }
744 }
745 #[doc = "Bits 29:31 - REPDELAY Select for SCAN REP Mode"]
746 #[inline(always)]
747 pub fn repdelay(&mut self) -> REPDELAY_W {
748 REPDELAY_W { w: self }
749 }
750}