efm32pg12_pac/leuart0/
clkdiv.rs

1#[doc = "Reader of register CLKDIV"]
2pub type R = crate::R<u32, super::CLKDIV>;
3#[doc = "Writer for register CLKDIV"]
4pub type W = crate::W<u32, super::CLKDIV>;
5#[doc = "Register CLKDIV `reset()`'s with value 0"]
6impl crate::ResetValue for super::CLKDIV {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIV`"]
14pub type DIV_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `DIV`"]
16pub struct DIV_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DIV_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x3fff << 3)) | (((value as u32) & 0x3fff) << 3);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 3:16 - Fractional Clock Divider"]
29    #[inline(always)]
30    pub fn div(&self) -> DIV_R {
31        DIV_R::new(((self.bits >> 3) & 0x3fff) as u16)
32    }
33}
34impl W {
35    #[doc = "Bits 3:16 - Fractional Clock Divider"]
36    #[inline(always)]
37    pub fn div(&mut self) -> DIV_W {
38        DIV_W { w: self }
39    }
40}
efm32pg12_pac/leuart0/clkdiv.rs

efm32pg12_pac/leuart0/
clkdiv.rs
