efm32pg12_pac/csen/
timctrl.rs

1#[doc = "Reader of register TIMCTRL"]
2pub type R = crate::R<u32, super::TIMCTRL>;
3#[doc = "Writer for register TIMCTRL"]
4pub type W = crate::W<u32, super::TIMCTRL>;
5#[doc = "Register TIMCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::TIMCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Period Counter Prescaler\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum PCPRESC_A {
17    #[doc = "0: The period counter clock frequency is LFBCLKCSEN/1"]
18    DIV1 = 0,
19    #[doc = "1: The period counter clock frequency is LFBCLKCSEN/2"]
20    DIV2 = 1,
21    #[doc = "2: The period counter clock frequency is LFBCLKCSEN/4"]
22    DIV4 = 2,
23    #[doc = "3: The period counter clock frequency is LFBCLKCSEN/8"]
24    DIV8 = 3,
25    #[doc = "4: The period counter clock frequency is LFBCLKCSEN/16"]
26    DIV16 = 4,
27    #[doc = "5: The period counter clock frequency is LFBCLKCSEN/32"]
28    DIV32 = 5,
29    #[doc = "6: The period counter clock frequency is LFBCLKCSEN/64"]
30    DIV64 = 6,
31    #[doc = "7: The period counter clock frequency is LFBCLKCSEN/128"]
32    DIV128 = 7,
33}
34impl From<PCPRESC_A> for u8 {
35    #[inline(always)]
36    fn from(variant: PCPRESC_A) -> Self {
37        variant as _
38    }
39}
40#[doc = "Reader of field `PCPRESC`"]
41pub type PCPRESC_R = crate::R<u8, PCPRESC_A>;
42impl PCPRESC_R {
43    #[doc = r"Get enumerated values variant"]
44    #[inline(always)]
45    pub fn variant(&self) -> PCPRESC_A {
46        match self.bits {
47            0 => PCPRESC_A::DIV1,
48            1 => PCPRESC_A::DIV2,
49            2 => PCPRESC_A::DIV4,
50            3 => PCPRESC_A::DIV8,
51            4 => PCPRESC_A::DIV16,
52            5 => PCPRESC_A::DIV32,
53            6 => PCPRESC_A::DIV64,
54            7 => PCPRESC_A::DIV128,
55            _ => unreachable!(),
56        }
57    }
58    #[doc = "Checks if the value of the field is `DIV1`"]
59    #[inline(always)]
60    pub fn is_div1(&self) -> bool {
61        *self == PCPRESC_A::DIV1
62    }
63    #[doc = "Checks if the value of the field is `DIV2`"]
64    #[inline(always)]
65    pub fn is_div2(&self) -> bool {
66        *self == PCPRESC_A::DIV2
67    }
68    #[doc = "Checks if the value of the field is `DIV4`"]
69    #[inline(always)]
70    pub fn is_div4(&self) -> bool {
71        *self == PCPRESC_A::DIV4
72    }
73    #[doc = "Checks if the value of the field is `DIV8`"]
74    #[inline(always)]
75    pub fn is_div8(&self) -> bool {
76        *self == PCPRESC_A::DIV8
77    }
78    #[doc = "Checks if the value of the field is `DIV16`"]
79    #[inline(always)]
80    pub fn is_div16(&self) -> bool {
81        *self == PCPRESC_A::DIV16
82    }
83    #[doc = "Checks if the value of the field is `DIV32`"]
84    #[inline(always)]
85    pub fn is_div32(&self) -> bool {
86        *self == PCPRESC_A::DIV32
87    }
88    #[doc = "Checks if the value of the field is `DIV64`"]
89    #[inline(always)]
90    pub fn is_div64(&self) -> bool {
91        *self == PCPRESC_A::DIV64
92    }
93    #[doc = "Checks if the value of the field is `DIV128`"]
94    #[inline(always)]
95    pub fn is_div128(&self) -> bool {
96        *self == PCPRESC_A::DIV128
97    }
98}
99#[doc = "Write proxy for field `PCPRESC`"]
100pub struct PCPRESC_W<'a> {
101    w: &'a mut W,
102}
103impl<'a> PCPRESC_W<'a> {
104    #[doc = r"Writes `variant` to the field"]
105    #[inline(always)]
106    pub fn variant(self, variant: PCPRESC_A) -> &'a mut W {
107        {
108            self.bits(variant.into())
109        }
110    }
111    #[doc = "The period counter clock frequency is LFBCLKCSEN/1"]
112    #[inline(always)]
113    pub fn div1(self) -> &'a mut W {
114        self.variant(PCPRESC_A::DIV1)
115    }
116    #[doc = "The period counter clock frequency is LFBCLKCSEN/2"]
117    #[inline(always)]
118    pub fn div2(self) -> &'a mut W {
119        self.variant(PCPRESC_A::DIV2)
120    }
121    #[doc = "The period counter clock frequency is LFBCLKCSEN/4"]
122    #[inline(always)]
123    pub fn div4(self) -> &'a mut W {
124        self.variant(PCPRESC_A::DIV4)
125    }
126    #[doc = "The period counter clock frequency is LFBCLKCSEN/8"]
127    #[inline(always)]
128    pub fn div8(self) -> &'a mut W {
129        self.variant(PCPRESC_A::DIV8)
130    }
131    #[doc = "The period counter clock frequency is LFBCLKCSEN/16"]
132    #[inline(always)]
133    pub fn div16(self) -> &'a mut W {
134        self.variant(PCPRESC_A::DIV16)
135    }
136    #[doc = "The period counter clock frequency is LFBCLKCSEN/32"]
137    #[inline(always)]
138    pub fn div32(self) -> &'a mut W {
139        self.variant(PCPRESC_A::DIV32)
140    }
141    #[doc = "The period counter clock frequency is LFBCLKCSEN/64"]
142    #[inline(always)]
143    pub fn div64(self) -> &'a mut W {
144        self.variant(PCPRESC_A::DIV64)
145    }
146    #[doc = "The period counter clock frequency is LFBCLKCSEN/128"]
147    #[inline(always)]
148    pub fn div128(self) -> &'a mut W {
149        self.variant(PCPRESC_A::DIV128)
150    }
151    #[doc = r"Writes raw bits to the field"]
152    #[inline(always)]
153    pub fn bits(self, value: u8) -> &'a mut W {
154        self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
155        self.w
156    }
157}
158#[doc = "Reader of field `PCTOP`"]
159pub type PCTOP_R = crate::R<u8, u8>;
160#[doc = "Write proxy for field `PCTOP`"]
161pub struct PCTOP_W<'a> {
162    w: &'a mut W,
163}
164impl<'a> PCTOP_W<'a> {
165    #[doc = r"Writes raw bits to the field"]
166    #[inline(always)]
167    pub unsafe fn bits(self, value: u8) -> &'a mut W {
168        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
169        self.w
170    }
171}
172#[doc = "Reader of field `WARMUPCNT`"]
173pub type WARMUPCNT_R = crate::R<u8, u8>;
174#[doc = "Write proxy for field `WARMUPCNT`"]
175pub struct WARMUPCNT_W<'a> {
176    w: &'a mut W,
177}
178impl<'a> WARMUPCNT_W<'a> {
179    #[doc = r"Writes raw bits to the field"]
180    #[inline(always)]
181    pub unsafe fn bits(self, value: u8) -> &'a mut W {
182        self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
183        self.w
184    }
185}
186impl R {
187    #[doc = "Bits 0:2 - Period Counter Prescaler"]
188    #[inline(always)]
189    pub fn pcpresc(&self) -> PCPRESC_R {
190        PCPRESC_R::new((self.bits & 0x07) as u8)
191    }
192    #[doc = "Bits 8:15 - Period Counter Top Value"]
193    #[inline(always)]
194    pub fn pctop(&self) -> PCTOP_R {
195        PCTOP_R::new(((self.bits >> 8) & 0xff) as u8)
196    }
197    #[doc = "Bits 16:17 - Warmup Period Counter"]
198    #[inline(always)]
199    pub fn warmupcnt(&self) -> WARMUPCNT_R {
200        WARMUPCNT_R::new(((self.bits >> 16) & 0x03) as u8)
201    }
202}
203impl W {
204    #[doc = "Bits 0:2 - Period Counter Prescaler"]
205    #[inline(always)]
206    pub fn pcpresc(&mut self) -> PCPRESC_W {
207        PCPRESC_W { w: self }
208    }
209    #[doc = "Bits 8:15 - Period Counter Top Value"]
210    #[inline(always)]
211    pub fn pctop(&mut self) -> PCTOP_W {
212        PCTOP_W { w: self }
213    }
214    #[doc = "Bits 16:17 - Warmup Period Counter"]
215    #[inline(always)]
216    pub fn warmupcnt(&mut self) -> WARMUPCNT_W {
217        WARMUPCNT_W { w: self }
218    }
219}
efm32pg12_pac/csen/timctrl.rs

efm32pg12_pac/csen/
timctrl.rs
