efm32pg12_pac/cmu/
dpllctrl.rs1#[doc = "Reader of register DPLLCTRL"]
2pub type R = crate::R<u32, super::DPLLCTRL>;
3#[doc = "Writer for register DPLLCTRL"]
4pub type W = crate::W<u32, super::DPLLCTRL>;
5#[doc = "Register DPLLCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::DPLLCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `MODE`"]
14pub type MODE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `MODE`"]
16pub struct MODE_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> MODE_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `EDGESEL`"]
38pub type EDGESEL_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `EDGESEL`"]
40pub struct EDGESEL_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> EDGESEL_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `AUTORECOVER`"]
62pub type AUTORECOVER_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `AUTORECOVER`"]
64pub struct AUTORECOVER_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> AUTORECOVER_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82 self.w
83 }
84}
85#[doc = "Reference Clock Selection Control\n\nValue on reset: 0"]
86#[derive(Clone, Copy, Debug, PartialEq)]
87#[repr(u8)]
88pub enum REFSEL_A {
89 #[doc = "0: HFXO selected"]
90 HFXO = 0,
91 #[doc = "1: LFXO selected"]
92 LFXO = 1,
93 #[doc = "3: CLKIN0 selected"]
94 CLKIN0 = 3,
95}
96impl From<REFSEL_A> for u8 {
97 #[inline(always)]
98 fn from(variant: REFSEL_A) -> Self {
99 variant as _
100 }
101}
102#[doc = "Reader of field `REFSEL`"]
103pub type REFSEL_R = crate::R<u8, REFSEL_A>;
104impl REFSEL_R {
105 #[doc = r"Get enumerated values variant"]
106 #[inline(always)]
107 pub fn variant(&self) -> crate::Variant<u8, REFSEL_A> {
108 use crate::Variant::*;
109 match self.bits {
110 0 => Val(REFSEL_A::HFXO),
111 1 => Val(REFSEL_A::LFXO),
112 3 => Val(REFSEL_A::CLKIN0),
113 i => Res(i),
114 }
115 }
116 #[doc = "Checks if the value of the field is `HFXO`"]
117 #[inline(always)]
118 pub fn is_hfxo(&self) -> bool {
119 *self == REFSEL_A::HFXO
120 }
121 #[doc = "Checks if the value of the field is `LFXO`"]
122 #[inline(always)]
123 pub fn is_lfxo(&self) -> bool {
124 *self == REFSEL_A::LFXO
125 }
126 #[doc = "Checks if the value of the field is `CLKIN0`"]
127 #[inline(always)]
128 pub fn is_clkin0(&self) -> bool {
129 *self == REFSEL_A::CLKIN0
130 }
131}
132#[doc = "Write proxy for field `REFSEL`"]
133pub struct REFSEL_W<'a> {
134 w: &'a mut W,
135}
136impl<'a> REFSEL_W<'a> {
137 #[doc = r"Writes `variant` to the field"]
138 #[inline(always)]
139 pub fn variant(self, variant: REFSEL_A) -> &'a mut W {
140 unsafe { self.bits(variant.into()) }
141 }
142 #[doc = "HFXO selected"]
143 #[inline(always)]
144 pub fn hfxo(self) -> &'a mut W {
145 self.variant(REFSEL_A::HFXO)
146 }
147 #[doc = "LFXO selected"]
148 #[inline(always)]
149 pub fn lfxo(self) -> &'a mut W {
150 self.variant(REFSEL_A::LFXO)
151 }
152 #[doc = "CLKIN0 selected"]
153 #[inline(always)]
154 pub fn clkin0(self) -> &'a mut W {
155 self.variant(REFSEL_A::CLKIN0)
156 }
157 #[doc = r"Writes raw bits to the field"]
158 #[inline(always)]
159 pub unsafe fn bits(self, value: u8) -> &'a mut W {
160 self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
161 self.w
162 }
163}
164impl R {
165 #[doc = "Bit 0 - Operating Mode Control"]
166 #[inline(always)]
167 pub fn mode(&self) -> MODE_R {
168 MODE_R::new((self.bits & 0x01) != 0)
169 }
170 #[doc = "Bit 1 - Reference Edge Select"]
171 #[inline(always)]
172 pub fn edgesel(&self) -> EDGESEL_R {
173 EDGESEL_R::new(((self.bits >> 1) & 0x01) != 0)
174 }
175 #[doc = "Bit 2 - Automatic Recovery Ctrl"]
176 #[inline(always)]
177 pub fn autorecover(&self) -> AUTORECOVER_R {
178 AUTORECOVER_R::new(((self.bits >> 2) & 0x01) != 0)
179 }
180 #[doc = "Bits 3:4 - Reference Clock Selection Control"]
181 #[inline(always)]
182 pub fn refsel(&self) -> REFSEL_R {
183 REFSEL_R::new(((self.bits >> 3) & 0x03) as u8)
184 }
185}
186impl W {
187 #[doc = "Bit 0 - Operating Mode Control"]
188 #[inline(always)]
189 pub fn mode(&mut self) -> MODE_W {
190 MODE_W { w: self }
191 }
192 #[doc = "Bit 1 - Reference Edge Select"]
193 #[inline(always)]
194 pub fn edgesel(&mut self) -> EDGESEL_W {
195 EDGESEL_W { w: self }
196 }
197 #[doc = "Bit 2 - Automatic Recovery Ctrl"]
198 #[inline(always)]
199 pub fn autorecover(&mut self) -> AUTORECOVER_W {
200 AUTORECOVER_W { w: self }
201 }
202 #[doc = "Bits 3:4 - Reference Clock Selection Control"]
203 #[inline(always)]
204 pub fn refsel(&mut self) -> REFSEL_W {
205 REFSEL_W { w: self }
206 }
207}