efm32pg12_pac/msc/
ramctrl.rs

1#[doc = "Reader of register RAMCTRL"]
2pub type R = crate::R<u32, super::RAMCTRL>;
3#[doc = "Writer for register RAMCTRL"]
4pub type W = crate::W<u32, super::RAMCTRL>;
5#[doc = "Register RAMCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::RAMCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `RAMCACHEEN`"]
14pub type RAMCACHEEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `RAMCACHEEN`"]
16pub struct RAMCACHEEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RAMCACHEEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `RAM1CACHEEN`"]
38pub type RAM1CACHEEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `RAM1CACHEEN`"]
40pub struct RAM1CACHEEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> RAM1CACHEEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
58        self.w
59    }
60}
61impl R {
62    #[doc = "Bit 0 - RAM CACHE Enable"]
63    #[inline(always)]
64    pub fn ramcacheen(&self) -> RAMCACHEEN_R {
65        RAMCACHEEN_R::new((self.bits & 0x01) != 0)
66    }
67    #[doc = "Bit 8 - RAM1 CACHE Enable"]
68    #[inline(always)]
69    pub fn ram1cacheen(&self) -> RAM1CACHEEN_R {
70        RAM1CACHEEN_R::new(((self.bits >> 8) & 0x01) != 0)
71    }
72}
73impl W {
74    #[doc = "Bit 0 - RAM CACHE Enable"]
75    #[inline(always)]
76    pub fn ramcacheen(&mut self) -> RAMCACHEEN_W {
77        RAMCACHEEN_W { w: self }
78    }
79    #[doc = "Bit 8 - RAM1 CACHE Enable"]
80    #[inline(always)]
81    pub fn ram1cacheen(&mut self) -> RAM1CACHEEN_W {
82        RAM1CACHEEN_W { w: self }
83    }
84}
efm32pg12_pac/msc/ramctrl.rs

efm32pg12_pac/msc/
ramctrl.rs
