efm32pg12_pac/gpio/
routepen.rs

1#[doc = "Reader of register ROUTEPEN"]
2pub type R = crate::R<u32, super::ROUTEPEN>;
3#[doc = "Writer for register ROUTEPEN"]
4pub type W = crate::W<u32, super::ROUTEPEN>;
5#[doc = "Register ROUTEPEN `reset()`'s with value 0x0f"]
6impl crate::ResetValue for super::ROUTEPEN {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0f
11    }
12}
13#[doc = "Reader of field `SWCLKTCKPEN`"]
14pub type SWCLKTCKPEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `SWCLKTCKPEN`"]
16pub struct SWCLKTCKPEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> SWCLKTCKPEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `SWDIOTMSPEN`"]
38pub type SWDIOTMSPEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `SWDIOTMSPEN`"]
40pub struct SWDIOTMSPEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> SWDIOTMSPEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `TDOPEN`"]
62pub type TDOPEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `TDOPEN`"]
64pub struct TDOPEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> TDOPEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `TDIPEN`"]
86pub type TDIPEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `TDIPEN`"]
88pub struct TDIPEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> TDIPEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `SWVPEN`"]
110pub type SWVPEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `SWVPEN`"]
112pub struct SWVPEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> SWVPEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133#[doc = "Reader of field `ETMTCLKPEN`"]
134pub type ETMTCLKPEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `ETMTCLKPEN`"]
136pub struct ETMTCLKPEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> ETMTCLKPEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
154        self.w
155    }
156}
157#[doc = "Reader of field `ETMTD0PEN`"]
158pub type ETMTD0PEN_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `ETMTD0PEN`"]
160pub struct ETMTD0PEN_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> ETMTD0PEN_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
178        self.w
179    }
180}
181#[doc = "Reader of field `ETMTD1PEN`"]
182pub type ETMTD1PEN_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `ETMTD1PEN`"]
184pub struct ETMTD1PEN_W<'a> {
185    w: &'a mut W,
186}
187impl<'a> ETMTD1PEN_W<'a> {
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
202        self.w
203    }
204}
205#[doc = "Reader of field `ETMTD2PEN`"]
206pub type ETMTD2PEN_R = crate::R<bool, bool>;
207#[doc = "Write proxy for field `ETMTD2PEN`"]
208pub struct ETMTD2PEN_W<'a> {
209    w: &'a mut W,
210}
211impl<'a> ETMTD2PEN_W<'a> {
212    #[doc = r"Sets the field bit"]
213    #[inline(always)]
214    pub fn set_bit(self) -> &'a mut W {
215        self.bit(true)
216    }
217    #[doc = r"Clears the field bit"]
218    #[inline(always)]
219    pub fn clear_bit(self) -> &'a mut W {
220        self.bit(false)
221    }
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub fn bit(self, value: bool) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
226        self.w
227    }
228}
229#[doc = "Reader of field `ETMTD3PEN`"]
230pub type ETMTD3PEN_R = crate::R<bool, bool>;
231#[doc = "Write proxy for field `ETMTD3PEN`"]
232pub struct ETMTD3PEN_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> ETMTD3PEN_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
250        self.w
251    }
252}
253impl R {
254    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
255    #[inline(always)]
256    pub fn swclktckpen(&self) -> SWCLKTCKPEN_R {
257        SWCLKTCKPEN_R::new((self.bits & 0x01) != 0)
258    }
259    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
260    #[inline(always)]
261    pub fn swdiotmspen(&self) -> SWDIOTMSPEN_R {
262        SWDIOTMSPEN_R::new(((self.bits >> 1) & 0x01) != 0)
263    }
264    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
265    #[inline(always)]
266    pub fn tdopen(&self) -> TDOPEN_R {
267        TDOPEN_R::new(((self.bits >> 2) & 0x01) != 0)
268    }
269    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
270    #[inline(always)]
271    pub fn tdipen(&self) -> TDIPEN_R {
272        TDIPEN_R::new(((self.bits >> 3) & 0x01) != 0)
273    }
274    #[doc = "Bit 4 - Serial Wire Viewer Output Pin Enable"]
275    #[inline(always)]
276    pub fn swvpen(&self) -> SWVPEN_R {
277        SWVPEN_R::new(((self.bits >> 4) & 0x01) != 0)
278    }
279    #[doc = "Bit 16 - ETM Trace Clock Pin Enable"]
280    #[inline(always)]
281    pub fn etmtclkpen(&self) -> ETMTCLKPEN_R {
282        ETMTCLKPEN_R::new(((self.bits >> 16) & 0x01) != 0)
283    }
284    #[doc = "Bit 17 - ETM Trace Data Pin Enable"]
285    #[inline(always)]
286    pub fn etmtd0pen(&self) -> ETMTD0PEN_R {
287        ETMTD0PEN_R::new(((self.bits >> 17) & 0x01) != 0)
288    }
289    #[doc = "Bit 18 - ETM Trace Data Pin Enable"]
290    #[inline(always)]
291    pub fn etmtd1pen(&self) -> ETMTD1PEN_R {
292        ETMTD1PEN_R::new(((self.bits >> 18) & 0x01) != 0)
293    }
294    #[doc = "Bit 19 - ETM Trace Data Pin Enable"]
295    #[inline(always)]
296    pub fn etmtd2pen(&self) -> ETMTD2PEN_R {
297        ETMTD2PEN_R::new(((self.bits >> 19) & 0x01) != 0)
298    }
299    #[doc = "Bit 20 - ETM Trace Data Pin Enable"]
300    #[inline(always)]
301    pub fn etmtd3pen(&self) -> ETMTD3PEN_R {
302        ETMTD3PEN_R::new(((self.bits >> 20) & 0x01) != 0)
303    }
304}
305impl W {
306    #[doc = "Bit 0 - Serial Wire Clock and JTAG Test Clock Pin Enable"]
307    #[inline(always)]
308    pub fn swclktckpen(&mut self) -> SWCLKTCKPEN_W {
309        SWCLKTCKPEN_W { w: self }
310    }
311    #[doc = "Bit 1 - Serial Wire Data and JTAG Test Mode Select Pin Enable"]
312    #[inline(always)]
313    pub fn swdiotmspen(&mut self) -> SWDIOTMSPEN_W {
314        SWDIOTMSPEN_W { w: self }
315    }
316    #[doc = "Bit 2 - JTAG Test Debug Output Pin Enable"]
317    #[inline(always)]
318    pub fn tdopen(&mut self) -> TDOPEN_W {
319        TDOPEN_W { w: self }
320    }
321    #[doc = "Bit 3 - JTAG Test Debug Input Pin Enable"]
322    #[inline(always)]
323    pub fn tdipen(&mut self) -> TDIPEN_W {
324        TDIPEN_W { w: self }
325    }
326    #[doc = "Bit 4 - Serial Wire Viewer Output Pin Enable"]
327    #[inline(always)]
328    pub fn swvpen(&mut self) -> SWVPEN_W {
329        SWVPEN_W { w: self }
330    }
331    #[doc = "Bit 16 - ETM Trace Clock Pin Enable"]
332    #[inline(always)]
333    pub fn etmtclkpen(&mut self) -> ETMTCLKPEN_W {
334        ETMTCLKPEN_W { w: self }
335    }
336    #[doc = "Bit 17 - ETM Trace Data Pin Enable"]
337    #[inline(always)]
338    pub fn etmtd0pen(&mut self) -> ETMTD0PEN_W {
339        ETMTD0PEN_W { w: self }
340    }
341    #[doc = "Bit 18 - ETM Trace Data Pin Enable"]
342    #[inline(always)]
343    pub fn etmtd1pen(&mut self) -> ETMTD1PEN_W {
344        ETMTD1PEN_W { w: self }
345    }
346    #[doc = "Bit 19 - ETM Trace Data Pin Enable"]
347    #[inline(always)]
348    pub fn etmtd2pen(&mut self) -> ETMTD2PEN_W {
349        ETMTD2PEN_W { w: self }
350    }
351    #[doc = "Bit 20 - ETM Trace Data Pin Enable"]
352    #[inline(always)]
353    pub fn etmtd3pen(&mut self) -> ETMTD3PEN_W {
354        ETMTD3PEN_W { w: self }
355    }
356}
efm32pg12_pac/gpio/routepen.rs

efm32pg12_pac/gpio/
routepen.rs
