efm32pg12_pac/etm/
etmcr.rs

1#[doc = "Reader of register ETMCR"]
2pub type R = crate::R<u32, super::ETMCR>;
3#[doc = "Writer for register ETMCR"]
4pub type W = crate::W<u32, super::ETMCR>;
5#[doc = "Register ETMCR `reset()`'s with value 0x0411"]
6impl crate::ResetValue for super::ETMCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0411
11    }
12}
13#[doc = "Reader of field `POWERDWN`"]
14pub type POWERDWN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `POWERDWN`"]
16pub struct POWERDWN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> POWERDWN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `PORTSIZE`"]
38pub type PORTSIZE_R = crate::R<u8, u8>;
39#[doc = "Write proxy for field `PORTSIZE`"]
40pub struct PORTSIZE_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> PORTSIZE_W<'a> {
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub unsafe fn bits(self, value: u8) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
48        self.w
49    }
50}
51#[doc = "Reader of field `STALL`"]
52pub type STALL_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `STALL`"]
54pub struct STALL_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> STALL_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W {
61        self.bit(true)
62    }
63    #[doc = r"Clears the field bit"]
64    #[inline(always)]
65    pub fn clear_bit(self) -> &'a mut W {
66        self.bit(false)
67    }
68    #[doc = r"Writes raw bits to the field"]
69    #[inline(always)]
70    pub fn bit(self, value: bool) -> &'a mut W {
71        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
72        self.w
73    }
74}
75#[doc = "Reader of field `BRANCHOUTPUT`"]
76pub type BRANCHOUTPUT_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `BRANCHOUTPUT`"]
78pub struct BRANCHOUTPUT_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> BRANCHOUTPUT_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
96        self.w
97    }
98}
99#[doc = "Reader of field `DBGREQCTRL`"]
100pub type DBGREQCTRL_R = crate::R<bool, bool>;
101#[doc = "Write proxy for field `DBGREQCTRL`"]
102pub struct DBGREQCTRL_W<'a> {
103    w: &'a mut W,
104}
105impl<'a> DBGREQCTRL_W<'a> {
106    #[doc = r"Sets the field bit"]
107    #[inline(always)]
108    pub fn set_bit(self) -> &'a mut W {
109        self.bit(true)
110    }
111    #[doc = r"Clears the field bit"]
112    #[inline(always)]
113    pub fn clear_bit(self) -> &'a mut W {
114        self.bit(false)
115    }
116    #[doc = r"Writes raw bits to the field"]
117    #[inline(always)]
118    pub fn bit(self, value: bool) -> &'a mut W {
119        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
120        self.w
121    }
122}
123#[doc = "Reader of field `ETMPROG`"]
124pub type ETMPROG_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `ETMPROG`"]
126pub struct ETMPROG_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> ETMPROG_W<'a> {
130    #[doc = r"Sets the field bit"]
131    #[inline(always)]
132    pub fn set_bit(self) -> &'a mut W {
133        self.bit(true)
134    }
135    #[doc = r"Clears the field bit"]
136    #[inline(always)]
137    pub fn clear_bit(self) -> &'a mut W {
138        self.bit(false)
139    }
140    #[doc = r"Writes raw bits to the field"]
141    #[inline(always)]
142    pub fn bit(self, value: bool) -> &'a mut W {
143        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
144        self.w
145    }
146}
147#[doc = "Reader of field `ETMPORTSEL`"]
148pub type ETMPORTSEL_R = crate::R<bool, bool>;
149#[doc = "Write proxy for field `ETMPORTSEL`"]
150pub struct ETMPORTSEL_W<'a> {
151    w: &'a mut W,
152}
153impl<'a> ETMPORTSEL_W<'a> {
154    #[doc = r"Sets the field bit"]
155    #[inline(always)]
156    pub fn set_bit(self) -> &'a mut W {
157        self.bit(true)
158    }
159    #[doc = r"Clears the field bit"]
160    #[inline(always)]
161    pub fn clear_bit(self) -> &'a mut W {
162        self.bit(false)
163    }
164    #[doc = r"Writes raw bits to the field"]
165    #[inline(always)]
166    pub fn bit(self, value: bool) -> &'a mut W {
167        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
168        self.w
169    }
170}
171#[doc = "Reader of field `PORTMODE2`"]
172pub type PORTMODE2_R = crate::R<bool, bool>;
173#[doc = "Write proxy for field `PORTMODE2`"]
174pub struct PORTMODE2_W<'a> {
175    w: &'a mut W,
176}
177impl<'a> PORTMODE2_W<'a> {
178    #[doc = r"Sets the field bit"]
179    #[inline(always)]
180    pub fn set_bit(self) -> &'a mut W {
181        self.bit(true)
182    }
183    #[doc = r"Clears the field bit"]
184    #[inline(always)]
185    pub fn clear_bit(self) -> &'a mut W {
186        self.bit(false)
187    }
188    #[doc = r"Writes raw bits to the field"]
189    #[inline(always)]
190    pub fn bit(self, value: bool) -> &'a mut W {
191        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
192        self.w
193    }
194}
195#[doc = "Reader of field `PORTMODE`"]
196pub type PORTMODE_R = crate::R<u8, u8>;
197#[doc = "Write proxy for field `PORTMODE`"]
198pub struct PORTMODE_W<'a> {
199    w: &'a mut W,
200}
201impl<'a> PORTMODE_W<'a> {
202    #[doc = r"Writes raw bits to the field"]
203    #[inline(always)]
204    pub unsafe fn bits(self, value: u8) -> &'a mut W {
205        self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
206        self.w
207    }
208}
209#[doc = "Reader of field `EPORTSIZE`"]
210pub type EPORTSIZE_R = crate::R<u8, u8>;
211#[doc = "Write proxy for field `EPORTSIZE`"]
212pub struct EPORTSIZE_W<'a> {
213    w: &'a mut W,
214}
215impl<'a> EPORTSIZE_W<'a> {
216    #[doc = r"Writes raw bits to the field"]
217    #[inline(always)]
218    pub unsafe fn bits(self, value: u8) -> &'a mut W {
219        self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21);
220        self.w
221    }
222}
223#[doc = "Reader of field `TSTAMPEN`"]
224pub type TSTAMPEN_R = crate::R<bool, bool>;
225#[doc = "Write proxy for field `TSTAMPEN`"]
226pub struct TSTAMPEN_W<'a> {
227    w: &'a mut W,
228}
229impl<'a> TSTAMPEN_W<'a> {
230    #[doc = r"Sets the field bit"]
231    #[inline(always)]
232    pub fn set_bit(self) -> &'a mut W {
233        self.bit(true)
234    }
235    #[doc = r"Clears the field bit"]
236    #[inline(always)]
237    pub fn clear_bit(self) -> &'a mut W {
238        self.bit(false)
239    }
240    #[doc = r"Writes raw bits to the field"]
241    #[inline(always)]
242    pub fn bit(self, value: bool) -> &'a mut W {
243        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
244        self.w
245    }
246}
247impl R {
248    #[doc = "Bit 0 - ETM Control in low power mode"]
249    #[inline(always)]
250    pub fn powerdwn(&self) -> POWERDWN_R {
251        POWERDWN_R::new((self.bits & 0x01) != 0)
252    }
253    #[doc = "Bits 4:6 - ETM Port Size"]
254    #[inline(always)]
255    pub fn portsize(&self) -> PORTSIZE_R {
256        PORTSIZE_R::new(((self.bits >> 4) & 0x07) as u8)
257    }
258    #[doc = "Bit 7 - Stall Processor"]
259    #[inline(always)]
260    pub fn stall(&self) -> STALL_R {
261        STALL_R::new(((self.bits >> 7) & 0x01) != 0)
262    }
263    #[doc = "Bit 8 - Branch Output"]
264    #[inline(always)]
265    pub fn branchoutput(&self) -> BRANCHOUTPUT_R {
266        BRANCHOUTPUT_R::new(((self.bits >> 8) & 0x01) != 0)
267    }
268    #[doc = "Bit 9 - Debug Request Control"]
269    #[inline(always)]
270    pub fn dbgreqctrl(&self) -> DBGREQCTRL_R {
271        DBGREQCTRL_R::new(((self.bits >> 9) & 0x01) != 0)
272    }
273    #[doc = "Bit 10 - ETM Programming"]
274    #[inline(always)]
275    pub fn etmprog(&self) -> ETMPROG_R {
276        ETMPROG_R::new(((self.bits >> 10) & 0x01) != 0)
277    }
278    #[doc = "Bit 11 - ETM Port Selection"]
279    #[inline(always)]
280    pub fn etmportsel(&self) -> ETMPORTSEL_R {
281        ETMPORTSEL_R::new(((self.bits >> 11) & 0x01) != 0)
282    }
283    #[doc = "Bit 13 - Port Mode\\[2\\]"]
284    #[inline(always)]
285    pub fn portmode2(&self) -> PORTMODE2_R {
286        PORTMODE2_R::new(((self.bits >> 13) & 0x01) != 0)
287    }
288    #[doc = "Bits 16:17 - Port Mode Control"]
289    #[inline(always)]
290    pub fn portmode(&self) -> PORTMODE_R {
291        PORTMODE_R::new(((self.bits >> 16) & 0x03) as u8)
292    }
293    #[doc = "Bits 21:22 - Port Size\\[3\\]"]
294    #[inline(always)]
295    pub fn eportsize(&self) -> EPORTSIZE_R {
296        EPORTSIZE_R::new(((self.bits >> 21) & 0x03) as u8)
297    }
298    #[doc = "Bit 28 - Time Stamp Enable"]
299    #[inline(always)]
300    pub fn tstampen(&self) -> TSTAMPEN_R {
301        TSTAMPEN_R::new(((self.bits >> 28) & 0x01) != 0)
302    }
303}
304impl W {
305    #[doc = "Bit 0 - ETM Control in low power mode"]
306    #[inline(always)]
307    pub fn powerdwn(&mut self) -> POWERDWN_W {
308        POWERDWN_W { w: self }
309    }
310    #[doc = "Bits 4:6 - ETM Port Size"]
311    #[inline(always)]
312    pub fn portsize(&mut self) -> PORTSIZE_W {
313        PORTSIZE_W { w: self }
314    }
315    #[doc = "Bit 7 - Stall Processor"]
316    #[inline(always)]
317    pub fn stall(&mut self) -> STALL_W {
318        STALL_W { w: self }
319    }
320    #[doc = "Bit 8 - Branch Output"]
321    #[inline(always)]
322    pub fn branchoutput(&mut self) -> BRANCHOUTPUT_W {
323        BRANCHOUTPUT_W { w: self }
324    }
325    #[doc = "Bit 9 - Debug Request Control"]
326    #[inline(always)]
327    pub fn dbgreqctrl(&mut self) -> DBGREQCTRL_W {
328        DBGREQCTRL_W { w: self }
329    }
330    #[doc = "Bit 10 - ETM Programming"]
331    #[inline(always)]
332    pub fn etmprog(&mut self) -> ETMPROG_W {
333        ETMPROG_W { w: self }
334    }
335    #[doc = "Bit 11 - ETM Port Selection"]
336    #[inline(always)]
337    pub fn etmportsel(&mut self) -> ETMPORTSEL_W {
338        ETMPORTSEL_W { w: self }
339    }
340    #[doc = "Bit 13 - Port Mode\\[2\\]"]
341    #[inline(always)]
342    pub fn portmode2(&mut self) -> PORTMODE2_W {
343        PORTMODE2_W { w: self }
344    }
345    #[doc = "Bits 16:17 - Port Mode Control"]
346    #[inline(always)]
347    pub fn portmode(&mut self) -> PORTMODE_W {
348        PORTMODE_W { w: self }
349    }
350    #[doc = "Bits 21:22 - Port Size\\[3\\]"]
351    #[inline(always)]
352    pub fn eportsize(&mut self) -> EPORTSIZE_W {
353        EPORTSIZE_W { w: self }
354    }
355    #[doc = "Bit 28 - Time Stamp Enable"]
356    #[inline(always)]
357    pub fn tstampen(&mut self) -> TSTAMPEN_W {
358        TSTAMPEN_W { w: self }
359    }
360}
efm32pg12_pac/etm/etmcr.rs

efm32pg12_pac/etm/
etmcr.rs
