efm32pg12_pac/etm/
etmtecr1.rs

1#[doc = "Reader of register ETMTECR1"]
2pub type R = crate::R<u32, super::ETMTECR1>;
3#[doc = "Writer for register ETMTECR1"]
4pub type W = crate::W<u32, super::ETMTECR1>;
5#[doc = "Register ETMTECR1 `reset()`'s with value 0"]
6impl crate::ResetValue for super::ETMTECR1 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `ADRCMP`"]
14pub type ADRCMP_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `ADRCMP`"]
16pub struct ADRCMP_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> ADRCMP_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
24        self.w
25    }
26}
27#[doc = "Reader of field `MEMMAP`"]
28pub type MEMMAP_R = crate::R<u16, u16>;
29#[doc = "Write proxy for field `MEMMAP`"]
30pub struct MEMMAP_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> MEMMAP_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u16) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0xffff << 8)) | (((value as u32) & 0xffff) << 8);
38        self.w
39    }
40}
41#[doc = "Reader of field `INCEXCTL`"]
42pub type INCEXCTL_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `INCEXCTL`"]
44pub struct INCEXCTL_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> INCEXCTL_W<'a> {
48    #[doc = r"Sets the field bit"]
49    #[inline(always)]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r"Clears the field bit"]
54    #[inline(always)]
55    pub fn clear_bit(self) -> &'a mut W {
56        self.bit(false)
57    }
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub fn bit(self, value: bool) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
62        self.w
63    }
64}
65#[doc = "Reader of field `TCE`"]
66pub type TCE_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `TCE`"]
68pub struct TCE_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> TCE_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
86        self.w
87    }
88}
89impl R {
90    #[doc = "Bits 0:7 - Address Comparator"]
91    #[inline(always)]
92    pub fn adrcmp(&self) -> ADRCMP_R {
93        ADRCMP_R::new((self.bits & 0xff) as u8)
94    }
95    #[doc = "Bits 8:23 - Memmap"]
96    #[inline(always)]
97    pub fn memmap(&self) -> MEMMAP_R {
98        MEMMAP_R::new(((self.bits >> 8) & 0xffff) as u16)
99    }
100    #[doc = "Bit 24 - Trace Include/Exclude Flag"]
101    #[inline(always)]
102    pub fn incexctl(&self) -> INCEXCTL_R {
103        INCEXCTL_R::new(((self.bits >> 24) & 0x01) != 0)
104    }
105    #[doc = "Bit 25 - Trace Control Enable"]
106    #[inline(always)]
107    pub fn tce(&self) -> TCE_R {
108        TCE_R::new(((self.bits >> 25) & 0x01) != 0)
109    }
110}
111impl W {
112    #[doc = "Bits 0:7 - Address Comparator"]
113    #[inline(always)]
114    pub fn adrcmp(&mut self) -> ADRCMP_W {
115        ADRCMP_W { w: self }
116    }
117    #[doc = "Bits 8:23 - Memmap"]
118    #[inline(always)]
119    pub fn memmap(&mut self) -> MEMMAP_W {
120        MEMMAP_W { w: self }
121    }
122    #[doc = "Bit 24 - Trace Include/Exclude Flag"]
123    #[inline(always)]
124    pub fn incexctl(&mut self) -> INCEXCTL_W {
125        INCEXCTL_W { w: self }
126    }
127    #[doc = "Bit 25 - Trace Control Enable"]
128    #[inline(always)]
129    pub fn tce(&mut self) -> TCE_W {
130        TCE_W { w: self }
131    }
132}
efm32pg12_pac/etm/etmtecr1.rs

efm32pg12_pac/etm/
etmtecr1.rs
