efm32pg12_pac/vdac0/
ch0ctrl.rs1#[doc = "Reader of register CH0CTRL"]
2pub type R = crate::R<u32, super::CH0CTRL>;
3#[doc = "Writer for register CH0CTRL"]
4pub type W = crate::W<u32, super::CH0CTRL>;
5#[doc = "Register CH0CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CH0CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `CONVMODE`"]
14pub type CONVMODE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `CONVMODE`"]
16pub struct CONVMODE_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> CONVMODE_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Channel 0 Trigger Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum TRIGMODE_A {
41 #[doc = "0: Channel 0 is triggered by CH0DATA or COMBDATA write"]
42 SW = 0,
43 #[doc = "1: Channel 0 is triggered by PRS input"]
44 PRS = 1,
45 #[doc = "2: Channel 0 is triggered by Refresh timer"]
46 REFRESH = 2,
47 #[doc = "3: Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input"]
48 SWPRS = 3,
49 #[doc = "4: Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer"]
50 SWREFRESH = 4,
51 #[doc = "5: Channel 0 is triggered by LESENSE"]
52 LESENSE = 5,
53}
54impl From<TRIGMODE_A> for u8 {
55 #[inline(always)]
56 fn from(variant: TRIGMODE_A) -> Self {
57 variant as _
58 }
59}
60#[doc = "Reader of field `TRIGMODE`"]
61pub type TRIGMODE_R = crate::R<u8, TRIGMODE_A>;
62impl TRIGMODE_R {
63 #[doc = r"Get enumerated values variant"]
64 #[inline(always)]
65 pub fn variant(&self) -> crate::Variant<u8, TRIGMODE_A> {
66 use crate::Variant::*;
67 match self.bits {
68 0 => Val(TRIGMODE_A::SW),
69 1 => Val(TRIGMODE_A::PRS),
70 2 => Val(TRIGMODE_A::REFRESH),
71 3 => Val(TRIGMODE_A::SWPRS),
72 4 => Val(TRIGMODE_A::SWREFRESH),
73 5 => Val(TRIGMODE_A::LESENSE),
74 i => Res(i),
75 }
76 }
77 #[doc = "Checks if the value of the field is `SW`"]
78 #[inline(always)]
79 pub fn is_sw(&self) -> bool {
80 *self == TRIGMODE_A::SW
81 }
82 #[doc = "Checks if the value of the field is `PRS`"]
83 #[inline(always)]
84 pub fn is_prs(&self) -> bool {
85 *self == TRIGMODE_A::PRS
86 }
87 #[doc = "Checks if the value of the field is `REFRESH`"]
88 #[inline(always)]
89 pub fn is_refresh(&self) -> bool {
90 *self == TRIGMODE_A::REFRESH
91 }
92 #[doc = "Checks if the value of the field is `SWPRS`"]
93 #[inline(always)]
94 pub fn is_swprs(&self) -> bool {
95 *self == TRIGMODE_A::SWPRS
96 }
97 #[doc = "Checks if the value of the field is `SWREFRESH`"]
98 #[inline(always)]
99 pub fn is_swrefresh(&self) -> bool {
100 *self == TRIGMODE_A::SWREFRESH
101 }
102 #[doc = "Checks if the value of the field is `LESENSE`"]
103 #[inline(always)]
104 pub fn is_lesense(&self) -> bool {
105 *self == TRIGMODE_A::LESENSE
106 }
107}
108#[doc = "Write proxy for field `TRIGMODE`"]
109pub struct TRIGMODE_W<'a> {
110 w: &'a mut W,
111}
112impl<'a> TRIGMODE_W<'a> {
113 #[doc = r"Writes `variant` to the field"]
114 #[inline(always)]
115 pub fn variant(self, variant: TRIGMODE_A) -> &'a mut W {
116 unsafe { self.bits(variant.into()) }
117 }
118 #[doc = "Channel 0 is triggered by CH0DATA or COMBDATA write"]
119 #[inline(always)]
120 pub fn sw(self) -> &'a mut W {
121 self.variant(TRIGMODE_A::SW)
122 }
123 #[doc = "Channel 0 is triggered by PRS input"]
124 #[inline(always)]
125 pub fn prs(self) -> &'a mut W {
126 self.variant(TRIGMODE_A::PRS)
127 }
128 #[doc = "Channel 0 is triggered by Refresh timer"]
129 #[inline(always)]
130 pub fn refresh(self) -> &'a mut W {
131 self.variant(TRIGMODE_A::REFRESH)
132 }
133 #[doc = "Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input"]
134 #[inline(always)]
135 pub fn swprs(self) -> &'a mut W {
136 self.variant(TRIGMODE_A::SWPRS)
137 }
138 #[doc = "Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer"]
139 #[inline(always)]
140 pub fn swrefresh(self) -> &'a mut W {
141 self.variant(TRIGMODE_A::SWREFRESH)
142 }
143 #[doc = "Channel 0 is triggered by LESENSE"]
144 #[inline(always)]
145 pub fn lesense(self) -> &'a mut W {
146 self.variant(TRIGMODE_A::LESENSE)
147 }
148 #[doc = r"Writes raw bits to the field"]
149 #[inline(always)]
150 pub unsafe fn bits(self, value: u8) -> &'a mut W {
151 self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
152 self.w
153 }
154}
155#[doc = "Reader of field `PRSASYNC`"]
156pub type PRSASYNC_R = crate::R<bool, bool>;
157#[doc = "Write proxy for field `PRSASYNC`"]
158pub struct PRSASYNC_W<'a> {
159 w: &'a mut W,
160}
161impl<'a> PRSASYNC_W<'a> {
162 #[doc = r"Sets the field bit"]
163 #[inline(always)]
164 pub fn set_bit(self) -> &'a mut W {
165 self.bit(true)
166 }
167 #[doc = r"Clears the field bit"]
168 #[inline(always)]
169 pub fn clear_bit(self) -> &'a mut W {
170 self.bit(false)
171 }
172 #[doc = r"Writes raw bits to the field"]
173 #[inline(always)]
174 pub fn bit(self, value: bool) -> &'a mut W {
175 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
176 self.w
177 }
178}
179#[doc = "Channel 0 PRS Trigger Select\n\nValue on reset: 0"]
180#[derive(Clone, Copy, Debug, PartialEq)]
181#[repr(u8)]
182pub enum PRSSEL_A {
183 #[doc = "0: PRS ch 0 triggers a conversion."]
184 PRSCH0 = 0,
185 #[doc = "1: PRS ch 1 triggers a conversion."]
186 PRSCH1 = 1,
187 #[doc = "2: PRS ch 2 triggers a conversion."]
188 PRSCH2 = 2,
189 #[doc = "3: PRS ch 3 triggers a conversion."]
190 PRSCH3 = 3,
191 #[doc = "4: PRS ch 4 triggers a conversion."]
192 PRSCH4 = 4,
193 #[doc = "5: PRS ch 5 triggers a conversion."]
194 PRSCH5 = 5,
195 #[doc = "6: PRS ch 6 triggers a conversion."]
196 PRSCH6 = 6,
197 #[doc = "7: PRS ch 7 triggers a conversion."]
198 PRSCH7 = 7,
199 #[doc = "8: PRS ch 8 triggers a conversion."]
200 PRSCH8 = 8,
201 #[doc = "9: PRS ch 9 triggers a conversion."]
202 PRSCH9 = 9,
203 #[doc = "10: PRS ch 10 triggers a conversion."]
204 PRSCH10 = 10,
205 #[doc = "11: PRS ch 11 triggers a conversion."]
206 PRSCH11 = 11,
207}
208impl From<PRSSEL_A> for u8 {
209 #[inline(always)]
210 fn from(variant: PRSSEL_A) -> Self {
211 variant as _
212 }
213}
214#[doc = "Reader of field `PRSSEL`"]
215pub type PRSSEL_R = crate::R<u8, PRSSEL_A>;
216impl PRSSEL_R {
217 #[doc = r"Get enumerated values variant"]
218 #[inline(always)]
219 pub fn variant(&self) -> crate::Variant<u8, PRSSEL_A> {
220 use crate::Variant::*;
221 match self.bits {
222 0 => Val(PRSSEL_A::PRSCH0),
223 1 => Val(PRSSEL_A::PRSCH1),
224 2 => Val(PRSSEL_A::PRSCH2),
225 3 => Val(PRSSEL_A::PRSCH3),
226 4 => Val(PRSSEL_A::PRSCH4),
227 5 => Val(PRSSEL_A::PRSCH5),
228 6 => Val(PRSSEL_A::PRSCH6),
229 7 => Val(PRSSEL_A::PRSCH7),
230 8 => Val(PRSSEL_A::PRSCH8),
231 9 => Val(PRSSEL_A::PRSCH9),
232 10 => Val(PRSSEL_A::PRSCH10),
233 11 => Val(PRSSEL_A::PRSCH11),
234 i => Res(i),
235 }
236 }
237 #[doc = "Checks if the value of the field is `PRSCH0`"]
238 #[inline(always)]
239 pub fn is_prsch0(&self) -> bool {
240 *self == PRSSEL_A::PRSCH0
241 }
242 #[doc = "Checks if the value of the field is `PRSCH1`"]
243 #[inline(always)]
244 pub fn is_prsch1(&self) -> bool {
245 *self == PRSSEL_A::PRSCH1
246 }
247 #[doc = "Checks if the value of the field is `PRSCH2`"]
248 #[inline(always)]
249 pub fn is_prsch2(&self) -> bool {
250 *self == PRSSEL_A::PRSCH2
251 }
252 #[doc = "Checks if the value of the field is `PRSCH3`"]
253 #[inline(always)]
254 pub fn is_prsch3(&self) -> bool {
255 *self == PRSSEL_A::PRSCH3
256 }
257 #[doc = "Checks if the value of the field is `PRSCH4`"]
258 #[inline(always)]
259 pub fn is_prsch4(&self) -> bool {
260 *self == PRSSEL_A::PRSCH4
261 }
262 #[doc = "Checks if the value of the field is `PRSCH5`"]
263 #[inline(always)]
264 pub fn is_prsch5(&self) -> bool {
265 *self == PRSSEL_A::PRSCH5
266 }
267 #[doc = "Checks if the value of the field is `PRSCH6`"]
268 #[inline(always)]
269 pub fn is_prsch6(&self) -> bool {
270 *self == PRSSEL_A::PRSCH6
271 }
272 #[doc = "Checks if the value of the field is `PRSCH7`"]
273 #[inline(always)]
274 pub fn is_prsch7(&self) -> bool {
275 *self == PRSSEL_A::PRSCH7
276 }
277 #[doc = "Checks if the value of the field is `PRSCH8`"]
278 #[inline(always)]
279 pub fn is_prsch8(&self) -> bool {
280 *self == PRSSEL_A::PRSCH8
281 }
282 #[doc = "Checks if the value of the field is `PRSCH9`"]
283 #[inline(always)]
284 pub fn is_prsch9(&self) -> bool {
285 *self == PRSSEL_A::PRSCH9
286 }
287 #[doc = "Checks if the value of the field is `PRSCH10`"]
288 #[inline(always)]
289 pub fn is_prsch10(&self) -> bool {
290 *self == PRSSEL_A::PRSCH10
291 }
292 #[doc = "Checks if the value of the field is `PRSCH11`"]
293 #[inline(always)]
294 pub fn is_prsch11(&self) -> bool {
295 *self == PRSSEL_A::PRSCH11
296 }
297}
298#[doc = "Write proxy for field `PRSSEL`"]
299pub struct PRSSEL_W<'a> {
300 w: &'a mut W,
301}
302impl<'a> PRSSEL_W<'a> {
303 #[doc = r"Writes `variant` to the field"]
304 #[inline(always)]
305 pub fn variant(self, variant: PRSSEL_A) -> &'a mut W {
306 unsafe { self.bits(variant.into()) }
307 }
308 #[doc = "PRS ch 0 triggers a conversion."]
309 #[inline(always)]
310 pub fn prsch0(self) -> &'a mut W {
311 self.variant(PRSSEL_A::PRSCH0)
312 }
313 #[doc = "PRS ch 1 triggers a conversion."]
314 #[inline(always)]
315 pub fn prsch1(self) -> &'a mut W {
316 self.variant(PRSSEL_A::PRSCH1)
317 }
318 #[doc = "PRS ch 2 triggers a conversion."]
319 #[inline(always)]
320 pub fn prsch2(self) -> &'a mut W {
321 self.variant(PRSSEL_A::PRSCH2)
322 }
323 #[doc = "PRS ch 3 triggers a conversion."]
324 #[inline(always)]
325 pub fn prsch3(self) -> &'a mut W {
326 self.variant(PRSSEL_A::PRSCH3)
327 }
328 #[doc = "PRS ch 4 triggers a conversion."]
329 #[inline(always)]
330 pub fn prsch4(self) -> &'a mut W {
331 self.variant(PRSSEL_A::PRSCH4)
332 }
333 #[doc = "PRS ch 5 triggers a conversion."]
334 #[inline(always)]
335 pub fn prsch5(self) -> &'a mut W {
336 self.variant(PRSSEL_A::PRSCH5)
337 }
338 #[doc = "PRS ch 6 triggers a conversion."]
339 #[inline(always)]
340 pub fn prsch6(self) -> &'a mut W {
341 self.variant(PRSSEL_A::PRSCH6)
342 }
343 #[doc = "PRS ch 7 triggers a conversion."]
344 #[inline(always)]
345 pub fn prsch7(self) -> &'a mut W {
346 self.variant(PRSSEL_A::PRSCH7)
347 }
348 #[doc = "PRS ch 8 triggers a conversion."]
349 #[inline(always)]
350 pub fn prsch8(self) -> &'a mut W {
351 self.variant(PRSSEL_A::PRSCH8)
352 }
353 #[doc = "PRS ch 9 triggers a conversion."]
354 #[inline(always)]
355 pub fn prsch9(self) -> &'a mut W {
356 self.variant(PRSSEL_A::PRSCH9)
357 }
358 #[doc = "PRS ch 10 triggers a conversion."]
359 #[inline(always)]
360 pub fn prsch10(self) -> &'a mut W {
361 self.variant(PRSSEL_A::PRSCH10)
362 }
363 #[doc = "PRS ch 11 triggers a conversion."]
364 #[inline(always)]
365 pub fn prsch11(self) -> &'a mut W {
366 self.variant(PRSSEL_A::PRSCH11)
367 }
368 #[doc = r"Writes raw bits to the field"]
369 #[inline(always)]
370 pub unsafe fn bits(self, value: u8) -> &'a mut W {
371 self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
372 self.w
373 }
374}
375impl R {
376 #[doc = "Bit 0 - Conversion Mode"]
377 #[inline(always)]
378 pub fn convmode(&self) -> CONVMODE_R {
379 CONVMODE_R::new((self.bits & 0x01) != 0)
380 }
381 #[doc = "Bits 4:6 - Channel 0 Trigger Mode"]
382 #[inline(always)]
383 pub fn trigmode(&self) -> TRIGMODE_R {
384 TRIGMODE_R::new(((self.bits >> 4) & 0x07) as u8)
385 }
386 #[doc = "Bit 8 - Channel 0 PRS Asynchronous Enable"]
387 #[inline(always)]
388 pub fn prsasync(&self) -> PRSASYNC_R {
389 PRSASYNC_R::new(((self.bits >> 8) & 0x01) != 0)
390 }
391 #[doc = "Bits 12:15 - Channel 0 PRS Trigger Select"]
392 #[inline(always)]
393 pub fn prssel(&self) -> PRSSEL_R {
394 PRSSEL_R::new(((self.bits >> 12) & 0x0f) as u8)
395 }
396}
397impl W {
398 #[doc = "Bit 0 - Conversion Mode"]
399 #[inline(always)]
400 pub fn convmode(&mut self) -> CONVMODE_W {
401 CONVMODE_W { w: self }
402 }
403 #[doc = "Bits 4:6 - Channel 0 Trigger Mode"]
404 #[inline(always)]
405 pub fn trigmode(&mut self) -> TRIGMODE_W {
406 TRIGMODE_W { w: self }
407 }
408 #[doc = "Bit 8 - Channel 0 PRS Asynchronous Enable"]
409 #[inline(always)]
410 pub fn prsasync(&mut self) -> PRSASYNC_W {
411 PRSASYNC_W { w: self }
412 }
413 #[doc = "Bits 12:15 - Channel 0 PRS Trigger Select"]
414 #[inline(always)]
415 pub fn prssel(&mut self) -> PRSSEL_W {
416 PRSSEL_W { w: self }
417 }
418}