efm32pg12_pac/vdac0/
ctrl.rs

1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIFF`"]
14pub type DIFF_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DIFF`"]
16pub struct DIFF_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DIFF_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `SINEMODE`"]
38pub type SINEMODE_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `SINEMODE`"]
40pub struct SINEMODE_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> SINEMODE_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
58        self.w
59    }
60}
61#[doc = "Reader of field `OUTENPRS`"]
62pub type OUTENPRS_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `OUTENPRS`"]
64pub struct OUTENPRS_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> OUTENPRS_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
82        self.w
83    }
84}
85#[doc = "Reader of field `CH0PRESCRST`"]
86pub type CH0PRESCRST_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `CH0PRESCRST`"]
88pub struct CH0PRESCRST_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> CH0PRESCRST_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
106        self.w
107    }
108}
109#[doc = "Reference Selection\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq)]
111#[repr(u8)]
112pub enum REFSEL_A {
113    #[doc = "0: Internal low noise 1.25 V bandgap reference"]
114    _1V25LN = 0,
115    #[doc = "1: Internal low noise 2.5 V bandgap reference"]
116    _2V5LN = 1,
117    #[doc = "2: Internal 1.25 V bandgap reference"]
118    _1V25 = 2,
119    #[doc = "3: Internal 2.5 V bandgap reference"]
120    _2V5 = 3,
121    #[doc = "4: AVDD reference"]
122    VDD = 4,
123    #[doc = "6: External pin reference"]
124    EXT = 6,
125}
126impl From<REFSEL_A> for u8 {
127    #[inline(always)]
128    fn from(variant: REFSEL_A) -> Self {
129        variant as _
130    }
131}
132#[doc = "Reader of field `REFSEL`"]
133pub type REFSEL_R = crate::R<u8, REFSEL_A>;
134impl REFSEL_R {
135    #[doc = r"Get enumerated values variant"]
136    #[inline(always)]
137    pub fn variant(&self) -> crate::Variant<u8, REFSEL_A> {
138        use crate::Variant::*;
139        match self.bits {
140            0 => Val(REFSEL_A::_1V25LN),
141            1 => Val(REFSEL_A::_2V5LN),
142            2 => Val(REFSEL_A::_1V25),
143            3 => Val(REFSEL_A::_2V5),
144            4 => Val(REFSEL_A::VDD),
145            6 => Val(REFSEL_A::EXT),
146            i => Res(i),
147        }
148    }
149    #[doc = "Checks if the value of the field is `_1V25LN`"]
150    #[inline(always)]
151    pub fn is_1v25ln(&self) -> bool {
152        *self == REFSEL_A::_1V25LN
153    }
154    #[doc = "Checks if the value of the field is `_2V5LN`"]
155    #[inline(always)]
156    pub fn is_2v5ln(&self) -> bool {
157        *self == REFSEL_A::_2V5LN
158    }
159    #[doc = "Checks if the value of the field is `_1V25`"]
160    #[inline(always)]
161    pub fn is_1v25(&self) -> bool {
162        *self == REFSEL_A::_1V25
163    }
164    #[doc = "Checks if the value of the field is `_2V5`"]
165    #[inline(always)]
166    pub fn is_2v5(&self) -> bool {
167        *self == REFSEL_A::_2V5
168    }
169    #[doc = "Checks if the value of the field is `VDD`"]
170    #[inline(always)]
171    pub fn is_vdd(&self) -> bool {
172        *self == REFSEL_A::VDD
173    }
174    #[doc = "Checks if the value of the field is `EXT`"]
175    #[inline(always)]
176    pub fn is_ext(&self) -> bool {
177        *self == REFSEL_A::EXT
178    }
179}
180#[doc = "Write proxy for field `REFSEL`"]
181pub struct REFSEL_W<'a> {
182    w: &'a mut W,
183}
184impl<'a> REFSEL_W<'a> {
185    #[doc = r"Writes `variant` to the field"]
186    #[inline(always)]
187    pub fn variant(self, variant: REFSEL_A) -> &'a mut W {
188        unsafe { self.bits(variant.into()) }
189    }
190    #[doc = "Internal low noise 1.25 V bandgap reference"]
191    #[inline(always)]
192    pub fn _1v25ln(self) -> &'a mut W {
193        self.variant(REFSEL_A::_1V25LN)
194    }
195    #[doc = "Internal low noise 2.5 V bandgap reference"]
196    #[inline(always)]
197    pub fn _2v5ln(self) -> &'a mut W {
198        self.variant(REFSEL_A::_2V5LN)
199    }
200    #[doc = "Internal 1.25 V bandgap reference"]
201    #[inline(always)]
202    pub fn _1v25(self) -> &'a mut W {
203        self.variant(REFSEL_A::_1V25)
204    }
205    #[doc = "Internal 2.5 V bandgap reference"]
206    #[inline(always)]
207    pub fn _2v5(self) -> &'a mut W {
208        self.variant(REFSEL_A::_2V5)
209    }
210    #[doc = "AVDD reference"]
211    #[inline(always)]
212    pub fn vdd(self) -> &'a mut W {
213        self.variant(REFSEL_A::VDD)
214    }
215    #[doc = "External pin reference"]
216    #[inline(always)]
217    pub fn ext(self) -> &'a mut W {
218        self.variant(REFSEL_A::EXT)
219    }
220    #[doc = r"Writes raw bits to the field"]
221    #[inline(always)]
222    pub unsafe fn bits(self, value: u8) -> &'a mut W {
223        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
224        self.w
225    }
226}
227#[doc = "Prescaler Setting for DAC Clock\n\nValue on reset: 0"]
228#[derive(Clone, Copy, Debug, PartialEq)]
229#[repr(u8)]
230pub enum PRESC_A {
231    #[doc = "0: `0`"]
232    NODIVISION = 0,
233}
234impl From<PRESC_A> for u8 {
235    #[inline(always)]
236    fn from(variant: PRESC_A) -> Self {
237        variant as _
238    }
239}
240#[doc = "Reader of field `PRESC`"]
241pub type PRESC_R = crate::R<u8, PRESC_A>;
242impl PRESC_R {
243    #[doc = r"Get enumerated values variant"]
244    #[inline(always)]
245    pub fn variant(&self) -> crate::Variant<u8, PRESC_A> {
246        use crate::Variant::*;
247        match self.bits {
248            0 => Val(PRESC_A::NODIVISION),
249            i => Res(i),
250        }
251    }
252    #[doc = "Checks if the value of the field is `NODIVISION`"]
253    #[inline(always)]
254    pub fn is_nodivision(&self) -> bool {
255        *self == PRESC_A::NODIVISION
256    }
257}
258#[doc = "Write proxy for field `PRESC`"]
259pub struct PRESC_W<'a> {
260    w: &'a mut W,
261}
262impl<'a> PRESC_W<'a> {
263    #[doc = r"Writes `variant` to the field"]
264    #[inline(always)]
265    pub fn variant(self, variant: PRESC_A) -> &'a mut W {
266        unsafe { self.bits(variant.into()) }
267    }
268    #[doc = "`0`"]
269    #[inline(always)]
270    pub fn nodivision(self) -> &'a mut W {
271        self.variant(PRESC_A::NODIVISION)
272    }
273    #[doc = r"Writes raw bits to the field"]
274    #[inline(always)]
275    pub unsafe fn bits(self, value: u8) -> &'a mut W {
276        self.w.bits = (self.w.bits & !(0x7f << 16)) | (((value as u32) & 0x7f) << 16);
277        self.w
278    }
279}
280#[doc = "Refresh Period\n\nValue on reset: 0"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282#[repr(u8)]
283pub enum REFRESHPERIOD_A {
284    #[doc = "0: All channels with enabled refresh are refreshed every 8 DAC_CLK cycles"]
285    _8CYCLES = 0,
286    #[doc = "1: All channels with enabled refresh are refreshed every 16 DAC_CLK cycles"]
287    _16CYCLES = 1,
288    #[doc = "2: All channels with enabled refresh are refreshed every 32 DAC_CLK cycles"]
289    _32CYCLES = 2,
290    #[doc = "3: All channels with enabled refresh are refreshed every 64 DAC_CLK cycles"]
291    _64CYCLES = 3,
292}
293impl From<REFRESHPERIOD_A> for u8 {
294    #[inline(always)]
295    fn from(variant: REFRESHPERIOD_A) -> Self {
296        variant as _
297    }
298}
299#[doc = "Reader of field `REFRESHPERIOD`"]
300pub type REFRESHPERIOD_R = crate::R<u8, REFRESHPERIOD_A>;
301impl REFRESHPERIOD_R {
302    #[doc = r"Get enumerated values variant"]
303    #[inline(always)]
304    pub fn variant(&self) -> REFRESHPERIOD_A {
305        match self.bits {
306            0 => REFRESHPERIOD_A::_8CYCLES,
307            1 => REFRESHPERIOD_A::_16CYCLES,
308            2 => REFRESHPERIOD_A::_32CYCLES,
309            3 => REFRESHPERIOD_A::_64CYCLES,
310            _ => unreachable!(),
311        }
312    }
313    #[doc = "Checks if the value of the field is `_8CYCLES`"]
314    #[inline(always)]
315    pub fn is_8cycles(&self) -> bool {
316        *self == REFRESHPERIOD_A::_8CYCLES
317    }
318    #[doc = "Checks if the value of the field is `_16CYCLES`"]
319    #[inline(always)]
320    pub fn is_16cycles(&self) -> bool {
321        *self == REFRESHPERIOD_A::_16CYCLES
322    }
323    #[doc = "Checks if the value of the field is `_32CYCLES`"]
324    #[inline(always)]
325    pub fn is_32cycles(&self) -> bool {
326        *self == REFRESHPERIOD_A::_32CYCLES
327    }
328    #[doc = "Checks if the value of the field is `_64CYCLES`"]
329    #[inline(always)]
330    pub fn is_64cycles(&self) -> bool {
331        *self == REFRESHPERIOD_A::_64CYCLES
332    }
333}
334#[doc = "Write proxy for field `REFRESHPERIOD`"]
335pub struct REFRESHPERIOD_W<'a> {
336    w: &'a mut W,
337}
338impl<'a> REFRESHPERIOD_W<'a> {
339    #[doc = r"Writes `variant` to the field"]
340    #[inline(always)]
341    pub fn variant(self, variant: REFRESHPERIOD_A) -> &'a mut W {
342        {
343            self.bits(variant.into())
344        }
345    }
346    #[doc = "All channels with enabled refresh are refreshed every 8 DAC_CLK cycles"]
347    #[inline(always)]
348    pub fn _8cycles(self) -> &'a mut W {
349        self.variant(REFRESHPERIOD_A::_8CYCLES)
350    }
351    #[doc = "All channels with enabled refresh are refreshed every 16 DAC_CLK cycles"]
352    #[inline(always)]
353    pub fn _16cycles(self) -> &'a mut W {
354        self.variant(REFRESHPERIOD_A::_16CYCLES)
355    }
356    #[doc = "All channels with enabled refresh are refreshed every 32 DAC_CLK cycles"]
357    #[inline(always)]
358    pub fn _32cycles(self) -> &'a mut W {
359        self.variant(REFRESHPERIOD_A::_32CYCLES)
360    }
361    #[doc = "All channels with enabled refresh are refreshed every 64 DAC_CLK cycles"]
362    #[inline(always)]
363    pub fn _64cycles(self) -> &'a mut W {
364        self.variant(REFRESHPERIOD_A::_64CYCLES)
365    }
366    #[doc = r"Writes raw bits to the field"]
367    #[inline(always)]
368    pub fn bits(self, value: u8) -> &'a mut W {
369        self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
370        self.w
371    }
372}
373#[doc = "Reader of field `WARMUPMODE`"]
374pub type WARMUPMODE_R = crate::R<bool, bool>;
375#[doc = "Write proxy for field `WARMUPMODE`"]
376pub struct WARMUPMODE_W<'a> {
377    w: &'a mut W,
378}
379impl<'a> WARMUPMODE_W<'a> {
380    #[doc = r"Sets the field bit"]
381    #[inline(always)]
382    pub fn set_bit(self) -> &'a mut W {
383        self.bit(true)
384    }
385    #[doc = r"Clears the field bit"]
386    #[inline(always)]
387    pub fn clear_bit(self) -> &'a mut W {
388        self.bit(false)
389    }
390    #[doc = r"Writes raw bits to the field"]
391    #[inline(always)]
392    pub fn bit(self, value: bool) -> &'a mut W {
393        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
394        self.w
395    }
396}
397#[doc = "Reader of field `DACCLKMODE`"]
398pub type DACCLKMODE_R = crate::R<bool, bool>;
399#[doc = "Write proxy for field `DACCLKMODE`"]
400pub struct DACCLKMODE_W<'a> {
401    w: &'a mut W,
402}
403impl<'a> DACCLKMODE_W<'a> {
404    #[doc = r"Sets the field bit"]
405    #[inline(always)]
406    pub fn set_bit(self) -> &'a mut W {
407        self.bit(true)
408    }
409    #[doc = r"Clears the field bit"]
410    #[inline(always)]
411    pub fn clear_bit(self) -> &'a mut W {
412        self.bit(false)
413    }
414    #[doc = r"Writes raw bits to the field"]
415    #[inline(always)]
416    pub fn bit(self, value: bool) -> &'a mut W {
417        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
418        self.w
419    }
420}
421impl R {
422    #[doc = "Bit 0 - Differential Mode"]
423    #[inline(always)]
424    pub fn diff(&self) -> DIFF_R {
425        DIFF_R::new((self.bits & 0x01) != 0)
426    }
427    #[doc = "Bit 4 - Sine Mode"]
428    #[inline(always)]
429    pub fn sinemode(&self) -> SINEMODE_R {
430        SINEMODE_R::new(((self.bits >> 4) & 0x01) != 0)
431    }
432    #[doc = "Bit 5 - PRS Controlled Output Enable"]
433    #[inline(always)]
434    pub fn outenprs(&self) -> OUTENPRS_R {
435        OUTENPRS_R::new(((self.bits >> 5) & 0x01) != 0)
436    }
437    #[doc = "Bit 6 - Channel 0 Start Reset Prescaler"]
438    #[inline(always)]
439    pub fn ch0prescrst(&self) -> CH0PRESCRST_R {
440        CH0PRESCRST_R::new(((self.bits >> 6) & 0x01) != 0)
441    }
442    #[doc = "Bits 8:10 - Reference Selection"]
443    #[inline(always)]
444    pub fn refsel(&self) -> REFSEL_R {
445        REFSEL_R::new(((self.bits >> 8) & 0x07) as u8)
446    }
447    #[doc = "Bits 16:22 - Prescaler Setting for DAC Clock"]
448    #[inline(always)]
449    pub fn presc(&self) -> PRESC_R {
450        PRESC_R::new(((self.bits >> 16) & 0x7f) as u8)
451    }
452    #[doc = "Bits 24:25 - Refresh Period"]
453    #[inline(always)]
454    pub fn refreshperiod(&self) -> REFRESHPERIOD_R {
455        REFRESHPERIOD_R::new(((self.bits >> 24) & 0x03) as u8)
456    }
457    #[doc = "Bit 28 - Warm-up Mode"]
458    #[inline(always)]
459    pub fn warmupmode(&self) -> WARMUPMODE_R {
460        WARMUPMODE_R::new(((self.bits >> 28) & 0x01) != 0)
461    }
462    #[doc = "Bit 31 - Clock Mode"]
463    #[inline(always)]
464    pub fn dacclkmode(&self) -> DACCLKMODE_R {
465        DACCLKMODE_R::new(((self.bits >> 31) & 0x01) != 0)
466    }
467}
468impl W {
469    #[doc = "Bit 0 - Differential Mode"]
470    #[inline(always)]
471    pub fn diff(&mut self) -> DIFF_W {
472        DIFF_W { w: self }
473    }
474    #[doc = "Bit 4 - Sine Mode"]
475    #[inline(always)]
476    pub fn sinemode(&mut self) -> SINEMODE_W {
477        SINEMODE_W { w: self }
478    }
479    #[doc = "Bit 5 - PRS Controlled Output Enable"]
480    #[inline(always)]
481    pub fn outenprs(&mut self) -> OUTENPRS_W {
482        OUTENPRS_W { w: self }
483    }
484    #[doc = "Bit 6 - Channel 0 Start Reset Prescaler"]
485    #[inline(always)]
486    pub fn ch0prescrst(&mut self) -> CH0PRESCRST_W {
487        CH0PRESCRST_W { w: self }
488    }
489    #[doc = "Bits 8:10 - Reference Selection"]
490    #[inline(always)]
491    pub fn refsel(&mut self) -> REFSEL_W {
492        REFSEL_W { w: self }
493    }
494    #[doc = "Bits 16:22 - Prescaler Setting for DAC Clock"]
495    #[inline(always)]
496    pub fn presc(&mut self) -> PRESC_W {
497        PRESC_W { w: self }
498    }
499    #[doc = "Bits 24:25 - Refresh Period"]
500    #[inline(always)]
501    pub fn refreshperiod(&mut self) -> REFRESHPERIOD_W {
502        REFRESHPERIOD_W { w: self }
503    }
504    #[doc = "Bit 28 - Warm-up Mode"]
505    #[inline(always)]
506    pub fn warmupmode(&mut self) -> WARMUPMODE_W {
507        WARMUPMODE_W { w: self }
508    }
509    #[doc = "Bit 31 - Clock Mode"]
510    #[inline(always)]
511    pub fn dacclkmode(&mut self) -> DACCLKMODE_W {
512        DACCLKMODE_W { w: self }
513    }
514}
efm32pg12_pac/vdac0/ctrl.rs

efm32pg12_pac/vdac0/
ctrl.rs
