efm32pg12_pac/cmu/
hfbusclken0.rs

1#[doc = "Reader of register HFBUSCLKEN0"]
2pub type R = crate::R<u32, super::HFBUSCLKEN0>;
3#[doc = "Writer for register HFBUSCLKEN0"]
4pub type W = crate::W<u32, super::HFBUSCLKEN0>;
5#[doc = "Register HFBUSCLKEN0 `reset()`'s with value 0"]
6impl crate::ResetValue for super::HFBUSCLKEN0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CRYPTO0`"]
14pub type CRYPTO0_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `CRYPTO0`"]
16pub struct CRYPTO0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CRYPTO0_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `CRYPTO1`"]
38pub type CRYPTO1_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `CRYPTO1`"]
40pub struct CRYPTO1_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> CRYPTO1_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `LE`"]
62pub type LE_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `LE`"]
64pub struct LE_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> LE_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `GPIO`"]
86pub type GPIO_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `GPIO`"]
88pub struct GPIO_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> GPIO_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `PRS`"]
110pub type PRS_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `PRS`"]
112pub struct PRS_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> PRS_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133#[doc = "Reader of field `LDMA`"]
134pub type LDMA_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `LDMA`"]
136pub struct LDMA_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> LDMA_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154        self.w
155    }
156}
157#[doc = "Reader of field `GPCRC`"]
158pub type GPCRC_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `GPCRC`"]
160pub struct GPCRC_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> GPCRC_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
178        self.w
179    }
180}
181impl R {
182    #[doc = "Bit 0 - Advanced Encryption Standard Accelerator 0 Clock Enable"]
183    #[inline(always)]
184    pub fn crypto0(&self) -> CRYPTO0_R {
185        CRYPTO0_R::new((self.bits & 0x01) != 0)
186    }
187    #[doc = "Bit 1 - Advanced Encryption Standard Accelerator 1 Clock Enable"]
188    #[inline(always)]
189    pub fn crypto1(&self) -> CRYPTO1_R {
190        CRYPTO1_R::new(((self.bits >> 1) & 0x01) != 0)
191    }
192    #[doc = "Bit 2 - Low Energy Peripheral Interface Clock Enable"]
193    #[inline(always)]
194    pub fn le(&self) -> LE_R {
195        LE_R::new(((self.bits >> 2) & 0x01) != 0)
196    }
197    #[doc = "Bit 3 - General purpose Input/Output Clock Enable"]
198    #[inline(always)]
199    pub fn gpio(&self) -> GPIO_R {
200        GPIO_R::new(((self.bits >> 3) & 0x01) != 0)
201    }
202    #[doc = "Bit 4 - Peripheral Reflex System Clock Enable"]
203    #[inline(always)]
204    pub fn prs(&self) -> PRS_R {
205        PRS_R::new(((self.bits >> 4) & 0x01) != 0)
206    }
207    #[doc = "Bit 5 - Linked Direct Memory Access Controller Clock Enable"]
208    #[inline(always)]
209    pub fn ldma(&self) -> LDMA_R {
210        LDMA_R::new(((self.bits >> 5) & 0x01) != 0)
211    }
212    #[doc = "Bit 6 - General Purpose CRC Clock Enable"]
213    #[inline(always)]
214    pub fn gpcrc(&self) -> GPCRC_R {
215        GPCRC_R::new(((self.bits >> 6) & 0x01) != 0)
216    }
217}
218impl W {
219    #[doc = "Bit 0 - Advanced Encryption Standard Accelerator 0 Clock Enable"]
220    #[inline(always)]
221    pub fn crypto0(&mut self) -> CRYPTO0_W {
222        CRYPTO0_W { w: self }
223    }
224    #[doc = "Bit 1 - Advanced Encryption Standard Accelerator 1 Clock Enable"]
225    #[inline(always)]
226    pub fn crypto1(&mut self) -> CRYPTO1_W {
227        CRYPTO1_W { w: self }
228    }
229    #[doc = "Bit 2 - Low Energy Peripheral Interface Clock Enable"]
230    #[inline(always)]
231    pub fn le(&mut self) -> LE_W {
232        LE_W { w: self }
233    }
234    #[doc = "Bit 3 - General purpose Input/Output Clock Enable"]
235    #[inline(always)]
236    pub fn gpio(&mut self) -> GPIO_W {
237        GPIO_W { w: self }
238    }
239    #[doc = "Bit 4 - Peripheral Reflex System Clock Enable"]
240    #[inline(always)]
241    pub fn prs(&mut self) -> PRS_W {
242        PRS_W { w: self }
243    }
244    #[doc = "Bit 5 - Linked Direct Memory Access Controller Clock Enable"]
245    #[inline(always)]
246    pub fn ldma(&mut self) -> LDMA_W {
247        LDMA_W { w: self }
248    }
249    #[doc = "Bit 6 - General Purpose CRC Clock Enable"]
250    #[inline(always)]
251    pub fn gpcrc(&mut self) -> GPCRC_W {
252        GPCRC_W { w: self }
253    }
254}
efm32pg12_pac/cmu/hfbusclken0.rs

efm32pg12_pac/cmu/
hfbusclken0.rs
