efm32pg12_pac/lesense/
perctrl.rs

1#[doc = "Reader of register PERCTRL"]
2pub type R = crate::R<u32, super::PERCTRL>;
3#[doc = "Writer for register PERCTRL"]
4pub type W = crate::W<u32, super::PERCTRL>;
5#[doc = "Register PERCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::PERCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DACCH0EN`"]
14pub type DACCH0EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DACCH0EN`"]
16pub struct DACCH0EN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DACCH0EN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `DACCH1EN`"]
38pub type DACCH1EN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DACCH1EN`"]
40pub struct DACCH1EN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> DACCH1EN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `DACCH0DATA`"]
62pub type DACCH0DATA_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `DACCH0DATA`"]
64pub struct DACCH0DATA_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> DACCH0DATA_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `DACCH1DATA`"]
86pub type DACCH1DATA_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DACCH1DATA`"]
88pub struct DACCH1DATA_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DACCH1DATA_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `DACSTARTUP`"]
110pub type DACSTARTUP_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `DACSTARTUP`"]
112pub struct DACSTARTUP_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> DACSTARTUP_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
130        self.w
131    }
132}
133#[doc = "Reader of field `DACCONVTRIG`"]
134pub type DACCONVTRIG_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `DACCONVTRIG`"]
136pub struct DACCONVTRIG_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> DACCONVTRIG_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
154        self.w
155    }
156}
157#[doc = "ACMP0 Mode\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq)]
159#[repr(u8)]
160pub enum ACMP0MODE_A {
161    #[doc = "0: LESENSE does not control ACMP0"]
162    DISABLE = 0,
163    #[doc = "1: LESENSE controls the input mux (POSSEL) of ACMP0"]
164    MUX = 1,
165    #[doc = "2: LESENSE controls the input mux (POSSEL) and the threshold value (VDDLEVEL) of ACMP0"]
166    MUXTHRES = 2,
167}
168impl From<ACMP0MODE_A> for u8 {
169    #[inline(always)]
170    fn from(variant: ACMP0MODE_A) -> Self {
171        variant as _
172    }
173}
174#[doc = "Reader of field `ACMP0MODE`"]
175pub type ACMP0MODE_R = crate::R<u8, ACMP0MODE_A>;
176impl ACMP0MODE_R {
177    #[doc = r"Get enumerated values variant"]
178    #[inline(always)]
179    pub fn variant(&self) -> crate::Variant<u8, ACMP0MODE_A> {
180        use crate::Variant::*;
181        match self.bits {
182            0 => Val(ACMP0MODE_A::DISABLE),
183            1 => Val(ACMP0MODE_A::MUX),
184            2 => Val(ACMP0MODE_A::MUXTHRES),
185            i => Res(i),
186        }
187    }
188    #[doc = "Checks if the value of the field is `DISABLE`"]
189    #[inline(always)]
190    pub fn is_disable(&self) -> bool {
191        *self == ACMP0MODE_A::DISABLE
192    }
193    #[doc = "Checks if the value of the field is `MUX`"]
194    #[inline(always)]
195    pub fn is_mux(&self) -> bool {
196        *self == ACMP0MODE_A::MUX
197    }
198    #[doc = "Checks if the value of the field is `MUXTHRES`"]
199    #[inline(always)]
200    pub fn is_muxthres(&self) -> bool {
201        *self == ACMP0MODE_A::MUXTHRES
202    }
203}
204#[doc = "Write proxy for field `ACMP0MODE`"]
205pub struct ACMP0MODE_W<'a> {
206    w: &'a mut W,
207}
208impl<'a> ACMP0MODE_W<'a> {
209    #[doc = r"Writes `variant` to the field"]
210    #[inline(always)]
211    pub fn variant(self, variant: ACMP0MODE_A) -> &'a mut W {
212        unsafe { self.bits(variant.into()) }
213    }
214    #[doc = "LESENSE does not control ACMP0"]
215    #[inline(always)]
216    pub fn disable(self) -> &'a mut W {
217        self.variant(ACMP0MODE_A::DISABLE)
218    }
219    #[doc = "LESENSE controls the input mux (POSSEL) of ACMP0"]
220    #[inline(always)]
221    pub fn mux(self) -> &'a mut W {
222        self.variant(ACMP0MODE_A::MUX)
223    }
224    #[doc = "LESENSE controls the input mux (POSSEL) and the threshold value (VDDLEVEL) of ACMP0"]
225    #[inline(always)]
226    pub fn muxthres(self) -> &'a mut W {
227        self.variant(ACMP0MODE_A::MUXTHRES)
228    }
229    #[doc = r"Writes raw bits to the field"]
230    #[inline(always)]
231    pub unsafe fn bits(self, value: u8) -> &'a mut W {
232        self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
233        self.w
234    }
235}
236#[doc = "ACMP1 Mode\n\nValue on reset: 0"]
237#[derive(Clone, Copy, Debug, PartialEq)]
238#[repr(u8)]
239pub enum ACMP1MODE_A {
240    #[doc = "0: LESENSE does not control ACMP1"]
241    DISABLE = 0,
242    #[doc = "1: LESENSE controls the input mux (POSSEL) of ACMP1"]
243    MUX = 1,
244    #[doc = "2: LESENSE controls the input mux and the threshold value (VDDLEVEL) of ACMP1"]
245    MUXTHRES = 2,
246}
247impl From<ACMP1MODE_A> for u8 {
248    #[inline(always)]
249    fn from(variant: ACMP1MODE_A) -> Self {
250        variant as _
251    }
252}
253#[doc = "Reader of field `ACMP1MODE`"]
254pub type ACMP1MODE_R = crate::R<u8, ACMP1MODE_A>;
255impl ACMP1MODE_R {
256    #[doc = r"Get enumerated values variant"]
257    #[inline(always)]
258    pub fn variant(&self) -> crate::Variant<u8, ACMP1MODE_A> {
259        use crate::Variant::*;
260        match self.bits {
261            0 => Val(ACMP1MODE_A::DISABLE),
262            1 => Val(ACMP1MODE_A::MUX),
263            2 => Val(ACMP1MODE_A::MUXTHRES),
264            i => Res(i),
265        }
266    }
267    #[doc = "Checks if the value of the field is `DISABLE`"]
268    #[inline(always)]
269    pub fn is_disable(&self) -> bool {
270        *self == ACMP1MODE_A::DISABLE
271    }
272    #[doc = "Checks if the value of the field is `MUX`"]
273    #[inline(always)]
274    pub fn is_mux(&self) -> bool {
275        *self == ACMP1MODE_A::MUX
276    }
277    #[doc = "Checks if the value of the field is `MUXTHRES`"]
278    #[inline(always)]
279    pub fn is_muxthres(&self) -> bool {
280        *self == ACMP1MODE_A::MUXTHRES
281    }
282}
283#[doc = "Write proxy for field `ACMP1MODE`"]
284pub struct ACMP1MODE_W<'a> {
285    w: &'a mut W,
286}
287impl<'a> ACMP1MODE_W<'a> {
288    #[doc = r"Writes `variant` to the field"]
289    #[inline(always)]
290    pub fn variant(self, variant: ACMP1MODE_A) -> &'a mut W {
291        unsafe { self.bits(variant.into()) }
292    }
293    #[doc = "LESENSE does not control ACMP1"]
294    #[inline(always)]
295    pub fn disable(self) -> &'a mut W {
296        self.variant(ACMP1MODE_A::DISABLE)
297    }
298    #[doc = "LESENSE controls the input mux (POSSEL) of ACMP1"]
299    #[inline(always)]
300    pub fn mux(self) -> &'a mut W {
301        self.variant(ACMP1MODE_A::MUX)
302    }
303    #[doc = "LESENSE controls the input mux and the threshold value (VDDLEVEL) of ACMP1"]
304    #[inline(always)]
305    pub fn muxthres(self) -> &'a mut W {
306        self.variant(ACMP1MODE_A::MUXTHRES)
307    }
308    #[doc = r"Writes raw bits to the field"]
309    #[inline(always)]
310    pub unsafe fn bits(self, value: u8) -> &'a mut W {
311        self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
312        self.w
313    }
314}
315#[doc = "Reader of field `ACMP0INV`"]
316pub type ACMP0INV_R = crate::R<bool, bool>;
317#[doc = "Write proxy for field `ACMP0INV`"]
318pub struct ACMP0INV_W<'a> {
319    w: &'a mut W,
320}
321impl<'a> ACMP0INV_W<'a> {
322    #[doc = r"Sets the field bit"]
323    #[inline(always)]
324    pub fn set_bit(self) -> &'a mut W {
325        self.bit(true)
326    }
327    #[doc = r"Clears the field bit"]
328    #[inline(always)]
329    pub fn clear_bit(self) -> &'a mut W {
330        self.bit(false)
331    }
332    #[doc = r"Writes raw bits to the field"]
333    #[inline(always)]
334    pub fn bit(self, value: bool) -> &'a mut W {
335        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
336        self.w
337    }
338}
339#[doc = "Reader of field `ACMP1INV`"]
340pub type ACMP1INV_R = crate::R<bool, bool>;
341#[doc = "Write proxy for field `ACMP1INV`"]
342pub struct ACMP1INV_W<'a> {
343    w: &'a mut W,
344}
345impl<'a> ACMP1INV_W<'a> {
346    #[doc = r"Sets the field bit"]
347    #[inline(always)]
348    pub fn set_bit(self) -> &'a mut W {
349        self.bit(true)
350    }
351    #[doc = r"Clears the field bit"]
352    #[inline(always)]
353    pub fn clear_bit(self) -> &'a mut W {
354        self.bit(false)
355    }
356    #[doc = r"Writes raw bits to the field"]
357    #[inline(always)]
358    pub fn bit(self, value: bool) -> &'a mut W {
359        self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
360        self.w
361    }
362}
363#[doc = "Reader of field `ACMP0HYSTEN`"]
364pub type ACMP0HYSTEN_R = crate::R<bool, bool>;
365#[doc = "Write proxy for field `ACMP0HYSTEN`"]
366pub struct ACMP0HYSTEN_W<'a> {
367    w: &'a mut W,
368}
369impl<'a> ACMP0HYSTEN_W<'a> {
370    #[doc = r"Sets the field bit"]
371    #[inline(always)]
372    pub fn set_bit(self) -> &'a mut W {
373        self.bit(true)
374    }
375    #[doc = r"Clears the field bit"]
376    #[inline(always)]
377    pub fn clear_bit(self) -> &'a mut W {
378        self.bit(false)
379    }
380    #[doc = r"Writes raw bits to the field"]
381    #[inline(always)]
382    pub fn bit(self, value: bool) -> &'a mut W {
383        self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
384        self.w
385    }
386}
387#[doc = "Reader of field `ACMP1HYSTEN`"]
388pub type ACMP1HYSTEN_R = crate::R<bool, bool>;
389#[doc = "Write proxy for field `ACMP1HYSTEN`"]
390pub struct ACMP1HYSTEN_W<'a> {
391    w: &'a mut W,
392}
393impl<'a> ACMP1HYSTEN_W<'a> {
394    #[doc = r"Sets the field bit"]
395    #[inline(always)]
396    pub fn set_bit(self) -> &'a mut W {
397        self.bit(true)
398    }
399    #[doc = r"Clears the field bit"]
400    #[inline(always)]
401    pub fn clear_bit(self) -> &'a mut W {
402        self.bit(false)
403    }
404    #[doc = r"Writes raw bits to the field"]
405    #[inline(always)]
406    pub fn bit(self, value: bool) -> &'a mut W {
407        self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
408        self.w
409    }
410}
411#[doc = "ACMP and VDAC Duty Cycle Mode\n\nValue on reset: 0"]
412#[derive(Clone, Copy, Debug, PartialEq)]
413#[repr(u8)]
414pub enum WARMUPMODE_A {
415    #[doc = "0: The analog comparators and VDAC are shut down when LESENSE is idle"]
416    NORMAL = 0,
417    #[doc = "1: The analog comparators are kept powered up when LESENSE is idle"]
418    KEEPACMPWARM = 1,
419    #[doc = "2: The VDAC is kept powered up when LESENSE is idle"]
420    KEEPDACWARM = 2,
421    #[doc = "3: The analog comparators and VDAC are kept powered up when LESENSE is idle"]
422    KEEPACMPDACWARM = 3,
423}
424impl From<WARMUPMODE_A> for u8 {
425    #[inline(always)]
426    fn from(variant: WARMUPMODE_A) -> Self {
427        variant as _
428    }
429}
430#[doc = "Reader of field `WARMUPMODE`"]
431pub type WARMUPMODE_R = crate::R<u8, WARMUPMODE_A>;
432impl WARMUPMODE_R {
433    #[doc = r"Get enumerated values variant"]
434    #[inline(always)]
435    pub fn variant(&self) -> WARMUPMODE_A {
436        match self.bits {
437            0 => WARMUPMODE_A::NORMAL,
438            1 => WARMUPMODE_A::KEEPACMPWARM,
439            2 => WARMUPMODE_A::KEEPDACWARM,
440            3 => WARMUPMODE_A::KEEPACMPDACWARM,
441            _ => unreachable!(),
442        }
443    }
444    #[doc = "Checks if the value of the field is `NORMAL`"]
445    #[inline(always)]
446    pub fn is_normal(&self) -> bool {
447        *self == WARMUPMODE_A::NORMAL
448    }
449    #[doc = "Checks if the value of the field is `KEEPACMPWARM`"]
450    #[inline(always)]
451    pub fn is_keepacmpwarm(&self) -> bool {
452        *self == WARMUPMODE_A::KEEPACMPWARM
453    }
454    #[doc = "Checks if the value of the field is `KEEPDACWARM`"]
455    #[inline(always)]
456    pub fn is_keepdacwarm(&self) -> bool {
457        *self == WARMUPMODE_A::KEEPDACWARM
458    }
459    #[doc = "Checks if the value of the field is `KEEPACMPDACWARM`"]
460    #[inline(always)]
461    pub fn is_keepacmpdacwarm(&self) -> bool {
462        *self == WARMUPMODE_A::KEEPACMPDACWARM
463    }
464}
465#[doc = "Write proxy for field `WARMUPMODE`"]
466pub struct WARMUPMODE_W<'a> {
467    w: &'a mut W,
468}
469impl<'a> WARMUPMODE_W<'a> {
470    #[doc = r"Writes `variant` to the field"]
471    #[inline(always)]
472    pub fn variant(self, variant: WARMUPMODE_A) -> &'a mut W {
473        {
474            self.bits(variant.into())
475        }
476    }
477    #[doc = "The analog comparators and VDAC are shut down when LESENSE is idle"]
478    #[inline(always)]
479    pub fn normal(self) -> &'a mut W {
480        self.variant(WARMUPMODE_A::NORMAL)
481    }
482    #[doc = "The analog comparators are kept powered up when LESENSE is idle"]
483    #[inline(always)]
484    pub fn keepacmpwarm(self) -> &'a mut W {
485        self.variant(WARMUPMODE_A::KEEPACMPWARM)
486    }
487    #[doc = "The VDAC is kept powered up when LESENSE is idle"]
488    #[inline(always)]
489    pub fn keepdacwarm(self) -> &'a mut W {
490        self.variant(WARMUPMODE_A::KEEPDACWARM)
491    }
492    #[doc = "The analog comparators and VDAC are kept powered up when LESENSE is idle"]
493    #[inline(always)]
494    pub fn keepacmpdacwarm(self) -> &'a mut W {
495        self.variant(WARMUPMODE_A::KEEPACMPDACWARM)
496    }
497    #[doc = r"Writes raw bits to the field"]
498    #[inline(always)]
499    pub fn bits(self, value: u8) -> &'a mut W {
500        self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
501        self.w
502    }
503}
504impl R {
505    #[doc = "Bit 0 - VDAC CH0 Enable"]
506    #[inline(always)]
507    pub fn dacch0en(&self) -> DACCH0EN_R {
508        DACCH0EN_R::new((self.bits & 0x01) != 0)
509    }
510    #[doc = "Bit 1 - VDAC CH1 Enable"]
511    #[inline(always)]
512    pub fn dacch1en(&self) -> DACCH1EN_R {
513        DACCH1EN_R::new(((self.bits >> 1) & 0x01) != 0)
514    }
515    #[doc = "Bit 2 - VDAC CH0 Data Selection"]
516    #[inline(always)]
517    pub fn dacch0data(&self) -> DACCH0DATA_R {
518        DACCH0DATA_R::new(((self.bits >> 2) & 0x01) != 0)
519    }
520    #[doc = "Bit 3 - VDAC CH1 Data Selection"]
521    #[inline(always)]
522    pub fn dacch1data(&self) -> DACCH1DATA_R {
523        DACCH1DATA_R::new(((self.bits >> 3) & 0x01) != 0)
524    }
525    #[doc = "Bit 6 - VDAC Startup Configuration"]
526    #[inline(always)]
527    pub fn dacstartup(&self) -> DACSTARTUP_R {
528        DACSTARTUP_R::new(((self.bits >> 6) & 0x01) != 0)
529    }
530    #[doc = "Bit 8 - VDAC Conversion Trigger Configuration"]
531    #[inline(always)]
532    pub fn dacconvtrig(&self) -> DACCONVTRIG_R {
533        DACCONVTRIG_R::new(((self.bits >> 8) & 0x01) != 0)
534    }
535    #[doc = "Bits 20:21 - ACMP0 Mode"]
536    #[inline(always)]
537    pub fn acmp0mode(&self) -> ACMP0MODE_R {
538        ACMP0MODE_R::new(((self.bits >> 20) & 0x03) as u8)
539    }
540    #[doc = "Bits 22:23 - ACMP1 Mode"]
541    #[inline(always)]
542    pub fn acmp1mode(&self) -> ACMP1MODE_R {
543        ACMP1MODE_R::new(((self.bits >> 22) & 0x03) as u8)
544    }
545    #[doc = "Bit 24 - Invert Analog Comparator 0 Output"]
546    #[inline(always)]
547    pub fn acmp0inv(&self) -> ACMP0INV_R {
548        ACMP0INV_R::new(((self.bits >> 24) & 0x01) != 0)
549    }
550    #[doc = "Bit 25 - Invert Analog Comparator 1 Output"]
551    #[inline(always)]
552    pub fn acmp1inv(&self) -> ACMP1INV_R {
553        ACMP1INV_R::new(((self.bits >> 25) & 0x01) != 0)
554    }
555    #[doc = "Bit 26 - ACMP0 Hysteresis Enable"]
556    #[inline(always)]
557    pub fn acmp0hysten(&self) -> ACMP0HYSTEN_R {
558        ACMP0HYSTEN_R::new(((self.bits >> 26) & 0x01) != 0)
559    }
560    #[doc = "Bit 27 - ACMP1 Hysteresis Enable"]
561    #[inline(always)]
562    pub fn acmp1hysten(&self) -> ACMP1HYSTEN_R {
563        ACMP1HYSTEN_R::new(((self.bits >> 27) & 0x01) != 0)
564    }
565    #[doc = "Bits 28:29 - ACMP and VDAC Duty Cycle Mode"]
566    #[inline(always)]
567    pub fn warmupmode(&self) -> WARMUPMODE_R {
568        WARMUPMODE_R::new(((self.bits >> 28) & 0x03) as u8)
569    }
570}
571impl W {
572    #[doc = "Bit 0 - VDAC CH0 Enable"]
573    #[inline(always)]
574    pub fn dacch0en(&mut self) -> DACCH0EN_W {
575        DACCH0EN_W { w: self }
576    }
577    #[doc = "Bit 1 - VDAC CH1 Enable"]
578    #[inline(always)]
579    pub fn dacch1en(&mut self) -> DACCH1EN_W {
580        DACCH1EN_W { w: self }
581    }
582    #[doc = "Bit 2 - VDAC CH0 Data Selection"]
583    #[inline(always)]
584    pub fn dacch0data(&mut self) -> DACCH0DATA_W {
585        DACCH0DATA_W { w: self }
586    }
587    #[doc = "Bit 3 - VDAC CH1 Data Selection"]
588    #[inline(always)]
589    pub fn dacch1data(&mut self) -> DACCH1DATA_W {
590        DACCH1DATA_W { w: self }
591    }
592    #[doc = "Bit 6 - VDAC Startup Configuration"]
593    #[inline(always)]
594    pub fn dacstartup(&mut self) -> DACSTARTUP_W {
595        DACSTARTUP_W { w: self }
596    }
597    #[doc = "Bit 8 - VDAC Conversion Trigger Configuration"]
598    #[inline(always)]
599    pub fn dacconvtrig(&mut self) -> DACCONVTRIG_W {
600        DACCONVTRIG_W { w: self }
601    }
602    #[doc = "Bits 20:21 - ACMP0 Mode"]
603    #[inline(always)]
604    pub fn acmp0mode(&mut self) -> ACMP0MODE_W {
605        ACMP0MODE_W { w: self }
606    }
607    #[doc = "Bits 22:23 - ACMP1 Mode"]
608    #[inline(always)]
609    pub fn acmp1mode(&mut self) -> ACMP1MODE_W {
610        ACMP1MODE_W { w: self }
611    }
612    #[doc = "Bit 24 - Invert Analog Comparator 0 Output"]
613    #[inline(always)]
614    pub fn acmp0inv(&mut self) -> ACMP0INV_W {
615        ACMP0INV_W { w: self }
616    }
617    #[doc = "Bit 25 - Invert Analog Comparator 1 Output"]
618    #[inline(always)]
619    pub fn acmp1inv(&mut self) -> ACMP1INV_W {
620        ACMP1INV_W { w: self }
621    }
622    #[doc = "Bit 26 - ACMP0 Hysteresis Enable"]
623    #[inline(always)]
624    pub fn acmp0hysten(&mut self) -> ACMP0HYSTEN_W {
625        ACMP0HYSTEN_W { w: self }
626    }
627    #[doc = "Bit 27 - ACMP1 Hysteresis Enable"]
628    #[inline(always)]
629    pub fn acmp1hysten(&mut self) -> ACMP1HYSTEN_W {
630        ACMP1HYSTEN_W { w: self }
631    }
632    #[doc = "Bits 28:29 - ACMP and VDAC Duty Cycle Mode"]
633    #[inline(always)]
634    pub fn warmupmode(&mut self) -> WARMUPMODE_W {
635        WARMUPMODE_W { w: self }
636    }
637}
efm32pg12_pac/lesense/perctrl.rs

efm32pg12_pac/lesense/
perctrl.rs
