1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0x001f_0000"]
6impl crate::ResetValue for super::CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x001f_0000
11 }
12}
13#[doc = "Warm-up Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum WARMUPMODE_A {
17 #[doc = "0: ADC is shut down after each conversion. 5us warmup time is used before each conversion."]
18 NORMAL = 0,
19 #[doc = "1: ADC is kept in standby mode between conversions. 1us warmup time is used before each conversion."]
20 KEEPINSTANDBY = 1,
21 #[doc = "2: ADC is kept in slow acquisition mode between conversions. 1us warmup time is used before each conversion."]
22 KEEPINSLOWACC = 2,
23 #[doc = "3: ADC is kept on after conversions, allowing for continuous conversion."]
24 KEEPADCWARM = 3,
25}
26impl From<WARMUPMODE_A> for u8 {
27 #[inline(always)]
28 fn from(variant: WARMUPMODE_A) -> Self {
29 variant as _
30 }
31}
32#[doc = "Reader of field `WARMUPMODE`"]
33pub type WARMUPMODE_R = crate::R<u8, WARMUPMODE_A>;
34impl WARMUPMODE_R {
35 #[doc = r"Get enumerated values variant"]
36 #[inline(always)]
37 pub fn variant(&self) -> WARMUPMODE_A {
38 match self.bits {
39 0 => WARMUPMODE_A::NORMAL,
40 1 => WARMUPMODE_A::KEEPINSTANDBY,
41 2 => WARMUPMODE_A::KEEPINSLOWACC,
42 3 => WARMUPMODE_A::KEEPADCWARM,
43 _ => unreachable!(),
44 }
45 }
46 #[doc = "Checks if the value of the field is `NORMAL`"]
47 #[inline(always)]
48 pub fn is_normal(&self) -> bool {
49 *self == WARMUPMODE_A::NORMAL
50 }
51 #[doc = "Checks if the value of the field is `KEEPINSTANDBY`"]
52 #[inline(always)]
53 pub fn is_keepinstandby(&self) -> bool {
54 *self == WARMUPMODE_A::KEEPINSTANDBY
55 }
56 #[doc = "Checks if the value of the field is `KEEPINSLOWACC`"]
57 #[inline(always)]
58 pub fn is_keepinslowacc(&self) -> bool {
59 *self == WARMUPMODE_A::KEEPINSLOWACC
60 }
61 #[doc = "Checks if the value of the field is `KEEPADCWARM`"]
62 #[inline(always)]
63 pub fn is_keepadcwarm(&self) -> bool {
64 *self == WARMUPMODE_A::KEEPADCWARM
65 }
66}
67#[doc = "Write proxy for field `WARMUPMODE`"]
68pub struct WARMUPMODE_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> WARMUPMODE_W<'a> {
72 #[doc = r"Writes `variant` to the field"]
73 #[inline(always)]
74 pub fn variant(self, variant: WARMUPMODE_A) -> &'a mut W {
75 {
76 self.bits(variant.into())
77 }
78 }
79 #[doc = "ADC is shut down after each conversion. 5us warmup time is used before each conversion."]
80 #[inline(always)]
81 pub fn normal(self) -> &'a mut W {
82 self.variant(WARMUPMODE_A::NORMAL)
83 }
84 #[doc = "ADC is kept in standby mode between conversions. 1us warmup time is used before each conversion."]
85 #[inline(always)]
86 pub fn keepinstandby(self) -> &'a mut W {
87 self.variant(WARMUPMODE_A::KEEPINSTANDBY)
88 }
89 #[doc = "ADC is kept in slow acquisition mode between conversions. 1us warmup time is used before each conversion."]
90 #[inline(always)]
91 pub fn keepinslowacc(self) -> &'a mut W {
92 self.variant(WARMUPMODE_A::KEEPINSLOWACC)
93 }
94 #[doc = "ADC is kept on after conversions, allowing for continuous conversion."]
95 #[inline(always)]
96 pub fn keepadcwarm(self) -> &'a mut W {
97 self.variant(WARMUPMODE_A::KEEPADCWARM)
98 }
99 #[doc = r"Writes raw bits to the field"]
100 #[inline(always)]
101 pub fn bits(self, value: u8) -> &'a mut W {
102 self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
103 self.w
104 }
105}
106#[doc = "Reader of field `SINGLEDMAWU`"]
107pub type SINGLEDMAWU_R = crate::R<bool, bool>;
108#[doc = "Write proxy for field `SINGLEDMAWU`"]
109pub struct SINGLEDMAWU_W<'a> {
110 w: &'a mut W,
111}
112impl<'a> SINGLEDMAWU_W<'a> {
113 #[doc = r"Sets the field bit"]
114 #[inline(always)]
115 pub fn set_bit(self) -> &'a mut W {
116 self.bit(true)
117 }
118 #[doc = r"Clears the field bit"]
119 #[inline(always)]
120 pub fn clear_bit(self) -> &'a mut W {
121 self.bit(false)
122 }
123 #[doc = r"Writes raw bits to the field"]
124 #[inline(always)]
125 pub fn bit(self, value: bool) -> &'a mut W {
126 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
127 self.w
128 }
129}
130#[doc = "Reader of field `SCANDMAWU`"]
131pub type SCANDMAWU_R = crate::R<bool, bool>;
132#[doc = "Write proxy for field `SCANDMAWU`"]
133pub struct SCANDMAWU_W<'a> {
134 w: &'a mut W,
135}
136impl<'a> SCANDMAWU_W<'a> {
137 #[doc = r"Sets the field bit"]
138 #[inline(always)]
139 pub fn set_bit(self) -> &'a mut W {
140 self.bit(true)
141 }
142 #[doc = r"Clears the field bit"]
143 #[inline(always)]
144 pub fn clear_bit(self) -> &'a mut W {
145 self.bit(false)
146 }
147 #[doc = r"Writes raw bits to the field"]
148 #[inline(always)]
149 pub fn bit(self, value: bool) -> &'a mut W {
150 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
151 self.w
152 }
153}
154#[doc = "Reader of field `TAILGATE`"]
155pub type TAILGATE_R = crate::R<bool, bool>;
156#[doc = "Write proxy for field `TAILGATE`"]
157pub struct TAILGATE_W<'a> {
158 w: &'a mut W,
159}
160impl<'a> TAILGATE_W<'a> {
161 #[doc = r"Sets the field bit"]
162 #[inline(always)]
163 pub fn set_bit(self) -> &'a mut W {
164 self.bit(true)
165 }
166 #[doc = r"Clears the field bit"]
167 #[inline(always)]
168 pub fn clear_bit(self) -> &'a mut W {
169 self.bit(false)
170 }
171 #[doc = r"Writes raw bits to the field"]
172 #[inline(always)]
173 pub fn bit(self, value: bool) -> &'a mut W {
174 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
175 self.w
176 }
177}
178#[doc = "Reader of field `ASYNCCLKEN`"]
179pub type ASYNCCLKEN_R = crate::R<bool, bool>;
180#[doc = "Write proxy for field `ASYNCCLKEN`"]
181pub struct ASYNCCLKEN_W<'a> {
182 w: &'a mut W,
183}
184impl<'a> ASYNCCLKEN_W<'a> {
185 #[doc = r"Sets the field bit"]
186 #[inline(always)]
187 pub fn set_bit(self) -> &'a mut W {
188 self.bit(true)
189 }
190 #[doc = r"Clears the field bit"]
191 #[inline(always)]
192 pub fn clear_bit(self) -> &'a mut W {
193 self.bit(false)
194 }
195 #[doc = r"Writes raw bits to the field"]
196 #[inline(always)]
197 pub fn bit(self, value: bool) -> &'a mut W {
198 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
199 self.w
200 }
201}
202#[doc = "Reader of field `ADCCLKMODE`"]
203pub type ADCCLKMODE_R = crate::R<bool, bool>;
204#[doc = "Write proxy for field `ADCCLKMODE`"]
205pub struct ADCCLKMODE_W<'a> {
206 w: &'a mut W,
207}
208impl<'a> ADCCLKMODE_W<'a> {
209 #[doc = r"Sets the field bit"]
210 #[inline(always)]
211 pub fn set_bit(self) -> &'a mut W {
212 self.bit(true)
213 }
214 #[doc = r"Clears the field bit"]
215 #[inline(always)]
216 pub fn clear_bit(self) -> &'a mut W {
217 self.bit(false)
218 }
219 #[doc = r"Writes raw bits to the field"]
220 #[inline(always)]
221 pub fn bit(self, value: bool) -> &'a mut W {
222 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
223 self.w
224 }
225}
226#[doc = "Prescalar Setting for ADC Sample and Conversion Clock\n\nValue on reset: 0"]
227#[derive(Clone, Copy, Debug, PartialEq)]
228#[repr(u8)]
229pub enum PRESC_A {
230 #[doc = "0: `0`"]
231 NODIVISION = 0,
232}
233impl From<PRESC_A> for u8 {
234 #[inline(always)]
235 fn from(variant: PRESC_A) -> Self {
236 variant as _
237 }
238}
239#[doc = "Reader of field `PRESC`"]
240pub type PRESC_R = crate::R<u8, PRESC_A>;
241impl PRESC_R {
242 #[doc = r"Get enumerated values variant"]
243 #[inline(always)]
244 pub fn variant(&self) -> crate::Variant<u8, PRESC_A> {
245 use crate::Variant::*;
246 match self.bits {
247 0 => Val(PRESC_A::NODIVISION),
248 i => Res(i),
249 }
250 }
251 #[doc = "Checks if the value of the field is `NODIVISION`"]
252 #[inline(always)]
253 pub fn is_nodivision(&self) -> bool {
254 *self == PRESC_A::NODIVISION
255 }
256}
257#[doc = "Write proxy for field `PRESC`"]
258pub struct PRESC_W<'a> {
259 w: &'a mut W,
260}
261impl<'a> PRESC_W<'a> {
262 #[doc = r"Writes `variant` to the field"]
263 #[inline(always)]
264 pub fn variant(self, variant: PRESC_A) -> &'a mut W {
265 unsafe { self.bits(variant.into()) }
266 }
267 #[doc = "`0`"]
268 #[inline(always)]
269 pub fn nodivision(self) -> &'a mut W {
270 self.variant(PRESC_A::NODIVISION)
271 }
272 #[doc = r"Writes raw bits to the field"]
273 #[inline(always)]
274 pub unsafe fn bits(self, value: u8) -> &'a mut W {
275 self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
276 self.w
277 }
278}
279#[doc = "Reader of field `TIMEBASE`"]
280pub type TIMEBASE_R = crate::R<u8, u8>;
281#[doc = "Write proxy for field `TIMEBASE`"]
282pub struct TIMEBASE_W<'a> {
283 w: &'a mut W,
284}
285impl<'a> TIMEBASE_W<'a> {
286 #[doc = r"Writes raw bits to the field"]
287 #[inline(always)]
288 pub unsafe fn bits(self, value: u8) -> &'a mut W {
289 self.w.bits = (self.w.bits & !(0x7f << 16)) | (((value as u32) & 0x7f) << 16);
290 self.w
291 }
292}
293#[doc = "Oversample Rate Select\n\nValue on reset: 0"]
294#[derive(Clone, Copy, Debug, PartialEq)]
295#[repr(u8)]
296pub enum OVSRSEL_A {
297 #[doc = "0: 2 samples for each conversion result"]
298 X2 = 0,
299 #[doc = "1: 4 samples for each conversion result"]
300 X4 = 1,
301 #[doc = "2: 8 samples for each conversion result"]
302 X8 = 2,
303 #[doc = "3: 16 samples for each conversion result"]
304 X16 = 3,
305 #[doc = "4: 32 samples for each conversion result"]
306 X32 = 4,
307 #[doc = "5: 64 samples for each conversion result"]
308 X64 = 5,
309 #[doc = "6: 128 samples for each conversion result"]
310 X128 = 6,
311 #[doc = "7: 256 samples for each conversion result"]
312 X256 = 7,
313 #[doc = "8: 512 samples for each conversion result"]
314 X512 = 8,
315 #[doc = "9: 1024 samples for each conversion result"]
316 X1024 = 9,
317 #[doc = "10: 2048 samples for each conversion result"]
318 X2048 = 10,
319 #[doc = "11: 4096 samples for each conversion result"]
320 X4096 = 11,
321}
322impl From<OVSRSEL_A> for u8 {
323 #[inline(always)]
324 fn from(variant: OVSRSEL_A) -> Self {
325 variant as _
326 }
327}
328#[doc = "Reader of field `OVSRSEL`"]
329pub type OVSRSEL_R = crate::R<u8, OVSRSEL_A>;
330impl OVSRSEL_R {
331 #[doc = r"Get enumerated values variant"]
332 #[inline(always)]
333 pub fn variant(&self) -> crate::Variant<u8, OVSRSEL_A> {
334 use crate::Variant::*;
335 match self.bits {
336 0 => Val(OVSRSEL_A::X2),
337 1 => Val(OVSRSEL_A::X4),
338 2 => Val(OVSRSEL_A::X8),
339 3 => Val(OVSRSEL_A::X16),
340 4 => Val(OVSRSEL_A::X32),
341 5 => Val(OVSRSEL_A::X64),
342 6 => Val(OVSRSEL_A::X128),
343 7 => Val(OVSRSEL_A::X256),
344 8 => Val(OVSRSEL_A::X512),
345 9 => Val(OVSRSEL_A::X1024),
346 10 => Val(OVSRSEL_A::X2048),
347 11 => Val(OVSRSEL_A::X4096),
348 i => Res(i),
349 }
350 }
351 #[doc = "Checks if the value of the field is `X2`"]
352 #[inline(always)]
353 pub fn is_x2(&self) -> bool {
354 *self == OVSRSEL_A::X2
355 }
356 #[doc = "Checks if the value of the field is `X4`"]
357 #[inline(always)]
358 pub fn is_x4(&self) -> bool {
359 *self == OVSRSEL_A::X4
360 }
361 #[doc = "Checks if the value of the field is `X8`"]
362 #[inline(always)]
363 pub fn is_x8(&self) -> bool {
364 *self == OVSRSEL_A::X8
365 }
366 #[doc = "Checks if the value of the field is `X16`"]
367 #[inline(always)]
368 pub fn is_x16(&self) -> bool {
369 *self == OVSRSEL_A::X16
370 }
371 #[doc = "Checks if the value of the field is `X32`"]
372 #[inline(always)]
373 pub fn is_x32(&self) -> bool {
374 *self == OVSRSEL_A::X32
375 }
376 #[doc = "Checks if the value of the field is `X64`"]
377 #[inline(always)]
378 pub fn is_x64(&self) -> bool {
379 *self == OVSRSEL_A::X64
380 }
381 #[doc = "Checks if the value of the field is `X128`"]
382 #[inline(always)]
383 pub fn is_x128(&self) -> bool {
384 *self == OVSRSEL_A::X128
385 }
386 #[doc = "Checks if the value of the field is `X256`"]
387 #[inline(always)]
388 pub fn is_x256(&self) -> bool {
389 *self == OVSRSEL_A::X256
390 }
391 #[doc = "Checks if the value of the field is `X512`"]
392 #[inline(always)]
393 pub fn is_x512(&self) -> bool {
394 *self == OVSRSEL_A::X512
395 }
396 #[doc = "Checks if the value of the field is `X1024`"]
397 #[inline(always)]
398 pub fn is_x1024(&self) -> bool {
399 *self == OVSRSEL_A::X1024
400 }
401 #[doc = "Checks if the value of the field is `X2048`"]
402 #[inline(always)]
403 pub fn is_x2048(&self) -> bool {
404 *self == OVSRSEL_A::X2048
405 }
406 #[doc = "Checks if the value of the field is `X4096`"]
407 #[inline(always)]
408 pub fn is_x4096(&self) -> bool {
409 *self == OVSRSEL_A::X4096
410 }
411}
412#[doc = "Write proxy for field `OVSRSEL`"]
413pub struct OVSRSEL_W<'a> {
414 w: &'a mut W,
415}
416impl<'a> OVSRSEL_W<'a> {
417 #[doc = r"Writes `variant` to the field"]
418 #[inline(always)]
419 pub fn variant(self, variant: OVSRSEL_A) -> &'a mut W {
420 unsafe { self.bits(variant.into()) }
421 }
422 #[doc = "2 samples for each conversion result"]
423 #[inline(always)]
424 pub fn x2(self) -> &'a mut W {
425 self.variant(OVSRSEL_A::X2)
426 }
427 #[doc = "4 samples for each conversion result"]
428 #[inline(always)]
429 pub fn x4(self) -> &'a mut W {
430 self.variant(OVSRSEL_A::X4)
431 }
432 #[doc = "8 samples for each conversion result"]
433 #[inline(always)]
434 pub fn x8(self) -> &'a mut W {
435 self.variant(OVSRSEL_A::X8)
436 }
437 #[doc = "16 samples for each conversion result"]
438 #[inline(always)]
439 pub fn x16(self) -> &'a mut W {
440 self.variant(OVSRSEL_A::X16)
441 }
442 #[doc = "32 samples for each conversion result"]
443 #[inline(always)]
444 pub fn x32(self) -> &'a mut W {
445 self.variant(OVSRSEL_A::X32)
446 }
447 #[doc = "64 samples for each conversion result"]
448 #[inline(always)]
449 pub fn x64(self) -> &'a mut W {
450 self.variant(OVSRSEL_A::X64)
451 }
452 #[doc = "128 samples for each conversion result"]
453 #[inline(always)]
454 pub fn x128(self) -> &'a mut W {
455 self.variant(OVSRSEL_A::X128)
456 }
457 #[doc = "256 samples for each conversion result"]
458 #[inline(always)]
459 pub fn x256(self) -> &'a mut W {
460 self.variant(OVSRSEL_A::X256)
461 }
462 #[doc = "512 samples for each conversion result"]
463 #[inline(always)]
464 pub fn x512(self) -> &'a mut W {
465 self.variant(OVSRSEL_A::X512)
466 }
467 #[doc = "1024 samples for each conversion result"]
468 #[inline(always)]
469 pub fn x1024(self) -> &'a mut W {
470 self.variant(OVSRSEL_A::X1024)
471 }
472 #[doc = "2048 samples for each conversion result"]
473 #[inline(always)]
474 pub fn x2048(self) -> &'a mut W {
475 self.variant(OVSRSEL_A::X2048)
476 }
477 #[doc = "4096 samples for each conversion result"]
478 #[inline(always)]
479 pub fn x4096(self) -> &'a mut W {
480 self.variant(OVSRSEL_A::X4096)
481 }
482 #[doc = r"Writes raw bits to the field"]
483 #[inline(always)]
484 pub unsafe fn bits(self, value: u8) -> &'a mut W {
485 self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
486 self.w
487 }
488}
489#[doc = "Reader of field `DBGHALT`"]
490pub type DBGHALT_R = crate::R<bool, bool>;
491#[doc = "Write proxy for field `DBGHALT`"]
492pub struct DBGHALT_W<'a> {
493 w: &'a mut W,
494}
495impl<'a> DBGHALT_W<'a> {
496 #[doc = r"Sets the field bit"]
497 #[inline(always)]
498 pub fn set_bit(self) -> &'a mut W {
499 self.bit(true)
500 }
501 #[doc = r"Clears the field bit"]
502 #[inline(always)]
503 pub fn clear_bit(self) -> &'a mut W {
504 self.bit(false)
505 }
506 #[doc = r"Writes raw bits to the field"]
507 #[inline(always)]
508 pub fn bit(self, value: bool) -> &'a mut W {
509 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
510 self.w
511 }
512}
513#[doc = "Reader of field `CHCONMODE`"]
514pub type CHCONMODE_R = crate::R<bool, bool>;
515#[doc = "Write proxy for field `CHCONMODE`"]
516pub struct CHCONMODE_W<'a> {
517 w: &'a mut W,
518}
519impl<'a> CHCONMODE_W<'a> {
520 #[doc = r"Sets the field bit"]
521 #[inline(always)]
522 pub fn set_bit(self) -> &'a mut W {
523 self.bit(true)
524 }
525 #[doc = r"Clears the field bit"]
526 #[inline(always)]
527 pub fn clear_bit(self) -> &'a mut W {
528 self.bit(false)
529 }
530 #[doc = r"Writes raw bits to the field"]
531 #[inline(always)]
532 pub fn bit(self, value: bool) -> &'a mut W {
533 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
534 self.w
535 }
536}
537#[doc = "Channel Connect and Reference Warm Sel When ADC is IDLE\n\nValue on reset: 0"]
538#[derive(Clone, Copy, Debug, PartialEq)]
539#[repr(u8)]
540pub enum CHCONREFWARMIDLE_A {
541 #[doc = "0: Keep scan reference warm and APORT switches for first scan channel closed if WARMUPMODE is not NORMAL"]
542 PREFSCAN = 0,
543 #[doc = "1: Keep single reference warm and keep APORT switches for single channel closed if WARMUPMODE is not NORMAL"]
544 PREFSINGLE = 1,
545 #[doc = "2: Keep last used reference warm and keep APORT switches for corresponding channel closed if WARMUPMODE is not NORMAL"]
546 KEEPPREV = 2,
547}
548impl From<CHCONREFWARMIDLE_A> for u8 {
549 #[inline(always)]
550 fn from(variant: CHCONREFWARMIDLE_A) -> Self {
551 variant as _
552 }
553}
554#[doc = "Reader of field `CHCONREFWARMIDLE`"]
555pub type CHCONREFWARMIDLE_R = crate::R<u8, CHCONREFWARMIDLE_A>;
556impl CHCONREFWARMIDLE_R {
557 #[doc = r"Get enumerated values variant"]
558 #[inline(always)]
559 pub fn variant(&self) -> crate::Variant<u8, CHCONREFWARMIDLE_A> {
560 use crate::Variant::*;
561 match self.bits {
562 0 => Val(CHCONREFWARMIDLE_A::PREFSCAN),
563 1 => Val(CHCONREFWARMIDLE_A::PREFSINGLE),
564 2 => Val(CHCONREFWARMIDLE_A::KEEPPREV),
565 i => Res(i),
566 }
567 }
568 #[doc = "Checks if the value of the field is `PREFSCAN`"]
569 #[inline(always)]
570 pub fn is_prefscan(&self) -> bool {
571 *self == CHCONREFWARMIDLE_A::PREFSCAN
572 }
573 #[doc = "Checks if the value of the field is `PREFSINGLE`"]
574 #[inline(always)]
575 pub fn is_prefsingle(&self) -> bool {
576 *self == CHCONREFWARMIDLE_A::PREFSINGLE
577 }
578 #[doc = "Checks if the value of the field is `KEEPPREV`"]
579 #[inline(always)]
580 pub fn is_keepprev(&self) -> bool {
581 *self == CHCONREFWARMIDLE_A::KEEPPREV
582 }
583}
584#[doc = "Write proxy for field `CHCONREFWARMIDLE`"]
585pub struct CHCONREFWARMIDLE_W<'a> {
586 w: &'a mut W,
587}
588impl<'a> CHCONREFWARMIDLE_W<'a> {
589 #[doc = r"Writes `variant` to the field"]
590 #[inline(always)]
591 pub fn variant(self, variant: CHCONREFWARMIDLE_A) -> &'a mut W {
592 unsafe { self.bits(variant.into()) }
593 }
594 #[doc = "Keep scan reference warm and APORT switches for first scan channel closed if WARMUPMODE is not NORMAL"]
595 #[inline(always)]
596 pub fn prefscan(self) -> &'a mut W {
597 self.variant(CHCONREFWARMIDLE_A::PREFSCAN)
598 }
599 #[doc = "Keep single reference warm and keep APORT switches for single channel closed if WARMUPMODE is not NORMAL"]
600 #[inline(always)]
601 pub fn prefsingle(self) -> &'a mut W {
602 self.variant(CHCONREFWARMIDLE_A::PREFSINGLE)
603 }
604 #[doc = "Keep last used reference warm and keep APORT switches for corresponding channel closed if WARMUPMODE is not NORMAL"]
605 #[inline(always)]
606 pub fn keepprev(self) -> &'a mut W {
607 self.variant(CHCONREFWARMIDLE_A::KEEPPREV)
608 }
609 #[doc = r"Writes raw bits to the field"]
610 #[inline(always)]
611 pub unsafe fn bits(self, value: u8) -> &'a mut W {
612 self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
613 self.w
614 }
615}
616impl R {
617 #[doc = "Bits 0:1 - Warm-up Mode"]
618 #[inline(always)]
619 pub fn warmupmode(&self) -> WARMUPMODE_R {
620 WARMUPMODE_R::new((self.bits & 0x03) as u8)
621 }
622 #[doc = "Bit 2 - SINGLEFIFO DMA Wakeup"]
623 #[inline(always)]
624 pub fn singledmawu(&self) -> SINGLEDMAWU_R {
625 SINGLEDMAWU_R::new(((self.bits >> 2) & 0x01) != 0)
626 }
627 #[doc = "Bit 3 - SCANFIFO DMA Wakeup"]
628 #[inline(always)]
629 pub fn scandmawu(&self) -> SCANDMAWU_R {
630 SCANDMAWU_R::new(((self.bits >> 3) & 0x01) != 0)
631 }
632 #[doc = "Bit 4 - Conversion Tailgating"]
633 #[inline(always)]
634 pub fn tailgate(&self) -> TAILGATE_R {
635 TAILGATE_R::new(((self.bits >> 4) & 0x01) != 0)
636 }
637 #[doc = "Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
638 #[inline(always)]
639 pub fn asyncclken(&self) -> ASYNCCLKEN_R {
640 ASYNCCLKEN_R::new(((self.bits >> 6) & 0x01) != 0)
641 }
642 #[doc = "Bit 7 - ADC Clock Mode"]
643 #[inline(always)]
644 pub fn adcclkmode(&self) -> ADCCLKMODE_R {
645 ADCCLKMODE_R::new(((self.bits >> 7) & 0x01) != 0)
646 }
647 #[doc = "Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock"]
648 #[inline(always)]
649 pub fn presc(&self) -> PRESC_R {
650 PRESC_R::new(((self.bits >> 8) & 0x7f) as u8)
651 }
652 #[doc = "Bits 16:22 - 1us Time Base"]
653 #[inline(always)]
654 pub fn timebase(&self) -> TIMEBASE_R {
655 TIMEBASE_R::new(((self.bits >> 16) & 0x7f) as u8)
656 }
657 #[doc = "Bits 24:27 - Oversample Rate Select"]
658 #[inline(always)]
659 pub fn ovsrsel(&self) -> OVSRSEL_R {
660 OVSRSEL_R::new(((self.bits >> 24) & 0x0f) as u8)
661 }
662 #[doc = "Bit 28 - Debug Mode Halt Enable"]
663 #[inline(always)]
664 pub fn dbghalt(&self) -> DBGHALT_R {
665 DBGHALT_R::new(((self.bits >> 28) & 0x01) != 0)
666 }
667 #[doc = "Bit 29 - Channel Connect"]
668 #[inline(always)]
669 pub fn chconmode(&self) -> CHCONMODE_R {
670 CHCONMODE_R::new(((self.bits >> 29) & 0x01) != 0)
671 }
672 #[doc = "Bits 30:31 - Channel Connect and Reference Warm Sel When ADC is IDLE"]
673 #[inline(always)]
674 pub fn chconrefwarmidle(&self) -> CHCONREFWARMIDLE_R {
675 CHCONREFWARMIDLE_R::new(((self.bits >> 30) & 0x03) as u8)
676 }
677}
678impl W {
679 #[doc = "Bits 0:1 - Warm-up Mode"]
680 #[inline(always)]
681 pub fn warmupmode(&mut self) -> WARMUPMODE_W {
682 WARMUPMODE_W { w: self }
683 }
684 #[doc = "Bit 2 - SINGLEFIFO DMA Wakeup"]
685 #[inline(always)]
686 pub fn singledmawu(&mut self) -> SINGLEDMAWU_W {
687 SINGLEDMAWU_W { w: self }
688 }
689 #[doc = "Bit 3 - SCANFIFO DMA Wakeup"]
690 #[inline(always)]
691 pub fn scandmawu(&mut self) -> SCANDMAWU_W {
692 SCANDMAWU_W { w: self }
693 }
694 #[doc = "Bit 4 - Conversion Tailgating"]
695 #[inline(always)]
696 pub fn tailgate(&mut self) -> TAILGATE_W {
697 TAILGATE_W { w: self }
698 }
699 #[doc = "Bit 6 - Selects ASYNC CLK Enable Mode When ADCCLKMODE=1"]
700 #[inline(always)]
701 pub fn asyncclken(&mut self) -> ASYNCCLKEN_W {
702 ASYNCCLKEN_W { w: self }
703 }
704 #[doc = "Bit 7 - ADC Clock Mode"]
705 #[inline(always)]
706 pub fn adcclkmode(&mut self) -> ADCCLKMODE_W {
707 ADCCLKMODE_W { w: self }
708 }
709 #[doc = "Bits 8:14 - Prescalar Setting for ADC Sample and Conversion Clock"]
710 #[inline(always)]
711 pub fn presc(&mut self) -> PRESC_W {
712 PRESC_W { w: self }
713 }
714 #[doc = "Bits 16:22 - 1us Time Base"]
715 #[inline(always)]
716 pub fn timebase(&mut self) -> TIMEBASE_W {
717 TIMEBASE_W { w: self }
718 }
719 #[doc = "Bits 24:27 - Oversample Rate Select"]
720 #[inline(always)]
721 pub fn ovsrsel(&mut self) -> OVSRSEL_W {
722 OVSRSEL_W { w: self }
723 }
724 #[doc = "Bit 28 - Debug Mode Halt Enable"]
725 #[inline(always)]
726 pub fn dbghalt(&mut self) -> DBGHALT_W {
727 DBGHALT_W { w: self }
728 }
729 #[doc = "Bit 29 - Channel Connect"]
730 #[inline(always)]
731 pub fn chconmode(&mut self) -> CHCONMODE_W {
732 CHCONMODE_W { w: self }
733 }
734 #[doc = "Bits 30:31 - Channel Connect and Reference Warm Sel When ADC is IDLE"]
735 #[inline(always)]
736 pub fn chconrefwarmidle(&mut self) -> CHCONREFWARMIDLE_W {
737 CHCONREFWARMIDLE_W { w: self }
738 }
739}