efm32pg12_pac/adc0/
scannegsel.rs

1#[doc = "Reader of register SCANNEGSEL"]
2pub type R = crate::R<u32, super::SCANNEGSEL>;
3#[doc = "Writer for register SCANNEGSEL"]
4pub type W = crate::W<u32, super::SCANNEGSEL>;
5#[doc = "Register SCANNEGSEL `reset()`'s with value 0x39e4"]
6impl crate::ResetValue for super::SCANNEGSEL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x39e4
11    }
12}
13#[doc = "Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum INPUT0NEGSEL_A {
17    #[doc = "0: Selects ADCn_INPUT1 as negative channel input"]
18    INPUT1 = 0,
19    #[doc = "1: Selects ADCn_INPUT3 as negative channel input"]
20    INPUT3 = 1,
21    #[doc = "2: Selects ADCn_INPUT5 as negative channel input"]
22    INPUT5 = 2,
23    #[doc = "3: Selects ADCn_INPUT7 as negative channel input"]
24    INPUT7 = 3,
25}
26impl From<INPUT0NEGSEL_A> for u8 {
27    #[inline(always)]
28    fn from(variant: INPUT0NEGSEL_A) -> Self {
29        variant as _
30    }
31}
32#[doc = "Reader of field `INPUT0NEGSEL`"]
33pub type INPUT0NEGSEL_R = crate::R<u8, INPUT0NEGSEL_A>;
34impl INPUT0NEGSEL_R {
35    #[doc = r"Get enumerated values variant"]
36    #[inline(always)]
37    pub fn variant(&self) -> INPUT0NEGSEL_A {
38        match self.bits {
39            0 => INPUT0NEGSEL_A::INPUT1,
40            1 => INPUT0NEGSEL_A::INPUT3,
41            2 => INPUT0NEGSEL_A::INPUT5,
42            3 => INPUT0NEGSEL_A::INPUT7,
43            _ => unreachable!(),
44        }
45    }
46    #[doc = "Checks if the value of the field is `INPUT1`"]
47    #[inline(always)]
48    pub fn is_input1(&self) -> bool {
49        *self == INPUT0NEGSEL_A::INPUT1
50    }
51    #[doc = "Checks if the value of the field is `INPUT3`"]
52    #[inline(always)]
53    pub fn is_input3(&self) -> bool {
54        *self == INPUT0NEGSEL_A::INPUT3
55    }
56    #[doc = "Checks if the value of the field is `INPUT5`"]
57    #[inline(always)]
58    pub fn is_input5(&self) -> bool {
59        *self == INPUT0NEGSEL_A::INPUT5
60    }
61    #[doc = "Checks if the value of the field is `INPUT7`"]
62    #[inline(always)]
63    pub fn is_input7(&self) -> bool {
64        *self == INPUT0NEGSEL_A::INPUT7
65    }
66}
67#[doc = "Write proxy for field `INPUT0NEGSEL`"]
68pub struct INPUT0NEGSEL_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> INPUT0NEGSEL_W<'a> {
72    #[doc = r"Writes `variant` to the field"]
73    #[inline(always)]
74    pub fn variant(self, variant: INPUT0NEGSEL_A) -> &'a mut W {
75        {
76            self.bits(variant.into())
77        }
78    }
79    #[doc = "Selects ADCn_INPUT1 as negative channel input"]
80    #[inline(always)]
81    pub fn input1(self) -> &'a mut W {
82        self.variant(INPUT0NEGSEL_A::INPUT1)
83    }
84    #[doc = "Selects ADCn_INPUT3 as negative channel input"]
85    #[inline(always)]
86    pub fn input3(self) -> &'a mut W {
87        self.variant(INPUT0NEGSEL_A::INPUT3)
88    }
89    #[doc = "Selects ADCn_INPUT5 as negative channel input"]
90    #[inline(always)]
91    pub fn input5(self) -> &'a mut W {
92        self.variant(INPUT0NEGSEL_A::INPUT5)
93    }
94    #[doc = "Selects ADCn_INPUT7 as negative channel input"]
95    #[inline(always)]
96    pub fn input7(self) -> &'a mut W {
97        self.variant(INPUT0NEGSEL_A::INPUT7)
98    }
99    #[doc = r"Writes raw bits to the field"]
100    #[inline(always)]
101    pub fn bits(self, value: u8) -> &'a mut W {
102        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
103        self.w
104    }
105}
106#[doc = "Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode\n\nValue on reset: 1"]
107#[derive(Clone, Copy, Debug, PartialEq)]
108#[repr(u8)]
109pub enum INPUT2NEGSEL_A {
110    #[doc = "0: Selects ADCn_INPUT1 as negative channel input"]
111    INPUT1 = 0,
112    #[doc = "1: Selects ADCn_INPUT3 as negative channel input"]
113    INPUT3 = 1,
114    #[doc = "2: Selects ADCn_INPUT5 as negative channel input"]
115    INPUT5 = 2,
116    #[doc = "3: Selects ADCn_INPUT7 as negative channel input"]
117    INPUT7 = 3,
118}
119impl From<INPUT2NEGSEL_A> for u8 {
120    #[inline(always)]
121    fn from(variant: INPUT2NEGSEL_A) -> Self {
122        variant as _
123    }
124}
125#[doc = "Reader of field `INPUT2NEGSEL`"]
126pub type INPUT2NEGSEL_R = crate::R<u8, INPUT2NEGSEL_A>;
127impl INPUT2NEGSEL_R {
128    #[doc = r"Get enumerated values variant"]
129    #[inline(always)]
130    pub fn variant(&self) -> INPUT2NEGSEL_A {
131        match self.bits {
132            0 => INPUT2NEGSEL_A::INPUT1,
133            1 => INPUT2NEGSEL_A::INPUT3,
134            2 => INPUT2NEGSEL_A::INPUT5,
135            3 => INPUT2NEGSEL_A::INPUT7,
136            _ => unreachable!(),
137        }
138    }
139    #[doc = "Checks if the value of the field is `INPUT1`"]
140    #[inline(always)]
141    pub fn is_input1(&self) -> bool {
142        *self == INPUT2NEGSEL_A::INPUT1
143    }
144    #[doc = "Checks if the value of the field is `INPUT3`"]
145    #[inline(always)]
146    pub fn is_input3(&self) -> bool {
147        *self == INPUT2NEGSEL_A::INPUT3
148    }
149    #[doc = "Checks if the value of the field is `INPUT5`"]
150    #[inline(always)]
151    pub fn is_input5(&self) -> bool {
152        *self == INPUT2NEGSEL_A::INPUT5
153    }
154    #[doc = "Checks if the value of the field is `INPUT7`"]
155    #[inline(always)]
156    pub fn is_input7(&self) -> bool {
157        *self == INPUT2NEGSEL_A::INPUT7
158    }
159}
160#[doc = "Write proxy for field `INPUT2NEGSEL`"]
161pub struct INPUT2NEGSEL_W<'a> {
162    w: &'a mut W,
163}
164impl<'a> INPUT2NEGSEL_W<'a> {
165    #[doc = r"Writes `variant` to the field"]
166    #[inline(always)]
167    pub fn variant(self, variant: INPUT2NEGSEL_A) -> &'a mut W {
168        {
169            self.bits(variant.into())
170        }
171    }
172    #[doc = "Selects ADCn_INPUT1 as negative channel input"]
173    #[inline(always)]
174    pub fn input1(self) -> &'a mut W {
175        self.variant(INPUT2NEGSEL_A::INPUT1)
176    }
177    #[doc = "Selects ADCn_INPUT3 as negative channel input"]
178    #[inline(always)]
179    pub fn input3(self) -> &'a mut W {
180        self.variant(INPUT2NEGSEL_A::INPUT3)
181    }
182    #[doc = "Selects ADCn_INPUT5 as negative channel input"]
183    #[inline(always)]
184    pub fn input5(self) -> &'a mut W {
185        self.variant(INPUT2NEGSEL_A::INPUT5)
186    }
187    #[doc = "Selects ADCn_INPUT7 as negative channel input"]
188    #[inline(always)]
189    pub fn input7(self) -> &'a mut W {
190        self.variant(INPUT2NEGSEL_A::INPUT7)
191    }
192    #[doc = r"Writes raw bits to the field"]
193    #[inline(always)]
194    pub fn bits(self, value: u8) -> &'a mut W {
195        self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
196        self.w
197    }
198}
199#[doc = "Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode\n\nValue on reset: 2"]
200#[derive(Clone, Copy, Debug, PartialEq)]
201#[repr(u8)]
202pub enum INPUT4NEGSEL_A {
203    #[doc = "0: Selects ADCn_INPUT1 as negative channel input"]
204    INPUT1 = 0,
205    #[doc = "1: Selects ADCn_INPUT3 as negative channel input"]
206    INPUT3 = 1,
207    #[doc = "2: Selects ADCn_INPUT5 as negative channel input"]
208    INPUT5 = 2,
209    #[doc = "3: Selects ADCn_INPUT7 as negative channel input"]
210    INPUT7 = 3,
211}
212impl From<INPUT4NEGSEL_A> for u8 {
213    #[inline(always)]
214    fn from(variant: INPUT4NEGSEL_A) -> Self {
215        variant as _
216    }
217}
218#[doc = "Reader of field `INPUT4NEGSEL`"]
219pub type INPUT4NEGSEL_R = crate::R<u8, INPUT4NEGSEL_A>;
220impl INPUT4NEGSEL_R {
221    #[doc = r"Get enumerated values variant"]
222    #[inline(always)]
223    pub fn variant(&self) -> INPUT4NEGSEL_A {
224        match self.bits {
225            0 => INPUT4NEGSEL_A::INPUT1,
226            1 => INPUT4NEGSEL_A::INPUT3,
227            2 => INPUT4NEGSEL_A::INPUT5,
228            3 => INPUT4NEGSEL_A::INPUT7,
229            _ => unreachable!(),
230        }
231    }
232    #[doc = "Checks if the value of the field is `INPUT1`"]
233    #[inline(always)]
234    pub fn is_input1(&self) -> bool {
235        *self == INPUT4NEGSEL_A::INPUT1
236    }
237    #[doc = "Checks if the value of the field is `INPUT3`"]
238    #[inline(always)]
239    pub fn is_input3(&self) -> bool {
240        *self == INPUT4NEGSEL_A::INPUT3
241    }
242    #[doc = "Checks if the value of the field is `INPUT5`"]
243    #[inline(always)]
244    pub fn is_input5(&self) -> bool {
245        *self == INPUT4NEGSEL_A::INPUT5
246    }
247    #[doc = "Checks if the value of the field is `INPUT7`"]
248    #[inline(always)]
249    pub fn is_input7(&self) -> bool {
250        *self == INPUT4NEGSEL_A::INPUT7
251    }
252}
253#[doc = "Write proxy for field `INPUT4NEGSEL`"]
254pub struct INPUT4NEGSEL_W<'a> {
255    w: &'a mut W,
256}
257impl<'a> INPUT4NEGSEL_W<'a> {
258    #[doc = r"Writes `variant` to the field"]
259    #[inline(always)]
260    pub fn variant(self, variant: INPUT4NEGSEL_A) -> &'a mut W {
261        {
262            self.bits(variant.into())
263        }
264    }
265    #[doc = "Selects ADCn_INPUT1 as negative channel input"]
266    #[inline(always)]
267    pub fn input1(self) -> &'a mut W {
268        self.variant(INPUT4NEGSEL_A::INPUT1)
269    }
270    #[doc = "Selects ADCn_INPUT3 as negative channel input"]
271    #[inline(always)]
272    pub fn input3(self) -> &'a mut W {
273        self.variant(INPUT4NEGSEL_A::INPUT3)
274    }
275    #[doc = "Selects ADCn_INPUT5 as negative channel input"]
276    #[inline(always)]
277    pub fn input5(self) -> &'a mut W {
278        self.variant(INPUT4NEGSEL_A::INPUT5)
279    }
280    #[doc = "Selects ADCn_INPUT7 as negative channel input"]
281    #[inline(always)]
282    pub fn input7(self) -> &'a mut W {
283        self.variant(INPUT4NEGSEL_A::INPUT7)
284    }
285    #[doc = r"Writes raw bits to the field"]
286    #[inline(always)]
287    pub fn bits(self, value: u8) -> &'a mut W {
288        self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
289        self.w
290    }
291}
292#[doc = "Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode\n\nValue on reset: 3"]
293#[derive(Clone, Copy, Debug, PartialEq)]
294#[repr(u8)]
295pub enum INPUT6NEGSEL_A {
296    #[doc = "0: Selects ADCn_INPUT1 as negative channel input"]
297    INPUT1 = 0,
298    #[doc = "1: Selects ADCn_INPUT3 as negative channel input"]
299    INPUT3 = 1,
300    #[doc = "2: Selects ADCn_INPUT5 as negative channel input"]
301    INPUT5 = 2,
302    #[doc = "3: Selects ADCn_INPUT7 as negative channel input"]
303    INPUT7 = 3,
304}
305impl From<INPUT6NEGSEL_A> for u8 {
306    #[inline(always)]
307    fn from(variant: INPUT6NEGSEL_A) -> Self {
308        variant as _
309    }
310}
311#[doc = "Reader of field `INPUT6NEGSEL`"]
312pub type INPUT6NEGSEL_R = crate::R<u8, INPUT6NEGSEL_A>;
313impl INPUT6NEGSEL_R {
314    #[doc = r"Get enumerated values variant"]
315    #[inline(always)]
316    pub fn variant(&self) -> INPUT6NEGSEL_A {
317        match self.bits {
318            0 => INPUT6NEGSEL_A::INPUT1,
319            1 => INPUT6NEGSEL_A::INPUT3,
320            2 => INPUT6NEGSEL_A::INPUT5,
321            3 => INPUT6NEGSEL_A::INPUT7,
322            _ => unreachable!(),
323        }
324    }
325    #[doc = "Checks if the value of the field is `INPUT1`"]
326    #[inline(always)]
327    pub fn is_input1(&self) -> bool {
328        *self == INPUT6NEGSEL_A::INPUT1
329    }
330    #[doc = "Checks if the value of the field is `INPUT3`"]
331    #[inline(always)]
332    pub fn is_input3(&self) -> bool {
333        *self == INPUT6NEGSEL_A::INPUT3
334    }
335    #[doc = "Checks if the value of the field is `INPUT5`"]
336    #[inline(always)]
337    pub fn is_input5(&self) -> bool {
338        *self == INPUT6NEGSEL_A::INPUT5
339    }
340    #[doc = "Checks if the value of the field is `INPUT7`"]
341    #[inline(always)]
342    pub fn is_input7(&self) -> bool {
343        *self == INPUT6NEGSEL_A::INPUT7
344    }
345}
346#[doc = "Write proxy for field `INPUT6NEGSEL`"]
347pub struct INPUT6NEGSEL_W<'a> {
348    w: &'a mut W,
349}
350impl<'a> INPUT6NEGSEL_W<'a> {
351    #[doc = r"Writes `variant` to the field"]
352    #[inline(always)]
353    pub fn variant(self, variant: INPUT6NEGSEL_A) -> &'a mut W {
354        {
355            self.bits(variant.into())
356        }
357    }
358    #[doc = "Selects ADCn_INPUT1 as negative channel input"]
359    #[inline(always)]
360    pub fn input1(self) -> &'a mut W {
361        self.variant(INPUT6NEGSEL_A::INPUT1)
362    }
363    #[doc = "Selects ADCn_INPUT3 as negative channel input"]
364    #[inline(always)]
365    pub fn input3(self) -> &'a mut W {
366        self.variant(INPUT6NEGSEL_A::INPUT3)
367    }
368    #[doc = "Selects ADCn_INPUT5 as negative channel input"]
369    #[inline(always)]
370    pub fn input5(self) -> &'a mut W {
371        self.variant(INPUT6NEGSEL_A::INPUT5)
372    }
373    #[doc = "Selects ADCn_INPUT7 as negative channel input"]
374    #[inline(always)]
375    pub fn input7(self) -> &'a mut W {
376        self.variant(INPUT6NEGSEL_A::INPUT7)
377    }
378    #[doc = r"Writes raw bits to the field"]
379    #[inline(always)]
380    pub fn bits(self, value: u8) -> &'a mut W {
381        self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
382        self.w
383    }
384}
385#[doc = "Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode\n\nValue on reset: 1"]
386#[derive(Clone, Copy, Debug, PartialEq)]
387#[repr(u8)]
388pub enum INPUT9NEGSEL_A {
389    #[doc = "0: Selects ADCn_INPUT8 as negative channel input"]
390    INPUT8 = 0,
391    #[doc = "1: Selects ADCn_INPUT10 as negative channel input"]
392    INPUT10 = 1,
393    #[doc = "2: Selects ADCn_INPUT12 as negative channel input"]
394    INPUT12 = 2,
395    #[doc = "3: Selects ADCn_INPUT14 as negative channel input"]
396    INPUT14 = 3,
397}
398impl From<INPUT9NEGSEL_A> for u8 {
399    #[inline(always)]
400    fn from(variant: INPUT9NEGSEL_A) -> Self {
401        variant as _
402    }
403}
404#[doc = "Reader of field `INPUT9NEGSEL`"]
405pub type INPUT9NEGSEL_R = crate::R<u8, INPUT9NEGSEL_A>;
406impl INPUT9NEGSEL_R {
407    #[doc = r"Get enumerated values variant"]
408    #[inline(always)]
409    pub fn variant(&self) -> INPUT9NEGSEL_A {
410        match self.bits {
411            0 => INPUT9NEGSEL_A::INPUT8,
412            1 => INPUT9NEGSEL_A::INPUT10,
413            2 => INPUT9NEGSEL_A::INPUT12,
414            3 => INPUT9NEGSEL_A::INPUT14,
415            _ => unreachable!(),
416        }
417    }
418    #[doc = "Checks if the value of the field is `INPUT8`"]
419    #[inline(always)]
420    pub fn is_input8(&self) -> bool {
421        *self == INPUT9NEGSEL_A::INPUT8
422    }
423    #[doc = "Checks if the value of the field is `INPUT10`"]
424    #[inline(always)]
425    pub fn is_input10(&self) -> bool {
426        *self == INPUT9NEGSEL_A::INPUT10
427    }
428    #[doc = "Checks if the value of the field is `INPUT12`"]
429    #[inline(always)]
430    pub fn is_input12(&self) -> bool {
431        *self == INPUT9NEGSEL_A::INPUT12
432    }
433    #[doc = "Checks if the value of the field is `INPUT14`"]
434    #[inline(always)]
435    pub fn is_input14(&self) -> bool {
436        *self == INPUT9NEGSEL_A::INPUT14
437    }
438}
439#[doc = "Write proxy for field `INPUT9NEGSEL`"]
440pub struct INPUT9NEGSEL_W<'a> {
441    w: &'a mut W,
442}
443impl<'a> INPUT9NEGSEL_W<'a> {
444    #[doc = r"Writes `variant` to the field"]
445    #[inline(always)]
446    pub fn variant(self, variant: INPUT9NEGSEL_A) -> &'a mut W {
447        {
448            self.bits(variant.into())
449        }
450    }
451    #[doc = "Selects ADCn_INPUT8 as negative channel input"]
452    #[inline(always)]
453    pub fn input8(self) -> &'a mut W {
454        self.variant(INPUT9NEGSEL_A::INPUT8)
455    }
456    #[doc = "Selects ADCn_INPUT10 as negative channel input"]
457    #[inline(always)]
458    pub fn input10(self) -> &'a mut W {
459        self.variant(INPUT9NEGSEL_A::INPUT10)
460    }
461    #[doc = "Selects ADCn_INPUT12 as negative channel input"]
462    #[inline(always)]
463    pub fn input12(self) -> &'a mut W {
464        self.variant(INPUT9NEGSEL_A::INPUT12)
465    }
466    #[doc = "Selects ADCn_INPUT14 as negative channel input"]
467    #[inline(always)]
468    pub fn input14(self) -> &'a mut W {
469        self.variant(INPUT9NEGSEL_A::INPUT14)
470    }
471    #[doc = r"Writes raw bits to the field"]
472    #[inline(always)]
473    pub fn bits(self, value: u8) -> &'a mut W {
474        self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
475        self.w
476    }
477}
478#[doc = "Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode\n\nValue on reset: 2"]
479#[derive(Clone, Copy, Debug, PartialEq)]
480#[repr(u8)]
481pub enum INPUT11NEGSEL_A {
482    #[doc = "0: Selects ADCn_INPUT8 as negative channel input"]
483    INPUT8 = 0,
484    #[doc = "1: Selects ADCn_INPUT10 as negative channel input"]
485    INPUT10 = 1,
486    #[doc = "2: Selects ADCn_INPUT12 as negative channel input"]
487    INPUT12 = 2,
488    #[doc = "3: Selects ADCn_INPUT14 as negative channel input"]
489    INPUT14 = 3,
490}
491impl From<INPUT11NEGSEL_A> for u8 {
492    #[inline(always)]
493    fn from(variant: INPUT11NEGSEL_A) -> Self {
494        variant as _
495    }
496}
497#[doc = "Reader of field `INPUT11NEGSEL`"]
498pub type INPUT11NEGSEL_R = crate::R<u8, INPUT11NEGSEL_A>;
499impl INPUT11NEGSEL_R {
500    #[doc = r"Get enumerated values variant"]
501    #[inline(always)]
502    pub fn variant(&self) -> INPUT11NEGSEL_A {
503        match self.bits {
504            0 => INPUT11NEGSEL_A::INPUT8,
505            1 => INPUT11NEGSEL_A::INPUT10,
506            2 => INPUT11NEGSEL_A::INPUT12,
507            3 => INPUT11NEGSEL_A::INPUT14,
508            _ => unreachable!(),
509        }
510    }
511    #[doc = "Checks if the value of the field is `INPUT8`"]
512    #[inline(always)]
513    pub fn is_input8(&self) -> bool {
514        *self == INPUT11NEGSEL_A::INPUT8
515    }
516    #[doc = "Checks if the value of the field is `INPUT10`"]
517    #[inline(always)]
518    pub fn is_input10(&self) -> bool {
519        *self == INPUT11NEGSEL_A::INPUT10
520    }
521    #[doc = "Checks if the value of the field is `INPUT12`"]
522    #[inline(always)]
523    pub fn is_input12(&self) -> bool {
524        *self == INPUT11NEGSEL_A::INPUT12
525    }
526    #[doc = "Checks if the value of the field is `INPUT14`"]
527    #[inline(always)]
528    pub fn is_input14(&self) -> bool {
529        *self == INPUT11NEGSEL_A::INPUT14
530    }
531}
532#[doc = "Write proxy for field `INPUT11NEGSEL`"]
533pub struct INPUT11NEGSEL_W<'a> {
534    w: &'a mut W,
535}
536impl<'a> INPUT11NEGSEL_W<'a> {
537    #[doc = r"Writes `variant` to the field"]
538    #[inline(always)]
539    pub fn variant(self, variant: INPUT11NEGSEL_A) -> &'a mut W {
540        {
541            self.bits(variant.into())
542        }
543    }
544    #[doc = "Selects ADCn_INPUT8 as negative channel input"]
545    #[inline(always)]
546    pub fn input8(self) -> &'a mut W {
547        self.variant(INPUT11NEGSEL_A::INPUT8)
548    }
549    #[doc = "Selects ADCn_INPUT10 as negative channel input"]
550    #[inline(always)]
551    pub fn input10(self) -> &'a mut W {
552        self.variant(INPUT11NEGSEL_A::INPUT10)
553    }
554    #[doc = "Selects ADCn_INPUT12 as negative channel input"]
555    #[inline(always)]
556    pub fn input12(self) -> &'a mut W {
557        self.variant(INPUT11NEGSEL_A::INPUT12)
558    }
559    #[doc = "Selects ADCn_INPUT14 as negative channel input"]
560    #[inline(always)]
561    pub fn input14(self) -> &'a mut W {
562        self.variant(INPUT11NEGSEL_A::INPUT14)
563    }
564    #[doc = r"Writes raw bits to the field"]
565    #[inline(always)]
566    pub fn bits(self, value: u8) -> &'a mut W {
567        self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
568        self.w
569    }
570}
571#[doc = "Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode\n\nValue on reset: 3"]
572#[derive(Clone, Copy, Debug, PartialEq)]
573#[repr(u8)]
574pub enum INPUT13NEGSEL_A {
575    #[doc = "0: Selects ADCn_INPUT8 as negative channel input"]
576    INPUT8 = 0,
577    #[doc = "1: Selects ADCn_INPUT10 as negative channel input"]
578    INPUT10 = 1,
579    #[doc = "2: Selects ADCn_INPUT12 as negative channel input"]
580    INPUT12 = 2,
581    #[doc = "3: Selects ADCn_INPUT14 as negative channel input"]
582    INPUT14 = 3,
583}
584impl From<INPUT13NEGSEL_A> for u8 {
585    #[inline(always)]
586    fn from(variant: INPUT13NEGSEL_A) -> Self {
587        variant as _
588    }
589}
590#[doc = "Reader of field `INPUT13NEGSEL`"]
591pub type INPUT13NEGSEL_R = crate::R<u8, INPUT13NEGSEL_A>;
592impl INPUT13NEGSEL_R {
593    #[doc = r"Get enumerated values variant"]
594    #[inline(always)]
595    pub fn variant(&self) -> INPUT13NEGSEL_A {
596        match self.bits {
597            0 => INPUT13NEGSEL_A::INPUT8,
598            1 => INPUT13NEGSEL_A::INPUT10,
599            2 => INPUT13NEGSEL_A::INPUT12,
600            3 => INPUT13NEGSEL_A::INPUT14,
601            _ => unreachable!(),
602        }
603    }
604    #[doc = "Checks if the value of the field is `INPUT8`"]
605    #[inline(always)]
606    pub fn is_input8(&self) -> bool {
607        *self == INPUT13NEGSEL_A::INPUT8
608    }
609    #[doc = "Checks if the value of the field is `INPUT10`"]
610    #[inline(always)]
611    pub fn is_input10(&self) -> bool {
612        *self == INPUT13NEGSEL_A::INPUT10
613    }
614    #[doc = "Checks if the value of the field is `INPUT12`"]
615    #[inline(always)]
616    pub fn is_input12(&self) -> bool {
617        *self == INPUT13NEGSEL_A::INPUT12
618    }
619    #[doc = "Checks if the value of the field is `INPUT14`"]
620    #[inline(always)]
621    pub fn is_input14(&self) -> bool {
622        *self == INPUT13NEGSEL_A::INPUT14
623    }
624}
625#[doc = "Write proxy for field `INPUT13NEGSEL`"]
626pub struct INPUT13NEGSEL_W<'a> {
627    w: &'a mut W,
628}
629impl<'a> INPUT13NEGSEL_W<'a> {
630    #[doc = r"Writes `variant` to the field"]
631    #[inline(always)]
632    pub fn variant(self, variant: INPUT13NEGSEL_A) -> &'a mut W {
633        {
634            self.bits(variant.into())
635        }
636    }
637    #[doc = "Selects ADCn_INPUT8 as negative channel input"]
638    #[inline(always)]
639    pub fn input8(self) -> &'a mut W {
640        self.variant(INPUT13NEGSEL_A::INPUT8)
641    }
642    #[doc = "Selects ADCn_INPUT10 as negative channel input"]
643    #[inline(always)]
644    pub fn input10(self) -> &'a mut W {
645        self.variant(INPUT13NEGSEL_A::INPUT10)
646    }
647    #[doc = "Selects ADCn_INPUT12 as negative channel input"]
648    #[inline(always)]
649    pub fn input12(self) -> &'a mut W {
650        self.variant(INPUT13NEGSEL_A::INPUT12)
651    }
652    #[doc = "Selects ADCn_INPUT14 as negative channel input"]
653    #[inline(always)]
654    pub fn input14(self) -> &'a mut W {
655        self.variant(INPUT13NEGSEL_A::INPUT14)
656    }
657    #[doc = r"Writes raw bits to the field"]
658    #[inline(always)]
659    pub fn bits(self, value: u8) -> &'a mut W {
660        self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
661        self.w
662    }
663}
664#[doc = "Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode\n\nValue on reset: 0"]
665#[derive(Clone, Copy, Debug, PartialEq)]
666#[repr(u8)]
667pub enum INPUT15NEGSEL_A {
668    #[doc = "0: Selects ADCn_INPUT8 as negative channel input"]
669    INPUT8 = 0,
670    #[doc = "1: Selects ADCn_INPUT10 as negative channel input"]
671    INPUT10 = 1,
672    #[doc = "2: Selects ADCn_INPUT12 as negative channel input"]
673    INPUT12 = 2,
674    #[doc = "3: Selects ADCn_INPUT14 as negative channel input"]
675    INPUT14 = 3,
676}
677impl From<INPUT15NEGSEL_A> for u8 {
678    #[inline(always)]
679    fn from(variant: INPUT15NEGSEL_A) -> Self {
680        variant as _
681    }
682}
683#[doc = "Reader of field `INPUT15NEGSEL`"]
684pub type INPUT15NEGSEL_R = crate::R<u8, INPUT15NEGSEL_A>;
685impl INPUT15NEGSEL_R {
686    #[doc = r"Get enumerated values variant"]
687    #[inline(always)]
688    pub fn variant(&self) -> INPUT15NEGSEL_A {
689        match self.bits {
690            0 => INPUT15NEGSEL_A::INPUT8,
691            1 => INPUT15NEGSEL_A::INPUT10,
692            2 => INPUT15NEGSEL_A::INPUT12,
693            3 => INPUT15NEGSEL_A::INPUT14,
694            _ => unreachable!(),
695        }
696    }
697    #[doc = "Checks if the value of the field is `INPUT8`"]
698    #[inline(always)]
699    pub fn is_input8(&self) -> bool {
700        *self == INPUT15NEGSEL_A::INPUT8
701    }
702    #[doc = "Checks if the value of the field is `INPUT10`"]
703    #[inline(always)]
704    pub fn is_input10(&self) -> bool {
705        *self == INPUT15NEGSEL_A::INPUT10
706    }
707    #[doc = "Checks if the value of the field is `INPUT12`"]
708    #[inline(always)]
709    pub fn is_input12(&self) -> bool {
710        *self == INPUT15NEGSEL_A::INPUT12
711    }
712    #[doc = "Checks if the value of the field is `INPUT14`"]
713    #[inline(always)]
714    pub fn is_input14(&self) -> bool {
715        *self == INPUT15NEGSEL_A::INPUT14
716    }
717}
718#[doc = "Write proxy for field `INPUT15NEGSEL`"]
719pub struct INPUT15NEGSEL_W<'a> {
720    w: &'a mut W,
721}
722impl<'a> INPUT15NEGSEL_W<'a> {
723    #[doc = r"Writes `variant` to the field"]
724    #[inline(always)]
725    pub fn variant(self, variant: INPUT15NEGSEL_A) -> &'a mut W {
726        {
727            self.bits(variant.into())
728        }
729    }
730    #[doc = "Selects ADCn_INPUT8 as negative channel input"]
731    #[inline(always)]
732    pub fn input8(self) -> &'a mut W {
733        self.variant(INPUT15NEGSEL_A::INPUT8)
734    }
735    #[doc = "Selects ADCn_INPUT10 as negative channel input"]
736    #[inline(always)]
737    pub fn input10(self) -> &'a mut W {
738        self.variant(INPUT15NEGSEL_A::INPUT10)
739    }
740    #[doc = "Selects ADCn_INPUT12 as negative channel input"]
741    #[inline(always)]
742    pub fn input12(self) -> &'a mut W {
743        self.variant(INPUT15NEGSEL_A::INPUT12)
744    }
745    #[doc = "Selects ADCn_INPUT14 as negative channel input"]
746    #[inline(always)]
747    pub fn input14(self) -> &'a mut W {
748        self.variant(INPUT15NEGSEL_A::INPUT14)
749    }
750    #[doc = r"Writes raw bits to the field"]
751    #[inline(always)]
752    pub fn bits(self, value: u8) -> &'a mut W {
753        self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14);
754        self.w
755    }
756}
757impl R {
758    #[doc = "Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode"]
759    #[inline(always)]
760    pub fn input0negsel(&self) -> INPUT0NEGSEL_R {
761        INPUT0NEGSEL_R::new((self.bits & 0x03) as u8)
762    }
763    #[doc = "Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode"]
764    #[inline(always)]
765    pub fn input2negsel(&self) -> INPUT2NEGSEL_R {
766        INPUT2NEGSEL_R::new(((self.bits >> 2) & 0x03) as u8)
767    }
768    #[doc = "Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode"]
769    #[inline(always)]
770    pub fn input4negsel(&self) -> INPUT4NEGSEL_R {
771        INPUT4NEGSEL_R::new(((self.bits >> 4) & 0x03) as u8)
772    }
773    #[doc = "Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode"]
774    #[inline(always)]
775    pub fn input6negsel(&self) -> INPUT6NEGSEL_R {
776        INPUT6NEGSEL_R::new(((self.bits >> 6) & 0x03) as u8)
777    }
778    #[doc = "Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode"]
779    #[inline(always)]
780    pub fn input9negsel(&self) -> INPUT9NEGSEL_R {
781        INPUT9NEGSEL_R::new(((self.bits >> 8) & 0x03) as u8)
782    }
783    #[doc = "Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode"]
784    #[inline(always)]
785    pub fn input11negsel(&self) -> INPUT11NEGSEL_R {
786        INPUT11NEGSEL_R::new(((self.bits >> 10) & 0x03) as u8)
787    }
788    #[doc = "Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode"]
789    #[inline(always)]
790    pub fn input13negsel(&self) -> INPUT13NEGSEL_R {
791        INPUT13NEGSEL_R::new(((self.bits >> 12) & 0x03) as u8)
792    }
793    #[doc = "Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode"]
794    #[inline(always)]
795    pub fn input15negsel(&self) -> INPUT15NEGSEL_R {
796        INPUT15NEGSEL_R::new(((self.bits >> 14) & 0x03) as u8)
797    }
798}
799impl W {
800    #[doc = "Bits 0:1 - Negative Input Select Register for ADCn_INPUT0 in Differential Scan Mode"]
801    #[inline(always)]
802    pub fn input0negsel(&mut self) -> INPUT0NEGSEL_W {
803        INPUT0NEGSEL_W { w: self }
804    }
805    #[doc = "Bits 2:3 - Negative Input Select Register for ADCn_INPUT2 in Differential Scan Mode"]
806    #[inline(always)]
807    pub fn input2negsel(&mut self) -> INPUT2NEGSEL_W {
808        INPUT2NEGSEL_W { w: self }
809    }
810    #[doc = "Bits 4:5 - Negative Input Select Register for ADCn_INPUT4 in Differential Scan Mode"]
811    #[inline(always)]
812    pub fn input4negsel(&mut self) -> INPUT4NEGSEL_W {
813        INPUT4NEGSEL_W { w: self }
814    }
815    #[doc = "Bits 6:7 - Negative Input Select Register for ADCn_INPUT1 in Differential Scan Mode"]
816    #[inline(always)]
817    pub fn input6negsel(&mut self) -> INPUT6NEGSEL_W {
818        INPUT6NEGSEL_W { w: self }
819    }
820    #[doc = "Bits 8:9 - Negative Input Select Register for ADCn_INPUT9 in Differential Scan Mode"]
821    #[inline(always)]
822    pub fn input9negsel(&mut self) -> INPUT9NEGSEL_W {
823        INPUT9NEGSEL_W { w: self }
824    }
825    #[doc = "Bits 10:11 - Negative Input Select Register for ADCn_INPUT11 in Differential Scan Mode"]
826    #[inline(always)]
827    pub fn input11negsel(&mut self) -> INPUT11NEGSEL_W {
828        INPUT11NEGSEL_W { w: self }
829    }
830    #[doc = "Bits 12:13 - Negative Input Select Register for ADCn_INPUT13 in Differential Scan Mode"]
831    #[inline(always)]
832    pub fn input13negsel(&mut self) -> INPUT13NEGSEL_W {
833        INPUT13NEGSEL_W { w: self }
834    }
835    #[doc = "Bits 14:15 - Negative Input Select Register for ADCn_INPUT15 in Differential Scan Mode"]
836    #[inline(always)]
837    pub fn input15negsel(&mut self) -> INPUT15NEGSEL_W {
838        INPUT15NEGSEL_W { w: self }
839    }
840}
efm32pg12_pac/adc0/scannegsel.rs

efm32pg12_pac/adc0/
scannegsel.rs
