efm32pg12_pac/msc/
cacheconfig0.rs

1#[doc = "Reader of register CACHECONFIG0"]
2pub type R = crate::R<u32, super::CACHECONFIG0>;
3#[doc = "Writer for register CACHECONFIG0"]
4pub type W = crate::W<u32, super::CACHECONFIG0>;
5#[doc = "Register CACHECONFIG0 `reset()`'s with value 0x03"]
6impl crate::ResetValue for super::CACHECONFIG0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x03
11    }
12}
13#[doc = "Instruction Cache Low-Power Level\n\nValue on reset: 3"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum CACHELPLEVEL_A {
17    #[doc = "0: Base instruction cache functionality."]
18    BASE = 0,
19    #[doc = "1: Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory."]
20    ADVANCED = 1,
21    #[doc = "3: Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
22    MINACTIVITY = 3,
23}
24impl From<CACHELPLEVEL_A> for u8 {
25    #[inline(always)]
26    fn from(variant: CACHELPLEVEL_A) -> Self {
27        variant as _
28    }
29}
30#[doc = "Reader of field `CACHELPLEVEL`"]
31pub type CACHELPLEVEL_R = crate::R<u8, CACHELPLEVEL_A>;
32impl CACHELPLEVEL_R {
33    #[doc = r"Get enumerated values variant"]
34    #[inline(always)]
35    pub fn variant(&self) -> crate::Variant<u8, CACHELPLEVEL_A> {
36        use crate::Variant::*;
37        match self.bits {
38            0 => Val(CACHELPLEVEL_A::BASE),
39            1 => Val(CACHELPLEVEL_A::ADVANCED),
40            3 => Val(CACHELPLEVEL_A::MINACTIVITY),
41            i => Res(i),
42        }
43    }
44    #[doc = "Checks if the value of the field is `BASE`"]
45    #[inline(always)]
46    pub fn is_base(&self) -> bool {
47        *self == CACHELPLEVEL_A::BASE
48    }
49    #[doc = "Checks if the value of the field is `ADVANCED`"]
50    #[inline(always)]
51    pub fn is_advanced(&self) -> bool {
52        *self == CACHELPLEVEL_A::ADVANCED
53    }
54    #[doc = "Checks if the value of the field is `MINACTIVITY`"]
55    #[inline(always)]
56    pub fn is_minactivity(&self) -> bool {
57        *self == CACHELPLEVEL_A::MINACTIVITY
58    }
59}
60#[doc = "Write proxy for field `CACHELPLEVEL`"]
61pub struct CACHELPLEVEL_W<'a> {
62    w: &'a mut W,
63}
64impl<'a> CACHELPLEVEL_W<'a> {
65    #[doc = r"Writes `variant` to the field"]
66    #[inline(always)]
67    pub fn variant(self, variant: CACHELPLEVEL_A) -> &'a mut W {
68        unsafe { self.bits(variant.into()) }
69    }
70    #[doc = "Base instruction cache functionality."]
71    #[inline(always)]
72    pub fn base(self) -> &'a mut W {
73        self.variant(CACHELPLEVEL_A::BASE)
74    }
75    #[doc = "Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory."]
76    #[inline(always)]
77    pub fn advanced(self) -> &'a mut W {
78        self.variant(CACHELPLEVEL_A::ADVANCED)
79    }
80    #[doc = "Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
81    #[inline(always)]
82    pub fn minactivity(self) -> &'a mut W {
83        self.variant(CACHELPLEVEL_A::MINACTIVITY)
84    }
85    #[doc = r"Writes raw bits to the field"]
86    #[inline(always)]
87    pub unsafe fn bits(self, value: u8) -> &'a mut W {
88        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
89        self.w
90    }
91}
92impl R {
93    #[doc = "Bits 0:1 - Instruction Cache Low-Power Level"]
94    #[inline(always)]
95    pub fn cachelplevel(&self) -> CACHELPLEVEL_R {
96        CACHELPLEVEL_R::new((self.bits & 0x03) as u8)
97    }
98}
99impl W {
100    #[doc = "Bits 0:1 - Instruction Cache Low-Power Level"]
101    #[inline(always)]
102    pub fn cachelplevel(&mut self) -> CACHELPLEVEL_W {
103        CACHELPLEVEL_W { w: self }
104    }
105}
efm32pg12_pac/msc/cacheconfig0.rs

efm32pg12_pac/msc/
cacheconfig0.rs
