1#[doc = "Reader of register SINGLECTRL"]
2pub type R = crate::R<u32, super::SINGLECTRL>;
3#[doc = "Writer for register SINGLECTRL"]
4pub type W = crate::W<u32, super::SINGLECTRL>;
5#[doc = "Register SINGLECTRL `reset()`'s with value 0x00ff_ff00"]
6impl crate::ResetValue for super::SINGLECTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x00ff_ff00
11 }
12}
13#[doc = "Reader of field `REP`"]
14pub type REP_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `REP`"]
16pub struct REP_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> REP_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `DIFF`"]
38pub type DIFF_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DIFF`"]
40pub struct DIFF_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> DIFF_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `ADJ`"]
62pub type ADJ_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `ADJ`"]
64pub struct ADJ_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> ADJ_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82 self.w
83 }
84}
85#[doc = "Single Channel Resolution Select\n\nValue on reset: 0"]
86#[derive(Clone, Copy, Debug, PartialEq)]
87#[repr(u8)]
88pub enum RES_A {
89 #[doc = "0: 12-bit resolution."]
90 _12BIT = 0,
91 #[doc = "1: 8-bit resolution."]
92 _8BIT = 1,
93 #[doc = "2: 6-bit resolution."]
94 _6BIT = 2,
95 #[doc = "3: Oversampling enabled. Oversampling rate is set in OVSRSEL."]
96 OVS = 3,
97}
98impl From<RES_A> for u8 {
99 #[inline(always)]
100 fn from(variant: RES_A) -> Self {
101 variant as _
102 }
103}
104#[doc = "Reader of field `RES`"]
105pub type RES_R = crate::R<u8, RES_A>;
106impl RES_R {
107 #[doc = r"Get enumerated values variant"]
108 #[inline(always)]
109 pub fn variant(&self) -> RES_A {
110 match self.bits {
111 0 => RES_A::_12BIT,
112 1 => RES_A::_8BIT,
113 2 => RES_A::_6BIT,
114 3 => RES_A::OVS,
115 _ => unreachable!(),
116 }
117 }
118 #[doc = "Checks if the value of the field is `_12BIT`"]
119 #[inline(always)]
120 pub fn is_12bit(&self) -> bool {
121 *self == RES_A::_12BIT
122 }
123 #[doc = "Checks if the value of the field is `_8BIT`"]
124 #[inline(always)]
125 pub fn is_8bit(&self) -> bool {
126 *self == RES_A::_8BIT
127 }
128 #[doc = "Checks if the value of the field is `_6BIT`"]
129 #[inline(always)]
130 pub fn is_6bit(&self) -> bool {
131 *self == RES_A::_6BIT
132 }
133 #[doc = "Checks if the value of the field is `OVS`"]
134 #[inline(always)]
135 pub fn is_ovs(&self) -> bool {
136 *self == RES_A::OVS
137 }
138}
139#[doc = "Write proxy for field `RES`"]
140pub struct RES_W<'a> {
141 w: &'a mut W,
142}
143impl<'a> RES_W<'a> {
144 #[doc = r"Writes `variant` to the field"]
145 #[inline(always)]
146 pub fn variant(self, variant: RES_A) -> &'a mut W {
147 {
148 self.bits(variant.into())
149 }
150 }
151 #[doc = "12-bit resolution."]
152 #[inline(always)]
153 pub fn _12bit(self) -> &'a mut W {
154 self.variant(RES_A::_12BIT)
155 }
156 #[doc = "8-bit resolution."]
157 #[inline(always)]
158 pub fn _8bit(self) -> &'a mut W {
159 self.variant(RES_A::_8BIT)
160 }
161 #[doc = "6-bit resolution."]
162 #[inline(always)]
163 pub fn _6bit(self) -> &'a mut W {
164 self.variant(RES_A::_6BIT)
165 }
166 #[doc = "Oversampling enabled. Oversampling rate is set in OVSRSEL."]
167 #[inline(always)]
168 pub fn ovs(self) -> &'a mut W {
169 self.variant(RES_A::OVS)
170 }
171 #[doc = r"Writes raw bits to the field"]
172 #[inline(always)]
173 pub fn bits(self, value: u8) -> &'a mut W {
174 self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
175 self.w
176 }
177}
178#[doc = "Single Channel Reference Selection\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq)]
180#[repr(u8)]
181pub enum REF_A {
182 #[doc = "0: VFS = 1.25V with internal VBGR reference"]
183 _1V25 = 0,
184 #[doc = "1: VFS = 2.5V with internal VBGR reference"]
185 _2V5 = 1,
186 #[doc = "2: VFS = AVDD with AVDD as reference source"]
187 VDD = 2,
188 #[doc = "3: VFS = 5V with internal VBGR reference"]
189 _5V = 3,
190 #[doc = "4: Single ended external reference"]
191 EXTSINGLE = 4,
192 #[doc = "5: Differential external reference, 2x"]
193 _2XEXTDIFF = 5,
194 #[doc = "6: VFS = 2xAVDD with AVDD as the reference source"]
195 _2XVDD = 6,
196 #[doc = "7: Use SINGLECTRLX to configure reference"]
197 CONF = 7,
198}
199impl From<REF_A> for u8 {
200 #[inline(always)]
201 fn from(variant: REF_A) -> Self {
202 variant as _
203 }
204}
205#[doc = "Reader of field `REF`"]
206pub type REF_R = crate::R<u8, REF_A>;
207impl REF_R {
208 #[doc = r"Get enumerated values variant"]
209 #[inline(always)]
210 pub fn variant(&self) -> REF_A {
211 match self.bits {
212 0 => REF_A::_1V25,
213 1 => REF_A::_2V5,
214 2 => REF_A::VDD,
215 3 => REF_A::_5V,
216 4 => REF_A::EXTSINGLE,
217 5 => REF_A::_2XEXTDIFF,
218 6 => REF_A::_2XVDD,
219 7 => REF_A::CONF,
220 _ => unreachable!(),
221 }
222 }
223 #[doc = "Checks if the value of the field is `_1V25`"]
224 #[inline(always)]
225 pub fn is_1v25(&self) -> bool {
226 *self == REF_A::_1V25
227 }
228 #[doc = "Checks if the value of the field is `_2V5`"]
229 #[inline(always)]
230 pub fn is_2v5(&self) -> bool {
231 *self == REF_A::_2V5
232 }
233 #[doc = "Checks if the value of the field is `VDD`"]
234 #[inline(always)]
235 pub fn is_vdd(&self) -> bool {
236 *self == REF_A::VDD
237 }
238 #[doc = "Checks if the value of the field is `_5V`"]
239 #[inline(always)]
240 pub fn is_5v(&self) -> bool {
241 *self == REF_A::_5V
242 }
243 #[doc = "Checks if the value of the field is `EXTSINGLE`"]
244 #[inline(always)]
245 pub fn is_extsingle(&self) -> bool {
246 *self == REF_A::EXTSINGLE
247 }
248 #[doc = "Checks if the value of the field is `_2XEXTDIFF`"]
249 #[inline(always)]
250 pub fn is_2xextdiff(&self) -> bool {
251 *self == REF_A::_2XEXTDIFF
252 }
253 #[doc = "Checks if the value of the field is `_2XVDD`"]
254 #[inline(always)]
255 pub fn is_2xvdd(&self) -> bool {
256 *self == REF_A::_2XVDD
257 }
258 #[doc = "Checks if the value of the field is `CONF`"]
259 #[inline(always)]
260 pub fn is_conf(&self) -> bool {
261 *self == REF_A::CONF
262 }
263}
264#[doc = "Write proxy for field `REF`"]
265pub struct REF_W<'a> {
266 w: &'a mut W,
267}
268impl<'a> REF_W<'a> {
269 #[doc = r"Writes `variant` to the field"]
270 #[inline(always)]
271 pub fn variant(self, variant: REF_A) -> &'a mut W {
272 {
273 self.bits(variant.into())
274 }
275 }
276 #[doc = "VFS = 1.25V with internal VBGR reference"]
277 #[inline(always)]
278 pub fn _1v25(self) -> &'a mut W {
279 self.variant(REF_A::_1V25)
280 }
281 #[doc = "VFS = 2.5V with internal VBGR reference"]
282 #[inline(always)]
283 pub fn _2v5(self) -> &'a mut W {
284 self.variant(REF_A::_2V5)
285 }
286 #[doc = "VFS = AVDD with AVDD as reference source"]
287 #[inline(always)]
288 pub fn vdd(self) -> &'a mut W {
289 self.variant(REF_A::VDD)
290 }
291 #[doc = "VFS = 5V with internal VBGR reference"]
292 #[inline(always)]
293 pub fn _5v(self) -> &'a mut W {
294 self.variant(REF_A::_5V)
295 }
296 #[doc = "Single ended external reference"]
297 #[inline(always)]
298 pub fn extsingle(self) -> &'a mut W {
299 self.variant(REF_A::EXTSINGLE)
300 }
301 #[doc = "Differential external reference, 2x"]
302 #[inline(always)]
303 pub fn _2xextdiff(self) -> &'a mut W {
304 self.variant(REF_A::_2XEXTDIFF)
305 }
306 #[doc = "VFS = 2xAVDD with AVDD as the reference source"]
307 #[inline(always)]
308 pub fn _2xvdd(self) -> &'a mut W {
309 self.variant(REF_A::_2XVDD)
310 }
311 #[doc = "Use SINGLECTRLX to configure reference"]
312 #[inline(always)]
313 pub fn conf(self) -> &'a mut W {
314 self.variant(REF_A::CONF)
315 }
316 #[doc = r"Writes raw bits to the field"]
317 #[inline(always)]
318 pub fn bits(self, value: u8) -> &'a mut W {
319 self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5);
320 self.w
321 }
322}
323#[doc = "Reader of field `POSSEL`"]
324pub type POSSEL_R = crate::R<u8, u8>;
325#[doc = "Write proxy for field `POSSEL`"]
326pub struct POSSEL_W<'a> {
327 w: &'a mut W,
328}
329impl<'a> POSSEL_W<'a> {
330 #[doc = r"Writes raw bits to the field"]
331 #[inline(always)]
332 pub unsafe fn bits(self, value: u8) -> &'a mut W {
333 self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
334 self.w
335 }
336}
337#[doc = "Reader of field `NEGSEL`"]
338pub type NEGSEL_R = crate::R<u8, u8>;
339#[doc = "Write proxy for field `NEGSEL`"]
340pub struct NEGSEL_W<'a> {
341 w: &'a mut W,
342}
343impl<'a> NEGSEL_W<'a> {
344 #[doc = r"Writes raw bits to the field"]
345 #[inline(always)]
346 pub unsafe fn bits(self, value: u8) -> &'a mut W {
347 self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
348 self.w
349 }
350}
351#[doc = "Single Channel Acquisition Time\n\nValue on reset: 0"]
352#[derive(Clone, Copy, Debug, PartialEq)]
353#[repr(u8)]
354pub enum AT_A {
355 #[doc = "0: 1 conversion clock cycle acquisition time for single channel"]
356 _1CYCLE = 0,
357 #[doc = "1: 2 conversion clock cycles acquisition time for single channel"]
358 _2CYCLES = 1,
359 #[doc = "2: 3 conversion clock cycles acquisition time for single channel"]
360 _3CYCLES = 2,
361 #[doc = "3: 4 conversion clock cycles acquisition time for single channel"]
362 _4CYCLES = 3,
363 #[doc = "4: 8 conversion clock cycles acquisition time for single channel"]
364 _8CYCLES = 4,
365 #[doc = "5: 16 conversion clock cycles acquisition time for single channel"]
366 _16CYCLES = 5,
367 #[doc = "6: 32 conversion clock cycles acquisition time for single channel"]
368 _32CYCLES = 6,
369 #[doc = "7: 64 conversion clock cycles acquisition time for single channel"]
370 _64CYCLES = 7,
371 #[doc = "8: 128 conversion clock cycles acquisition time for single channel"]
372 _128CYCLES = 8,
373 #[doc = "9: 256 conversion clock cycles acquisition time for single channel"]
374 _256CYCLES = 9,
375}
376impl From<AT_A> for u8 {
377 #[inline(always)]
378 fn from(variant: AT_A) -> Self {
379 variant as _
380 }
381}
382#[doc = "Reader of field `AT`"]
383pub type AT_R = crate::R<u8, AT_A>;
384impl AT_R {
385 #[doc = r"Get enumerated values variant"]
386 #[inline(always)]
387 pub fn variant(&self) -> crate::Variant<u8, AT_A> {
388 use crate::Variant::*;
389 match self.bits {
390 0 => Val(AT_A::_1CYCLE),
391 1 => Val(AT_A::_2CYCLES),
392 2 => Val(AT_A::_3CYCLES),
393 3 => Val(AT_A::_4CYCLES),
394 4 => Val(AT_A::_8CYCLES),
395 5 => Val(AT_A::_16CYCLES),
396 6 => Val(AT_A::_32CYCLES),
397 7 => Val(AT_A::_64CYCLES),
398 8 => Val(AT_A::_128CYCLES),
399 9 => Val(AT_A::_256CYCLES),
400 i => Res(i),
401 }
402 }
403 #[doc = "Checks if the value of the field is `_1CYCLE`"]
404 #[inline(always)]
405 pub fn is_1cycle(&self) -> bool {
406 *self == AT_A::_1CYCLE
407 }
408 #[doc = "Checks if the value of the field is `_2CYCLES`"]
409 #[inline(always)]
410 pub fn is_2cycles(&self) -> bool {
411 *self == AT_A::_2CYCLES
412 }
413 #[doc = "Checks if the value of the field is `_3CYCLES`"]
414 #[inline(always)]
415 pub fn is_3cycles(&self) -> bool {
416 *self == AT_A::_3CYCLES
417 }
418 #[doc = "Checks if the value of the field is `_4CYCLES`"]
419 #[inline(always)]
420 pub fn is_4cycles(&self) -> bool {
421 *self == AT_A::_4CYCLES
422 }
423 #[doc = "Checks if the value of the field is `_8CYCLES`"]
424 #[inline(always)]
425 pub fn is_8cycles(&self) -> bool {
426 *self == AT_A::_8CYCLES
427 }
428 #[doc = "Checks if the value of the field is `_16CYCLES`"]
429 #[inline(always)]
430 pub fn is_16cycles(&self) -> bool {
431 *self == AT_A::_16CYCLES
432 }
433 #[doc = "Checks if the value of the field is `_32CYCLES`"]
434 #[inline(always)]
435 pub fn is_32cycles(&self) -> bool {
436 *self == AT_A::_32CYCLES
437 }
438 #[doc = "Checks if the value of the field is `_64CYCLES`"]
439 #[inline(always)]
440 pub fn is_64cycles(&self) -> bool {
441 *self == AT_A::_64CYCLES
442 }
443 #[doc = "Checks if the value of the field is `_128CYCLES`"]
444 #[inline(always)]
445 pub fn is_128cycles(&self) -> bool {
446 *self == AT_A::_128CYCLES
447 }
448 #[doc = "Checks if the value of the field is `_256CYCLES`"]
449 #[inline(always)]
450 pub fn is_256cycles(&self) -> bool {
451 *self == AT_A::_256CYCLES
452 }
453}
454#[doc = "Write proxy for field `AT`"]
455pub struct AT_W<'a> {
456 w: &'a mut W,
457}
458impl<'a> AT_W<'a> {
459 #[doc = r"Writes `variant` to the field"]
460 #[inline(always)]
461 pub fn variant(self, variant: AT_A) -> &'a mut W {
462 unsafe { self.bits(variant.into()) }
463 }
464 #[doc = "1 conversion clock cycle acquisition time for single channel"]
465 #[inline(always)]
466 pub fn _1cycle(self) -> &'a mut W {
467 self.variant(AT_A::_1CYCLE)
468 }
469 #[doc = "2 conversion clock cycles acquisition time for single channel"]
470 #[inline(always)]
471 pub fn _2cycles(self) -> &'a mut W {
472 self.variant(AT_A::_2CYCLES)
473 }
474 #[doc = "3 conversion clock cycles acquisition time for single channel"]
475 #[inline(always)]
476 pub fn _3cycles(self) -> &'a mut W {
477 self.variant(AT_A::_3CYCLES)
478 }
479 #[doc = "4 conversion clock cycles acquisition time for single channel"]
480 #[inline(always)]
481 pub fn _4cycles(self) -> &'a mut W {
482 self.variant(AT_A::_4CYCLES)
483 }
484 #[doc = "8 conversion clock cycles acquisition time for single channel"]
485 #[inline(always)]
486 pub fn _8cycles(self) -> &'a mut W {
487 self.variant(AT_A::_8CYCLES)
488 }
489 #[doc = "16 conversion clock cycles acquisition time for single channel"]
490 #[inline(always)]
491 pub fn _16cycles(self) -> &'a mut W {
492 self.variant(AT_A::_16CYCLES)
493 }
494 #[doc = "32 conversion clock cycles acquisition time for single channel"]
495 #[inline(always)]
496 pub fn _32cycles(self) -> &'a mut W {
497 self.variant(AT_A::_32CYCLES)
498 }
499 #[doc = "64 conversion clock cycles acquisition time for single channel"]
500 #[inline(always)]
501 pub fn _64cycles(self) -> &'a mut W {
502 self.variant(AT_A::_64CYCLES)
503 }
504 #[doc = "128 conversion clock cycles acquisition time for single channel"]
505 #[inline(always)]
506 pub fn _128cycles(self) -> &'a mut W {
507 self.variant(AT_A::_128CYCLES)
508 }
509 #[doc = "256 conversion clock cycles acquisition time for single channel"]
510 #[inline(always)]
511 pub fn _256cycles(self) -> &'a mut W {
512 self.variant(AT_A::_256CYCLES)
513 }
514 #[doc = r"Writes raw bits to the field"]
515 #[inline(always)]
516 pub unsafe fn bits(self, value: u8) -> &'a mut W {
517 self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
518 self.w
519 }
520}
521#[doc = "Reader of field `PRSEN`"]
522pub type PRSEN_R = crate::R<bool, bool>;
523#[doc = "Write proxy for field `PRSEN`"]
524pub struct PRSEN_W<'a> {
525 w: &'a mut W,
526}
527impl<'a> PRSEN_W<'a> {
528 #[doc = r"Sets the field bit"]
529 #[inline(always)]
530 pub fn set_bit(self) -> &'a mut W {
531 self.bit(true)
532 }
533 #[doc = r"Clears the field bit"]
534 #[inline(always)]
535 pub fn clear_bit(self) -> &'a mut W {
536 self.bit(false)
537 }
538 #[doc = r"Writes raw bits to the field"]
539 #[inline(always)]
540 pub fn bit(self, value: bool) -> &'a mut W {
541 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
542 self.w
543 }
544}
545#[doc = "Reader of field `CMPEN`"]
546pub type CMPEN_R = crate::R<bool, bool>;
547#[doc = "Write proxy for field `CMPEN`"]
548pub struct CMPEN_W<'a> {
549 w: &'a mut W,
550}
551impl<'a> CMPEN_W<'a> {
552 #[doc = r"Sets the field bit"]
553 #[inline(always)]
554 pub fn set_bit(self) -> &'a mut W {
555 self.bit(true)
556 }
557 #[doc = r"Clears the field bit"]
558 #[inline(always)]
559 pub fn clear_bit(self) -> &'a mut W {
560 self.bit(false)
561 }
562 #[doc = r"Writes raw bits to the field"]
563 #[inline(always)]
564 pub fn bit(self, value: bool) -> &'a mut W {
565 self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
566 self.w
567 }
568}
569impl R {
570 #[doc = "Bit 0 - Single Channel Repetitive Mode"]
571 #[inline(always)]
572 pub fn rep(&self) -> REP_R {
573 REP_R::new((self.bits & 0x01) != 0)
574 }
575 #[doc = "Bit 1 - Single Channel Differential Mode"]
576 #[inline(always)]
577 pub fn diff(&self) -> DIFF_R {
578 DIFF_R::new(((self.bits >> 1) & 0x01) != 0)
579 }
580 #[doc = "Bit 2 - Single Channel Result Adjustment"]
581 #[inline(always)]
582 pub fn adj(&self) -> ADJ_R {
583 ADJ_R::new(((self.bits >> 2) & 0x01) != 0)
584 }
585 #[doc = "Bits 3:4 - Single Channel Resolution Select"]
586 #[inline(always)]
587 pub fn res(&self) -> RES_R {
588 RES_R::new(((self.bits >> 3) & 0x03) as u8)
589 }
590 #[doc = "Bits 5:7 - Single Channel Reference Selection"]
591 #[inline(always)]
592 pub fn ref_(&self) -> REF_R {
593 REF_R::new(((self.bits >> 5) & 0x07) as u8)
594 }
595 #[doc = "Bits 8:15 - Single Channel Positive Input Selection"]
596 #[inline(always)]
597 pub fn possel(&self) -> POSSEL_R {
598 POSSEL_R::new(((self.bits >> 8) & 0xff) as u8)
599 }
600 #[doc = "Bits 16:23 - Single Channel Negative Input Selection"]
601 #[inline(always)]
602 pub fn negsel(&self) -> NEGSEL_R {
603 NEGSEL_R::new(((self.bits >> 16) & 0xff) as u8)
604 }
605 #[doc = "Bits 24:27 - Single Channel Acquisition Time"]
606 #[inline(always)]
607 pub fn at(&self) -> AT_R {
608 AT_R::new(((self.bits >> 24) & 0x0f) as u8)
609 }
610 #[doc = "Bit 29 - Single Channel PRS Trigger Enable"]
611 #[inline(always)]
612 pub fn prsen(&self) -> PRSEN_R {
613 PRSEN_R::new(((self.bits >> 29) & 0x01) != 0)
614 }
615 #[doc = "Bit 31 - Compare Logic Enable for Single Channel"]
616 #[inline(always)]
617 pub fn cmpen(&self) -> CMPEN_R {
618 CMPEN_R::new(((self.bits >> 31) & 0x01) != 0)
619 }
620}
621impl W {
622 #[doc = "Bit 0 - Single Channel Repetitive Mode"]
623 #[inline(always)]
624 pub fn rep(&mut self) -> REP_W {
625 REP_W { w: self }
626 }
627 #[doc = "Bit 1 - Single Channel Differential Mode"]
628 #[inline(always)]
629 pub fn diff(&mut self) -> DIFF_W {
630 DIFF_W { w: self }
631 }
632 #[doc = "Bit 2 - Single Channel Result Adjustment"]
633 #[inline(always)]
634 pub fn adj(&mut self) -> ADJ_W {
635 ADJ_W { w: self }
636 }
637 #[doc = "Bits 3:4 - Single Channel Resolution Select"]
638 #[inline(always)]
639 pub fn res(&mut self) -> RES_W {
640 RES_W { w: self }
641 }
642 #[doc = "Bits 5:7 - Single Channel Reference Selection"]
643 #[inline(always)]
644 pub fn ref_(&mut self) -> REF_W {
645 REF_W { w: self }
646 }
647 #[doc = "Bits 8:15 - Single Channel Positive Input Selection"]
648 #[inline(always)]
649 pub fn possel(&mut self) -> POSSEL_W {
650 POSSEL_W { w: self }
651 }
652 #[doc = "Bits 16:23 - Single Channel Negative Input Selection"]
653 #[inline(always)]
654 pub fn negsel(&mut self) -> NEGSEL_W {
655 NEGSEL_W { w: self }
656 }
657 #[doc = "Bits 24:27 - Single Channel Acquisition Time"]
658 #[inline(always)]
659 pub fn at(&mut self) -> AT_W {
660 AT_W { w: self }
661 }
662 #[doc = "Bit 29 - Single Channel PRS Trigger Enable"]
663 #[inline(always)]
664 pub fn prsen(&mut self) -> PRSEN_W {
665 PRSEN_W { w: self }
666 }
667 #[doc = "Bit 31 - Compare Logic Enable for Single Channel"]
668 #[inline(always)]
669 pub fn cmpen(&mut self) -> CMPEN_W {
670 CMPEN_W { w: self }
671 }
672}