efm32pg12_pac/cmu/
lfepresc0.rs

1#[doc = "Reader of register LFEPRESC0"]
2pub type R = crate::R<u32, super::LFEPRESC0>;
3#[doc = "Writer for register LFEPRESC0"]
4pub type W = crate::W<u32, super::LFEPRESC0>;
5#[doc = "Register LFEPRESC0 `reset()`'s with value 0"]
6impl crate::ResetValue for super::LFEPRESC0 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Real-Time Counter and Calendar Prescaler\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum RTCC_A {
17    #[doc = "0: LFECLKRTCC = LFECLK"]
18    DIV1 = 0,
19    #[doc = "1: LFECLKRTCC = LFECLK/2"]
20    DIV2 = 1,
21    #[doc = "2: LFECLKRTCC = LFECLK/4"]
22    DIV4 = 2,
23}
24impl From<RTCC_A> for u8 {
25    #[inline(always)]
26    fn from(variant: RTCC_A) -> Self {
27        variant as _
28    }
29}
30#[doc = "Reader of field `RTCC`"]
31pub type RTCC_R = crate::R<u8, RTCC_A>;
32impl RTCC_R {
33    #[doc = r"Get enumerated values variant"]
34    #[inline(always)]
35    pub fn variant(&self) -> crate::Variant<u8, RTCC_A> {
36        use crate::Variant::*;
37        match self.bits {
38            0 => Val(RTCC_A::DIV1),
39            1 => Val(RTCC_A::DIV2),
40            2 => Val(RTCC_A::DIV4),
41            i => Res(i),
42        }
43    }
44    #[doc = "Checks if the value of the field is `DIV1`"]
45    #[inline(always)]
46    pub fn is_div1(&self) -> bool {
47        *self == RTCC_A::DIV1
48    }
49    #[doc = "Checks if the value of the field is `DIV2`"]
50    #[inline(always)]
51    pub fn is_div2(&self) -> bool {
52        *self == RTCC_A::DIV2
53    }
54    #[doc = "Checks if the value of the field is `DIV4`"]
55    #[inline(always)]
56    pub fn is_div4(&self) -> bool {
57        *self == RTCC_A::DIV4
58    }
59}
60#[doc = "Write proxy for field `RTCC`"]
61pub struct RTCC_W<'a> {
62    w: &'a mut W,
63}
64impl<'a> RTCC_W<'a> {
65    #[doc = r"Writes `variant` to the field"]
66    #[inline(always)]
67    pub fn variant(self, variant: RTCC_A) -> &'a mut W {
68        unsafe { self.bits(variant.into()) }
69    }
70    #[doc = "LFECLKRTCC = LFECLK"]
71    #[inline(always)]
72    pub fn div1(self) -> &'a mut W {
73        self.variant(RTCC_A::DIV1)
74    }
75    #[doc = "LFECLKRTCC = LFECLK/2"]
76    #[inline(always)]
77    pub fn div2(self) -> &'a mut W {
78        self.variant(RTCC_A::DIV2)
79    }
80    #[doc = "LFECLKRTCC = LFECLK/4"]
81    #[inline(always)]
82    pub fn div4(self) -> &'a mut W {
83        self.variant(RTCC_A::DIV4)
84    }
85    #[doc = r"Writes raw bits to the field"]
86    #[inline(always)]
87    pub unsafe fn bits(self, value: u8) -> &'a mut W {
88        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
89        self.w
90    }
91}
92impl R {
93    #[doc = "Bits 0:1 - Real-Time Counter and Calendar Prescaler"]
94    #[inline(always)]
95    pub fn rtcc(&self) -> RTCC_R {
96        RTCC_R::new((self.bits & 0x03) as u8)
97    }
98}
99impl W {
100    #[doc = "Bits 0:1 - Real-Time Counter and Calendar Prescaler"]
101    #[inline(always)]
102    pub fn rtcc(&mut self) -> RTCC_W {
103        RTCC_W { w: self }
104    }
105}
efm32pg12_pac/cmu/lfepresc0.rs

efm32pg12_pac/cmu/
lfepresc0.rs
