efm32pg12_pac/cmu/
hfxosteadystatectrl.rs1#[doc = "Reader of register HFXOSTEADYSTATECTRL"]
2pub type R = crate::R<u32, super::HFXOSTEADYSTATECTRL>;
3#[doc = "Writer for register HFXOSTEADYSTATECTRL"]
4pub type W = crate::W<u32, super::HFXOSTEADYSTATECTRL>;
5#[doc = "Register HFXOSTEADYSTATECTRL `reset()`'s with value 0xa30b_4507"]
6impl crate::ResetValue for super::HFXOSTEADYSTATECTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0xa30b_4507
11 }
12}
13#[doc = "Reader of field `IBTRIMXOCORE`"]
14pub type IBTRIMXOCORE_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `IBTRIMXOCORE`"]
16pub struct IBTRIMXOCORE_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> IBTRIMXOCORE_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
24 self.w
25 }
26}
27#[doc = "Reader of field `REGISH`"]
28pub type REGISH_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `REGISH`"]
30pub struct REGISH_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> REGISH_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x0f << 7)) | (((value as u32) & 0x0f) << 7);
38 self.w
39 }
40}
41#[doc = "Reader of field `CTUNE`"]
42pub type CTUNE_R = crate::R<u16, u16>;
43#[doc = "Write proxy for field `CTUNE`"]
44pub struct CTUNE_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> CTUNE_W<'a> {
48 #[doc = r"Writes raw bits to the field"]
49 #[inline(always)]
50 pub unsafe fn bits(self, value: u16) -> &'a mut W {
51 self.w.bits = (self.w.bits & !(0x01ff << 11)) | (((value as u32) & 0x01ff) << 11);
52 self.w
53 }
54}
55#[doc = "Reader of field `REGSELILOW`"]
56pub type REGSELILOW_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `REGSELILOW`"]
58pub struct REGSELILOW_W<'a> {
59 w: &'a mut W,
60}
61impl<'a> REGSELILOW_W<'a> {
62 #[doc = r"Writes raw bits to the field"]
63 #[inline(always)]
64 pub unsafe fn bits(self, value: u8) -> &'a mut W {
65 self.w.bits = (self.w.bits & !(0x03 << 24)) | (((value as u32) & 0x03) << 24);
66 self.w
67 }
68}
69#[doc = "Reader of field `PEAKDETEN`"]
70pub type PEAKDETEN_R = crate::R<bool, bool>;
71#[doc = "Write proxy for field `PEAKDETEN`"]
72pub struct PEAKDETEN_W<'a> {
73 w: &'a mut W,
74}
75impl<'a> PEAKDETEN_W<'a> {
76 #[doc = r"Sets the field bit"]
77 #[inline(always)]
78 pub fn set_bit(self) -> &'a mut W {
79 self.bit(true)
80 }
81 #[doc = r"Clears the field bit"]
82 #[inline(always)]
83 pub fn clear_bit(self) -> &'a mut W {
84 self.bit(false)
85 }
86 #[doc = r"Writes raw bits to the field"]
87 #[inline(always)]
88 pub fn bit(self, value: bool) -> &'a mut W {
89 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
90 self.w
91 }
92}
93#[doc = "Reader of field `REGISHUPPER`"]
94pub type REGISHUPPER_R = crate::R<u8, u8>;
95#[doc = "Write proxy for field `REGISHUPPER`"]
96pub struct REGISHUPPER_W<'a> {
97 w: &'a mut W,
98}
99impl<'a> REGISHUPPER_W<'a> {
100 #[doc = r"Writes raw bits to the field"]
101 #[inline(always)]
102 pub unsafe fn bits(self, value: u8) -> &'a mut W {
103 self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
104 self.w
105 }
106}
107impl R {
108 #[doc = "Bits 0:6 - Sets the Steady State Oscillator Core Bias Current."]
109 #[inline(always)]
110 pub fn ibtrimxocore(&self) -> IBTRIMXOCORE_R {
111 IBTRIMXOCORE_R::new((self.bits & 0x7f) as u8)
112 }
113 #[doc = "Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
114 #[inline(always)]
115 pub fn regish(&self) -> REGISH_R {
116 REGISH_R::new(((self.bits >> 7) & 0x0f) as u8)
117 }
118 #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
119 #[inline(always)]
120 pub fn ctune(&self) -> CTUNE_R {
121 CTUNE_R::new(((self.bits >> 11) & 0x01ff) as u16)
122 }
123 #[doc = "Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
124 #[inline(always)]
125 pub fn regselilow(&self) -> REGSELILOW_R {
126 REGSELILOW_R::new(((self.bits >> 24) & 0x03) as u8)
127 }
128 #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
129 #[inline(always)]
130 pub fn peakdeten(&self) -> PEAKDETEN_R {
131 PEAKDETEN_R::new(((self.bits >> 26) & 0x01) != 0)
132 }
133 #[doc = "Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
134 #[inline(always)]
135 pub fn regishupper(&self) -> REGISHUPPER_R {
136 REGISHUPPER_R::new(((self.bits >> 28) & 0x0f) as u8)
137 }
138}
139impl W {
140 #[doc = "Bits 0:6 - Sets the Steady State Oscillator Core Bias Current."]
141 #[inline(always)]
142 pub fn ibtrimxocore(&mut self) -> IBTRIMXOCORE_W {
143 IBTRIMXOCORE_W { w: self }
144 }
145 #[doc = "Bits 7:10 - Sets the Steady State Regulator Output Current Level (shunt Regulator)"]
146 #[inline(always)]
147 pub fn regish(&mut self) -> REGISH_W {
148 REGISH_W { w: self }
149 }
150 #[doc = "Bits 11:19 - Sets Oscillator Tuning Capacitance"]
151 #[inline(always)]
152 pub fn ctune(&mut self) -> CTUNE_W {
153 CTUNE_W { w: self }
154 }
155 #[doc = "Bits 24:25 - Controls Regulator Minimum Shunt Current Detection Relative to Nominal"]
156 #[inline(always)]
157 pub fn regselilow(&mut self) -> REGSELILOW_W {
158 REGSELILOW_W { w: self }
159 }
160 #[doc = "Bit 26 - Enables Oscillator Peak Detectors"]
161 #[inline(always)]
162 pub fn peakdeten(&mut self) -> PEAKDETEN_W {
163 PEAKDETEN_W { w: self }
164 }
165 #[doc = "Bits 28:31 - Set Regulator Output Current Level (shunt Regulator). Ish = 120uA + REGISHUPPER X 120uA"]
166 #[inline(always)]
167 pub fn regishupper(&mut self) -> REGISHUPPER_W {
168 REGISHUPPER_W { w: self }
169 }
170}