efm32pg12_pac/msc/
startup.rs

1#[doc = "Reader of register STARTUP"]
2pub type R = crate::R<u32, super::STARTUP>;
3#[doc = "Writer for register STARTUP"]
4pub type W = crate::W<u32, super::STARTUP>;
5#[doc = "Register STARTUP `reset()`'s with value 0x1300_104d"]
6impl crate::ResetValue for super::STARTUP {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x1300_104d
11    }
12}
13#[doc = "Reader of field `STDLY0`"]
14pub type STDLY0_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `STDLY0`"]
16pub struct STDLY0_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> STDLY0_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
24        self.w
25    }
26}
27#[doc = "Reader of field `STDLY1`"]
28pub type STDLY1_R = crate::R<u16, u16>;
29#[doc = "Write proxy for field `STDLY1`"]
30pub struct STDLY1_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> STDLY1_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u16) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x03ff << 12)) | (((value as u32) & 0x03ff) << 12);
38        self.w
39    }
40}
41#[doc = "Reader of field `ASTWAIT`"]
42pub type ASTWAIT_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `ASTWAIT`"]
44pub struct ASTWAIT_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> ASTWAIT_W<'a> {
48    #[doc = r"Sets the field bit"]
49    #[inline(always)]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r"Clears the field bit"]
54    #[inline(always)]
55    pub fn clear_bit(self) -> &'a mut W {
56        self.bit(false)
57    }
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub fn bit(self, value: bool) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
62        self.w
63    }
64}
65#[doc = "Reader of field `STWSEN`"]
66pub type STWSEN_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `STWSEN`"]
68pub struct STWSEN_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> STWSEN_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
86        self.w
87    }
88}
89#[doc = "Reader of field `STWSAEN`"]
90pub type STWSAEN_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `STWSAEN`"]
92pub struct STWSAEN_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> STWSAEN_W<'a> {
96    #[doc = r"Sets the field bit"]
97    #[inline(always)]
98    pub fn set_bit(self) -> &'a mut W {
99        self.bit(true)
100    }
101    #[doc = r"Clears the field bit"]
102    #[inline(always)]
103    pub fn clear_bit(self) -> &'a mut W {
104        self.bit(false)
105    }
106    #[doc = r"Writes raw bits to the field"]
107    #[inline(always)]
108    pub fn bit(self, value: bool) -> &'a mut W {
109        self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
110        self.w
111    }
112}
113#[doc = "Reader of field `STWS`"]
114pub type STWS_R = crate::R<u8, u8>;
115#[doc = "Write proxy for field `STWS`"]
116pub struct STWS_W<'a> {
117    w: &'a mut W,
118}
119impl<'a> STWS_W<'a> {
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub unsafe fn bits(self, value: u8) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x07 << 28)) | (((value as u32) & 0x07) << 28);
124        self.w
125    }
126}
127impl R {
128    #[doc = "Bits 0:9 - Startup Delay 0"]
129    #[inline(always)]
130    pub fn stdly0(&self) -> STDLY0_R {
131        STDLY0_R::new((self.bits & 0x03ff) as u16)
132    }
133    #[doc = "Bits 12:21 - Startup Delay 0"]
134    #[inline(always)]
135    pub fn stdly1(&self) -> STDLY1_R {
136        STDLY1_R::new(((self.bits >> 12) & 0x03ff) as u16)
137    }
138    #[doc = "Bit 24 - Active Startup Wait"]
139    #[inline(always)]
140    pub fn astwait(&self) -> ASTWAIT_R {
141        ASTWAIT_R::new(((self.bits >> 24) & 0x01) != 0)
142    }
143    #[doc = "Bit 25 - Startup Waitstates Enable"]
144    #[inline(always)]
145    pub fn stwsen(&self) -> STWSEN_R {
146        STWSEN_R::new(((self.bits >> 25) & 0x01) != 0)
147    }
148    #[doc = "Bit 26 - Startup Waitstates Always Enable"]
149    #[inline(always)]
150    pub fn stwsaen(&self) -> STWSAEN_R {
151        STWSAEN_R::new(((self.bits >> 26) & 0x01) != 0)
152    }
153    #[doc = "Bits 28:30 - Startup Waitstates"]
154    #[inline(always)]
155    pub fn stws(&self) -> STWS_R {
156        STWS_R::new(((self.bits >> 28) & 0x07) as u8)
157    }
158}
159impl W {
160    #[doc = "Bits 0:9 - Startup Delay 0"]
161    #[inline(always)]
162    pub fn stdly0(&mut self) -> STDLY0_W {
163        STDLY0_W { w: self }
164    }
165    #[doc = "Bits 12:21 - Startup Delay 0"]
166    #[inline(always)]
167    pub fn stdly1(&mut self) -> STDLY1_W {
168        STDLY1_W { w: self }
169    }
170    #[doc = "Bit 24 - Active Startup Wait"]
171    #[inline(always)]
172    pub fn astwait(&mut self) -> ASTWAIT_W {
173        ASTWAIT_W { w: self }
174    }
175    #[doc = "Bit 25 - Startup Waitstates Enable"]
176    #[inline(always)]
177    pub fn stwsen(&mut self) -> STWSEN_W {
178        STWSEN_W { w: self }
179    }
180    #[doc = "Bit 26 - Startup Waitstates Always Enable"]
181    #[inline(always)]
182    pub fn stwsaen(&mut self) -> STWSAEN_W {
183        STWSAEN_W { w: self }
184    }
185    #[doc = "Bits 28:30 - Startup Waitstates"]
186    #[inline(always)]
187    pub fn stws(&mut self) -> STWS_W {
188        STWS_W { w: self }
189    }
190}
efm32pg12_pac/msc/startup.rs

efm32pg12_pac/msc/
startup.rs
