efm32pg12_pac/emu/
dcdcctrl.rs1#[doc = "Reader of register DCDCCTRL"]
2pub type R = crate::R<u32, super::DCDCCTRL>;
3#[doc = "Writer for register DCDCCTRL"]
4pub type W = crate::W<u32, super::DCDCCTRL>;
5#[doc = "Register DCDCCTRL `reset()`'s with value 0x33"]
6impl crate::ResetValue for super::DCDCCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x33
11 }
12}
13#[doc = "Regulator Mode\n\nValue on reset: 3"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum DCDCMODE_A {
17 #[doc = "0: DCDC regulator is operating in bypass mode. Prior to configuring DCDCMODE=BYPASS, software must set EMU_DCDCCLIMCTRL.BYPLIMEN=1 to prevent excessive current between VREGVDD and DVDD supplies."]
18 BYPASS = 0,
19 #[doc = "1: DCDC regulator is operating in low noise mode."]
20 LOWNOISE = 1,
21 #[doc = "2: DCDC regulator is operating in low power mode."]
22 LOWPOWER = 2,
23 #[doc = "3: DCDC regulator is off and the bypass switch is off. Note: DVDD must be supplied externally"]
24 OFF = 3,
25}
26impl From<DCDCMODE_A> for u8 {
27 #[inline(always)]
28 fn from(variant: DCDCMODE_A) -> Self {
29 variant as _
30 }
31}
32#[doc = "Reader of field `DCDCMODE`"]
33pub type DCDCMODE_R = crate::R<u8, DCDCMODE_A>;
34impl DCDCMODE_R {
35 #[doc = r"Get enumerated values variant"]
36 #[inline(always)]
37 pub fn variant(&self) -> DCDCMODE_A {
38 match self.bits {
39 0 => DCDCMODE_A::BYPASS,
40 1 => DCDCMODE_A::LOWNOISE,
41 2 => DCDCMODE_A::LOWPOWER,
42 3 => DCDCMODE_A::OFF,
43 _ => unreachable!(),
44 }
45 }
46 #[doc = "Checks if the value of the field is `BYPASS`"]
47 #[inline(always)]
48 pub fn is_bypass(&self) -> bool {
49 *self == DCDCMODE_A::BYPASS
50 }
51 #[doc = "Checks if the value of the field is `LOWNOISE`"]
52 #[inline(always)]
53 pub fn is_lownoise(&self) -> bool {
54 *self == DCDCMODE_A::LOWNOISE
55 }
56 #[doc = "Checks if the value of the field is `LOWPOWER`"]
57 #[inline(always)]
58 pub fn is_lowpower(&self) -> bool {
59 *self == DCDCMODE_A::LOWPOWER
60 }
61 #[doc = "Checks if the value of the field is `OFF`"]
62 #[inline(always)]
63 pub fn is_off(&self) -> bool {
64 *self == DCDCMODE_A::OFF
65 }
66}
67#[doc = "Write proxy for field `DCDCMODE`"]
68pub struct DCDCMODE_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> DCDCMODE_W<'a> {
72 #[doc = r"Writes `variant` to the field"]
73 #[inline(always)]
74 pub fn variant(self, variant: DCDCMODE_A) -> &'a mut W {
75 {
76 self.bits(variant.into())
77 }
78 }
79 #[doc = "DCDC regulator is operating in bypass mode. Prior to configuring DCDCMODE=BYPASS, software must set EMU_DCDCCLIMCTRL.BYPLIMEN=1 to prevent excessive current between VREGVDD and DVDD supplies."]
80 #[inline(always)]
81 pub fn bypass(self) -> &'a mut W {
82 self.variant(DCDCMODE_A::BYPASS)
83 }
84 #[doc = "DCDC regulator is operating in low noise mode."]
85 #[inline(always)]
86 pub fn lownoise(self) -> &'a mut W {
87 self.variant(DCDCMODE_A::LOWNOISE)
88 }
89 #[doc = "DCDC regulator is operating in low power mode."]
90 #[inline(always)]
91 pub fn lowpower(self) -> &'a mut W {
92 self.variant(DCDCMODE_A::LOWPOWER)
93 }
94 #[doc = "DCDC regulator is off and the bypass switch is off. Note: DVDD must be supplied externally"]
95 #[inline(always)]
96 pub fn off(self) -> &'a mut W {
97 self.variant(DCDCMODE_A::OFF)
98 }
99 #[doc = r"Writes raw bits to the field"]
100 #[inline(always)]
101 pub fn bits(self, value: u8) -> &'a mut W {
102 self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
103 self.w
104 }
105}
106#[doc = "Reader of field `DCDCMODEEM23`"]
107pub type DCDCMODEEM23_R = crate::R<bool, bool>;
108#[doc = "Write proxy for field `DCDCMODEEM23`"]
109pub struct DCDCMODEEM23_W<'a> {
110 w: &'a mut W,
111}
112impl<'a> DCDCMODEEM23_W<'a> {
113 #[doc = r"Sets the field bit"]
114 #[inline(always)]
115 pub fn set_bit(self) -> &'a mut W {
116 self.bit(true)
117 }
118 #[doc = r"Clears the field bit"]
119 #[inline(always)]
120 pub fn clear_bit(self) -> &'a mut W {
121 self.bit(false)
122 }
123 #[doc = r"Writes raw bits to the field"]
124 #[inline(always)]
125 pub fn bit(self, value: bool) -> &'a mut W {
126 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
127 self.w
128 }
129}
130#[doc = "Reader of field `DCDCMODEEM4`"]
131pub type DCDCMODEEM4_R = crate::R<bool, bool>;
132#[doc = "Write proxy for field `DCDCMODEEM4`"]
133pub struct DCDCMODEEM4_W<'a> {
134 w: &'a mut W,
135}
136impl<'a> DCDCMODEEM4_W<'a> {
137 #[doc = r"Sets the field bit"]
138 #[inline(always)]
139 pub fn set_bit(self) -> &'a mut W {
140 self.bit(true)
141 }
142 #[doc = r"Clears the field bit"]
143 #[inline(always)]
144 pub fn clear_bit(self) -> &'a mut W {
145 self.bit(false)
146 }
147 #[doc = r"Writes raw bits to the field"]
148 #[inline(always)]
149 pub fn bit(self, value: bool) -> &'a mut W {
150 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
151 self.w
152 }
153}
154impl R {
155 #[doc = "Bits 0:1 - Regulator Mode"]
156 #[inline(always)]
157 pub fn dcdcmode(&self) -> DCDCMODE_R {
158 DCDCMODE_R::new((self.bits & 0x03) as u8)
159 }
160 #[doc = "Bit 4 - DCDC Mode EM23"]
161 #[inline(always)]
162 pub fn dcdcmodeem23(&self) -> DCDCMODEEM23_R {
163 DCDCMODEEM23_R::new(((self.bits >> 4) & 0x01) != 0)
164 }
165 #[doc = "Bit 5 - DCDC Mode EM4H"]
166 #[inline(always)]
167 pub fn dcdcmodeem4(&self) -> DCDCMODEEM4_R {
168 DCDCMODEEM4_R::new(((self.bits >> 5) & 0x01) != 0)
169 }
170}
171impl W {
172 #[doc = "Bits 0:1 - Regulator Mode"]
173 #[inline(always)]
174 pub fn dcdcmode(&mut self) -> DCDCMODE_W {
175 DCDCMODE_W { w: self }
176 }
177 #[doc = "Bit 4 - DCDC Mode EM23"]
178 #[inline(always)]
179 pub fn dcdcmodeem23(&mut self) -> DCDCMODEEM23_W {
180 DCDCMODEEM23_W { w: self }
181 }
182 #[doc = "Bit 5 - DCDC Mode EM4H"]
183 #[inline(always)]
184 pub fn dcdcmodeem4(&mut self) -> DCDCMODEEM4_W {
185 DCDCMODEEM4_W { w: self }
186 }
187}