efm32pg12_pac/emu/
dcdclpctrl.rs

1#[doc = "Reader of register DCDCLPCTRL"]
2pub type R = crate::R<u32, super::DCDCLPCTRL>;
3#[doc = "Writer for register DCDCLPCTRL"]
4pub type W = crate::W<u32, super::DCDCLPCTRL>;
5#[doc = "Register DCDCLPCTRL `reset()`'s with value 0x0300_0000"]
6impl crate::ResetValue for super::DCDCLPCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0300_0000
11    }
12}
13#[doc = "Reader of field `LPCMPHYSSELEM234H`"]
14pub type LPCMPHYSSELEM234H_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `LPCMPHYSSELEM234H`"]
16pub struct LPCMPHYSSELEM234H_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> LPCMPHYSSELEM234H_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
24        self.w
25    }
26}
27#[doc = "Reader of field `LPVREFDUTYEN`"]
28pub type LPVREFDUTYEN_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `LPVREFDUTYEN`"]
30pub struct LPVREFDUTYEN_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> LPVREFDUTYEN_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
48        self.w
49    }
50}
51#[doc = "Reader of field `LPBLANK`"]
52pub type LPBLANK_R = crate::R<u8, u8>;
53#[doc = "Write proxy for field `LPBLANK`"]
54pub struct LPBLANK_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> LPBLANK_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
62        self.w
63    }
64}
65impl R {
66    #[doc = "Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H"]
67    #[inline(always)]
68    pub fn lpcmphysselem234h(&self) -> LPCMPHYSSELEM234H_R {
69        LPCMPHYSSELEM234H_R::new(((self.bits >> 12) & 0x0f) as u8)
70    }
71    #[doc = "Bit 24 - LP Mode Duty Cycling Enable"]
72    #[inline(always)]
73    pub fn lpvrefdutyen(&self) -> LPVREFDUTYEN_R {
74        LPVREFDUTYEN_R::new(((self.bits >> 24) & 0x01) != 0)
75    }
76    #[doc = "Bits 25:26 - Reserved for internal use. Do not change."]
77    #[inline(always)]
78    pub fn lpblank(&self) -> LPBLANK_R {
79        LPBLANK_R::new(((self.bits >> 25) & 0x03) as u8)
80    }
81}
82impl W {
83    #[doc = "Bits 12:15 - LP Mode Hysteresis Selection for EM23 and EM4H"]
84    #[inline(always)]
85    pub fn lpcmphysselem234h(&mut self) -> LPCMPHYSSELEM234H_W {
86        LPCMPHYSSELEM234H_W { w: self }
87    }
88    #[doc = "Bit 24 - LP Mode Duty Cycling Enable"]
89    #[inline(always)]
90    pub fn lpvrefdutyen(&mut self) -> LPVREFDUTYEN_W {
91        LPVREFDUTYEN_W { w: self }
92    }
93    #[doc = "Bits 25:26 - Reserved for internal use. Do not change."]
94    #[inline(always)]
95    pub fn lpblank(&mut self) -> LPBLANK_W {
96        LPBLANK_W { w: self }
97    }
98}
efm32pg12_pac/emu/dcdclpctrl.rs

efm32pg12_pac/emu/
dcdclpctrl.rs
