rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `TIM17` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `DIER` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Dier = 2,
    /// `SR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Sr = 3,
    /// `EGR` at offset `0x14`, resets to `0x0000_0000`, write-only.
    Egr = 4,
    /// `CCMR1_Input` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Input = 5,
    /// `CCMR1_Output` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ccmr1Output = 6,
    /// `CCER` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Ccer = 7,
    /// `CNT` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Cnt = 8,
    /// `PSC` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Psc = 9,
    /// `ARR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Arr = 10,
    /// `RCR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Rcr = 11,
    /// `CCR1` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Ccr1 = 12,
    /// `BDTR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Bdtr = 13,
    /// `DCR` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Dcr = 14,
    /// `DMAR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Dmar = 15,
    /// `TIM17_AF1` at offset `0x60`, resets to `0x0000_0000`, read-write.
    Tim17Af1 = 16,
    /// `TIM17_TISEL` at offset `0x68`, resets to `0x0000_0000`, read-write.
    Tim17Tisel = 17,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 18] = [Self::Cr1, Self::Cr2, Self::Dier, Self::Sr, Self::Egr, Self::Ccmr1Input, Self::Ccmr1Output, Self::Ccer, Self::Cnt, Self::Psc, Self::Arr, Self::Rcr, Self::Ccr1, Self::Bdtr, Self::Dcr, Self::Dmar, Self::Tim17Af1, Self::Tim17Tisel];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `CEN`, bit 0.
    pub const CEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `UDIS`, bit 1.
    pub const UDIS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `URS`, bit 2.
    pub const URS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `OPM`, bit 3.
    pub const OPM: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `ARPE`, bit 7.
    pub const ARPE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `CKD`, bits 8..=9.
    pub const CKD: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `UIFREMAP`, bit 11.
    pub const UIFREMAP: &FieldSpec = &super::REGISTERS[0].fields[6];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `CCPC`, bit 0.
    pub const CCPC: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CCUS`, bit 2.
    pub const CCUS: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `CCDS`, bit 3.
    pub const CCDS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `OIS1`, bit 8.
    pub const OIS1: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `OIS1N`, bit 9.
    pub const OIS1N: &FieldSpec = &super::REGISTERS[1].fields[4];
}

/// The fields of `DIER`.
pub mod dier {
    use super::FieldSpec;
    /// `UIE`, bit 0.
    pub const UIE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CC1IE`, bit 1.
    pub const CC1IE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `COMIE`, bit 5.
    pub const COMIE: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `BIE`, bit 7.
    pub const BIE: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `UDE`, bit 8.
    pub const UDE: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CC1DE`, bit 9.
    pub const CC1DE: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `COMDE`, bit 13.
    pub const COMDE: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `UIF`, bit 0.
    pub const UIF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CC1IF`, bit 1.
    pub const CC1IF: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `COMIF`, bit 5.
    pub const COMIF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `BIF`, bit 7.
    pub const BIF: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CC1OF`, bit 9.
    pub const CC1OF: &FieldSpec = &super::REGISTERS[3].fields[4];
}

/// The fields of `EGR`.
pub mod egr {
    use super::FieldSpec;
    /// `UG`, bit 0.
    pub const UG: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `CC1G`, bit 1.
    pub const CC1G: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `COMG`, bit 5.
    pub const COMG: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `BG`, bit 7.
    pub const BG: &FieldSpec = &super::REGISTERS[4].fields[3];
}

/// The fields of `CCMR1_Input`.
pub mod ccmr1_input {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `IC1PSC`, bits 2..=3.
    pub const IC1PSC: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `IC1F`, bits 4..=7.
    pub const IC1F: &FieldSpec = &super::REGISTERS[5].fields[2];
}

/// The fields of `CCMR1_Output`.
pub mod ccmr1_output {
    use super::FieldSpec;
    /// `CC1S`, bits 0..=1.
    pub const CC1S: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `OC1FE`, bit 2.
    pub const OC1FE: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `OC1PE`, bit 3.
    pub const OC1PE: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `OC1M`, bits 4..=6.
    pub const OC1M: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `OC1M_3`, bit 16.
    pub const OC1M_3: &FieldSpec = &super::REGISTERS[6].fields[4];
}

/// The fields of `CCER`.
pub mod ccer {
    use super::FieldSpec;
    /// `CC1E`, bit 0.
    pub const CC1E: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `CC1P`, bit 1.
    pub const CC1P: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `CC1NE`, bit 2.
    pub const CC1NE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `CC1NP`, bit 3.
    pub const CC1NP: &FieldSpec = &super::REGISTERS[7].fields[3];
}

/// The fields of `CNT`.
pub mod cnt {
    use super::FieldSpec;
    /// `CNT`, bits 0..=15.
    pub const CNT: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `UIFCPY`, bit 31, read-only.
    pub const UIFCPY: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `PSC`.
pub mod psc {
    use super::FieldSpec;
    /// `PSC`, bits 0..=15.
    pub const PSC: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `ARR`.
pub mod arr {
    use super::FieldSpec;
    /// `ARR`, bits 0..=15.
    pub const ARR: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `RCR`.
pub mod rcr {
    use super::FieldSpec;
    /// `REP`, bits 0..=7.
    pub const REP: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `CCR1`.
pub mod ccr1 {
    use super::FieldSpec;
    /// `CCR1`, bits 0..=15.
    pub const CCR1: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `BDTR`.
pub mod bdtr {
    use super::FieldSpec;
    /// `DTG`, bits 0..=7.
    pub const DTG: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `LOCK`, bits 8..=9.
    pub const LOCK: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `OSSI`, bit 10.
    pub const OSSI: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `OSSR`, bit 11.
    pub const OSSR: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `BKE`, bit 12.
    pub const BKE: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `BKP`, bit 13.
    pub const BKP: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `AOE`, bit 14.
    pub const AOE: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `MOE`, bit 15.
    pub const MOE: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `BKF`, bits 16..=19.
    pub const BKF: &FieldSpec = &super::REGISTERS[13].fields[8];
}

/// The fields of `DCR`.
pub mod dcr {
    use super::FieldSpec;
    /// `DBA`, bits 0..=4.
    pub const DBA: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `DBL`, bits 8..=12.
    pub const DBL: &FieldSpec = &super::REGISTERS[14].fields[1];
}

/// The fields of `DMAR`.
pub mod dmar {
    use super::FieldSpec;
    /// `DMAB`, bits 0..=15.
    pub const DMAB: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `TIM17_AF1`.
pub mod tim17_af1 {
    use super::FieldSpec;
    /// `BKINE`, bit 0.
    pub const BKINE: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `BKCMP1E`, bit 1.
    pub const BKCMP1E: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `BKCMP2E`, bit 2.
    pub const BKCMP2E: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `BKDFBK1E`, bit 8.
    pub const BKDFBK1E: &FieldSpec = &super::REGISTERS[16].fields[3];
    /// `BKINP`, bit 9.
    pub const BKINP: &FieldSpec = &super::REGISTERS[16].fields[4];
    /// `BKCMP1P`, bit 10.
    pub const BKCMP1P: &FieldSpec = &super::REGISTERS[16].fields[5];
    /// `BKCMP2P`, bit 11.
    pub const BKCMP2P: &FieldSpec = &super::REGISTERS[16].fields[6];
}

/// The fields of `TIM17_TISEL`.
pub mod tim17_tisel {
    use super::FieldSpec;
    /// `TI1SEL`, bits 0..=3.
    pub const TI1SEL: &FieldSpec = &super::REGISTERS[17].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 18] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "URS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPM", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ARPE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKD", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UIFREMAP", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCPC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCUS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCDS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIS1", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OIS1N", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIER", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UDE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1DE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMDE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UIF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1IF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMIF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BIF", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1OF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EGR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UG", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1G", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMG", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BG", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Input", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC1PSC", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IC1F", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCMR1_Output", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1S", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1FE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1PE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1M", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OC1M_3", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCER", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CC1E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1P", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1NE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CC1NP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CNT", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UIFCPY", bit: 31, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PSC", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PSC", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ARR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ARR", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RCR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "REP", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR1", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CCR1", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDTR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTG", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LOCK", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSSI", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSSR", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKP", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AOE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MOE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKF", bit: 16, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DBA", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DMAR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMAB", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TIM17_AF1", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKINE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKCMP1E", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKCMP2E", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKDFBK1E", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKINP", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKCMP1P", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKCMP2P", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TIM17_TISEL", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TI1SEL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];