rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `HRTIM_Common` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `ISR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Isr = 2,
    /// `ICR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Icr = 3,
    /// `IER` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Ier = 4,
    /// `OENR` at offset `0x14`, resets to `0x0000_0000`, write-only.
    Oenr = 5,
    /// `DISR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Disr = 6,
    /// `ODSR` at offset `0x1C`, resets to `0x0000_0000`, read-only.
    Odsr = 7,
    /// `BMCR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Bmcr = 8,
    /// `BMTRG` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Bmtrg = 9,
    /// `BMCMPR6` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Bmcmpr6 = 10,
    /// `BMPER` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Bmper = 11,
    /// `EECR1` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Eecr1 = 12,
    /// `EECR2` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Eecr2 = 13,
    /// `EECR3` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Eecr3 = 14,
    /// `ADC1R` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Adc1r = 15,
    /// `ADC2R` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Adc2r = 16,
    /// `ADC3R` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Adc3r = 17,
    /// `ADC4R` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Adc4r = 18,
    /// `DLLCR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Dllcr = 19,
    /// `FLTINR1` at offset `0x50`, resets to `0x0000_0000`, read-write.
    Fltinr1 = 20,
    /// `FLTINR2` at offset `0x54`, resets to `0x0000_0000`, read-write.
    Fltinr2 = 21,
    /// `BDMUPDR` at offset `0x58`, resets to `0x0000_0000`, read-write.
    Bdmupdr = 22,
    /// `BDTxUPR` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    Bdtxupr = 23,
    /// `BDMADR` at offset `0x60`, resets to `0x0000_0000`, read-write.
    Bdmadr = 24,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 25] = [Self::Cr1, Self::Cr2, Self::Isr, Self::Icr, Self::Ier, Self::Oenr, Self::Disr, Self::Odsr, Self::Bmcr, Self::Bmtrg, Self::Bmcmpr6, Self::Bmper, Self::Eecr1, Self::Eecr2, Self::Eecr3, Self::Adc1r, Self::Adc2r, Self::Adc3r, Self::Adc4r, Self::Dllcr, Self::Fltinr1, Self::Fltinr2, Self::Bdmupdr, Self::Bdtxupr, Self::Bdmadr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `MUDIS`, bit 0.
    pub const MUDIS: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `TAUDIS`, bit 1.
    pub const TAUDIS: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `TBUDIS`, bit 2.
    pub const TBUDIS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TCUDIS`, bit 3.
    pub const TCUDIS: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `TDUDIS`, bit 4.
    pub const TDUDIS: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `TEUDIS`, bit 5.
    pub const TEUDIS: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `AD1USRC`, bits 16..=18.
    pub const AD1USRC: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `AD2USRC`, bits 19..=21.
    pub const AD2USRC: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `AD3USRC`, bits 22..=24.
    pub const AD3USRC: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `AD4USRC`, bits 25..=27.
    pub const AD4USRC: &FieldSpec = &super::REGISTERS[0].fields[9];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `MSWU`, bit 0.
    pub const MSWU: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TASWU`, bit 1.
    pub const TASWU: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TBSWU`, bit 2.
    pub const TBSWU: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `TCSWU`, bit 3.
    pub const TCSWU: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `TDSWU`, bit 4.
    pub const TDSWU: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `TESWU`, bit 5.
    pub const TESWU: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `MRST`, bit 8.
    pub const MRST: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `TARST`, bit 9.
    pub const TARST: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `TBRST`, bit 10.
    pub const TBRST: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `TCRST`, bit 11.
    pub const TCRST: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `TDRST`, bit 12.
    pub const TDRST: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `TERST`, bit 13.
    pub const TERST: &FieldSpec = &super::REGISTERS[1].fields[11];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `FLT1`, bit 0, read-only.
    pub const FLT1: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `FLT2`, bit 1, read-only.
    pub const FLT2: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `FLT3`, bit 2, read-only.
    pub const FLT3: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `FLT4`, bit 3, read-only.
    pub const FLT4: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `FLT5`, bit 4, read-only.
    pub const FLT5: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `SYSFLT`, bit 5.
    pub const SYSFLT: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `DLLRDY`, bit 16, read-only.
    pub const DLLRDY: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `BMPER`, bit 17, read-only.
    pub const BMPER: &FieldSpec = &super::REGISTERS[2].fields[7];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `FLT1C`, bit 0, write-only.
    pub const FLT1C: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `FLT2C`, bit 1, write-only.
    pub const FLT2C: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `FLT3C`, bit 2, write-only.
    pub const FLT3C: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `FLT4C`, bit 3, write-only.
    pub const FLT4C: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `FLT5C`, bit 4, write-only.
    pub const FLT5C: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `SYSFLTC`, bit 5.
    pub const SYSFLTC: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `DLLRDYC`, bit 16, write-only.
    pub const DLLRDYC: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `BMPERC`, bit 17, write-only.
    pub const BMPERC: &FieldSpec = &super::REGISTERS[3].fields[7];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `FLT1IE`, bit 0.
    pub const FLT1IE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `FLT2IE`, bit 1.
    pub const FLT2IE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `FLT3IE`, bit 2.
    pub const FLT3IE: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `FLT4IE`, bit 3.
    pub const FLT4IE: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `FLT5IE`, bit 4.
    pub const FLT5IE: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `SYSFLTE`, bit 5.
    pub const SYSFLTE: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `DLLRDYIE`, bit 16.
    pub const DLLRDYIE: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `BMPERIE`, bit 17.
    pub const BMPERIE: &FieldSpec = &super::REGISTERS[4].fields[7];
}

/// The fields of `OENR`.
pub mod oenr {
    use super::FieldSpec;
    /// `TA1OEN`, bit 0.
    pub const TA1OEN: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TA2OEN`, bit 1.
    pub const TA2OEN: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `TB1OEN`, bit 2.
    pub const TB1OEN: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `TB2OEN`, bit 3.
    pub const TB2OEN: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `TC1OEN`, bit 4.
    pub const TC1OEN: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `TC2OEN`, bit 5.
    pub const TC2OEN: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `TD1OEN`, bit 6.
    pub const TD1OEN: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `TD2OEN`, bit 7.
    pub const TD2OEN: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `TE1OEN`, bit 8.
    pub const TE1OEN: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `TE2OEN`, bit 9.
    pub const TE2OEN: &FieldSpec = &super::REGISTERS[5].fields[9];
}

/// The fields of `DISR`.
pub mod disr {
    use super::FieldSpec;
    /// `TA1ODIS`, bit 0.
    pub const TA1ODIS: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `TA2ODIS`, bit 1.
    pub const TA2ODIS: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `TB1ODIS`, bit 2.
    pub const TB1ODIS: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `TB2ODIS`, bit 3.
    pub const TB2ODIS: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `TC1ODIS`, bit 4.
    pub const TC1ODIS: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `TC2ODIS`, bit 5.
    pub const TC2ODIS: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `TD1ODIS`, bit 6.
    pub const TD1ODIS: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `TD2ODIS`, bit 7.
    pub const TD2ODIS: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `TE1ODIS`, bit 8.
    pub const TE1ODIS: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `TE2ODIS`, bit 9.
    pub const TE2ODIS: &FieldSpec = &super::REGISTERS[6].fields[9];
}

/// The fields of `ODSR`.
pub mod odsr {
    use super::FieldSpec;
    /// `TA1ODS`, bit 0.
    pub const TA1ODS: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `TA2ODS`, bit 1.
    pub const TA2ODS: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `TB1ODS`, bit 2.
    pub const TB1ODS: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `TB2ODS`, bit 3.
    pub const TB2ODS: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `TC1ODS`, bit 4.
    pub const TC1ODS: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `TC2ODS`, bit 5.
    pub const TC2ODS: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `TD1ODS`, bit 6.
    pub const TD1ODS: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `TD2ODS`, bit 7.
    pub const TD2ODS: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `TE1ODS`, bit 8.
    pub const TE1ODS: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `TE2ODS`, bit 9.
    pub const TE2ODS: &FieldSpec = &super::REGISTERS[7].fields[9];
}

/// The fields of `BMCR`.
pub mod bmcr {
    use super::FieldSpec;
    /// `BME`, bit 0.
    pub const BME: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `BMOM`, bit 1.
    pub const BMOM: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `BMCLK`, bits 2..=5.
    pub const BMCLK: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `BMPRSC`, bits 6..=9.
    pub const BMPRSC: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `BMPREN`, bit 10.
    pub const BMPREN: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `MTBM`, bit 16.
    pub const MTBM: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `TABM`, bit 17.
    pub const TABM: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `TBBM`, bit 18.
    pub const TBBM: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `TCBM`, bit 19.
    pub const TCBM: &FieldSpec = &super::REGISTERS[8].fields[8];
    /// `TDBM`, bit 20.
    pub const TDBM: &FieldSpec = &super::REGISTERS[8].fields[9];
    /// `TEBM`, bit 21.
    pub const TEBM: &FieldSpec = &super::REGISTERS[8].fields[10];
    /// `BMSTAT`, bit 31.
    pub const BMSTAT: &FieldSpec = &super::REGISTERS[8].fields[11];
}

/// The fields of `BMTRG`.
pub mod bmtrg {
    use super::FieldSpec;
    /// `SW`, bit 0.
    pub const SW: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `MSTRST`, bit 1.
    pub const MSTRST: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `MSTREP`, bit 2.
    pub const MSTREP: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `MSTCMP1`, bit 3.
    pub const MSTCMP1: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `MSTCMP2`, bit 4.
    pub const MSTCMP2: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `MSTCMP3`, bit 5.
    pub const MSTCMP3: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `MSTCMP4`, bit 6.
    pub const MSTCMP4: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `TARST`, bit 7.
    pub const TARST: &FieldSpec = &super::REGISTERS[9].fields[7];
    /// `TAREP`, bit 8.
    pub const TAREP: &FieldSpec = &super::REGISTERS[9].fields[8];
    /// `TACMP1`, bit 9.
    pub const TACMP1: &FieldSpec = &super::REGISTERS[9].fields[9];
    /// `TACMP2`, bit 10.
    pub const TACMP2: &FieldSpec = &super::REGISTERS[9].fields[10];
    /// `TBRST`, bit 11.
    pub const TBRST: &FieldSpec = &super::REGISTERS[9].fields[11];
    /// `TBREP`, bit 12.
    pub const TBREP: &FieldSpec = &super::REGISTERS[9].fields[12];
    /// `TBCMP1`, bit 13.
    pub const TBCMP1: &FieldSpec = &super::REGISTERS[9].fields[13];
    /// `TBCMP2`, bit 14.
    pub const TBCMP2: &FieldSpec = &super::REGISTERS[9].fields[14];
    /// `TCRST`, bit 15.
    pub const TCRST: &FieldSpec = &super::REGISTERS[9].fields[15];
    /// `TCREP`, bit 16.
    pub const TCREP: &FieldSpec = &super::REGISTERS[9].fields[16];
    /// `TCCMP1`, bit 17.
    pub const TCCMP1: &FieldSpec = &super::REGISTERS[9].fields[17];
    /// `TCCMP2`, bit 18.
    pub const TCCMP2: &FieldSpec = &super::REGISTERS[9].fields[18];
    /// `TDRST`, bit 19.
    pub const TDRST: &FieldSpec = &super::REGISTERS[9].fields[19];
    /// `TDREP`, bit 20.
    pub const TDREP: &FieldSpec = &super::REGISTERS[9].fields[20];
    /// `TDCMP1`, bit 21.
    pub const TDCMP1: &FieldSpec = &super::REGISTERS[9].fields[21];
    /// `TDCMP2`, bit 22.
    pub const TDCMP2: &FieldSpec = &super::REGISTERS[9].fields[22];
    /// `TERST`, bit 23.
    pub const TERST: &FieldSpec = &super::REGISTERS[9].fields[23];
    /// `TEREP`, bit 24.
    pub const TEREP: &FieldSpec = &super::REGISTERS[9].fields[24];
    /// `TECMP1`, bit 25.
    pub const TECMP1: &FieldSpec = &super::REGISTERS[9].fields[25];
    /// `TECMP2`, bit 26.
    pub const TECMP2: &FieldSpec = &super::REGISTERS[9].fields[26];
    /// `OCHPEV`, bit 31.
    pub const OCHPEV: &FieldSpec = &super::REGISTERS[9].fields[27];
}

/// The fields of `BMCMPR6`.
pub mod bmcmpr6 {
    use super::FieldSpec;
    /// `BMCMP`, bits 0..=15.
    pub const BMCMP: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `BMPER`.
pub mod bmper {
    use super::FieldSpec;
    /// `BMPER`, bits 0..=15.
    pub const BMPER: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `EECR1`.
pub mod eecr1 {
    use super::FieldSpec;
    /// `EE1SRC`, bits 0..=1.
    pub const EE1SRC: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `EE1POL`, bit 2.
    pub const EE1POL: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `EE1SNS`, bits 3..=4.
    pub const EE1SNS: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `EE1FAST`, bit 5.
    pub const EE1FAST: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `EE2SRC`, bits 6..=7.
    pub const EE2SRC: &FieldSpec = &super::REGISTERS[12].fields[4];
    /// `EE2POL`, bit 8.
    pub const EE2POL: &FieldSpec = &super::REGISTERS[12].fields[5];
    /// `EE2SNS`, bits 9..=10.
    pub const EE2SNS: &FieldSpec = &super::REGISTERS[12].fields[6];
    /// `EE2FAST`, bit 11.
    pub const EE2FAST: &FieldSpec = &super::REGISTERS[12].fields[7];
    /// `EE3SRC`, bits 12..=13.
    pub const EE3SRC: &FieldSpec = &super::REGISTERS[12].fields[8];
    /// `EE3POL`, bit 14.
    pub const EE3POL: &FieldSpec = &super::REGISTERS[12].fields[9];
    /// `EE3SNS`, bits 15..=16.
    pub const EE3SNS: &FieldSpec = &super::REGISTERS[12].fields[10];
    /// `EE3FAST`, bit 17.
    pub const EE3FAST: &FieldSpec = &super::REGISTERS[12].fields[11];
    /// `EE4SRC`, bits 18..=19.
    pub const EE4SRC: &FieldSpec = &super::REGISTERS[12].fields[12];
    /// `EE4POL`, bit 20.
    pub const EE4POL: &FieldSpec = &super::REGISTERS[12].fields[13];
    /// `EE4SNS`, bits 21..=22.
    pub const EE4SNS: &FieldSpec = &super::REGISTERS[12].fields[14];
    /// `EE4FAST`, bit 23.
    pub const EE4FAST: &FieldSpec = &super::REGISTERS[12].fields[15];
    /// `EE5SRC`, bits 24..=25.
    pub const EE5SRC: &FieldSpec = &super::REGISTERS[12].fields[16];
    /// `EE5POL`, bit 26.
    pub const EE5POL: &FieldSpec = &super::REGISTERS[12].fields[17];
    /// `EE5SNS`, bits 27..=28.
    pub const EE5SNS: &FieldSpec = &super::REGISTERS[12].fields[18];
    /// `EE5FAST`, bit 29.
    pub const EE5FAST: &FieldSpec = &super::REGISTERS[12].fields[19];
}

/// The fields of `EECR2`.
pub mod eecr2 {
    use super::FieldSpec;
    /// `EE6SRC`, bits 0..=1.
    pub const EE6SRC: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `EE6POL`, bit 2.
    pub const EE6POL: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `EE6SNS`, bits 3..=4.
    pub const EE6SNS: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `EE7SRC`, bits 6..=7.
    pub const EE7SRC: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `EE7POL`, bit 8.
    pub const EE7POL: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `EE7SNS`, bits 9..=10.
    pub const EE7SNS: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `EE8SRC`, bits 12..=13.
    pub const EE8SRC: &FieldSpec = &super::REGISTERS[13].fields[6];
    /// `EE8POL`, bit 14.
    pub const EE8POL: &FieldSpec = &super::REGISTERS[13].fields[7];
    /// `EE8SNS`, bits 15..=16.
    pub const EE8SNS: &FieldSpec = &super::REGISTERS[13].fields[8];
    /// `EE9SRC`, bits 18..=19.
    pub const EE9SRC: &FieldSpec = &super::REGISTERS[13].fields[9];
    /// `EE9POL`, bit 20.
    pub const EE9POL: &FieldSpec = &super::REGISTERS[13].fields[10];
    /// `EE9SNS`, bits 21..=22.
    pub const EE9SNS: &FieldSpec = &super::REGISTERS[13].fields[11];
    /// `EE10SRC`, bits 24..=25.
    pub const EE10SRC: &FieldSpec = &super::REGISTERS[13].fields[12];
    /// `EE10POL`, bit 26.
    pub const EE10POL: &FieldSpec = &super::REGISTERS[13].fields[13];
    /// `EE10SNS`, bits 27..=28.
    pub const EE10SNS: &FieldSpec = &super::REGISTERS[13].fields[14];
}

/// The fields of `EECR3`.
pub mod eecr3 {
    use super::FieldSpec;
    /// `EE6SRC`, bits 0..=1.
    pub const EE6SRC: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `EE6POL`, bit 2.
    pub const EE6POL: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `EE6SNS`, bits 3..=4.
    pub const EE6SNS: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `EE7SRC`, bits 6..=7.
    pub const EE7SRC: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `EE7POL`, bit 8.
    pub const EE7POL: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `EE7SNS`, bits 9..=10.
    pub const EE7SNS: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `EE8SRC`, bits 12..=13.
    pub const EE8SRC: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `EE8POL`, bit 14.
    pub const EE8POL: &FieldSpec = &super::REGISTERS[14].fields[7];
    /// `EE8SNS`, bits 15..=16.
    pub const EE8SNS: &FieldSpec = &super::REGISTERS[14].fields[8];
    /// `EE9SRC`, bits 18..=19.
    pub const EE9SRC: &FieldSpec = &super::REGISTERS[14].fields[9];
    /// `EE9POL`, bit 20.
    pub const EE9POL: &FieldSpec = &super::REGISTERS[14].fields[10];
    /// `EE9SNS`, bits 21..=22.
    pub const EE9SNS: &FieldSpec = &super::REGISTERS[14].fields[11];
    /// `EE10SRC`, bits 24..=25.
    pub const EE10SRC: &FieldSpec = &super::REGISTERS[14].fields[12];
    /// `EE10POL`, bit 26.
    pub const EE10POL: &FieldSpec = &super::REGISTERS[14].fields[13];
    /// `EE10SNS`, bits 27..=28.
    pub const EE10SNS: &FieldSpec = &super::REGISTERS[14].fields[14];
}

/// The fields of `ADC1R`.
pub mod adc1r {
    use super::FieldSpec;
    /// `AD1MC1`, bit 0.
    pub const AD1MC1: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `AD1MC2`, bit 1.
    pub const AD1MC2: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `AD1MC3`, bit 2.
    pub const AD1MC3: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `AD1MC4`, bit 3.
    pub const AD1MC4: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `AD1MPER`, bit 4.
    pub const AD1MPER: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `AD1EEV1`, bit 5.
    pub const AD1EEV1: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `AD1EEV2`, bit 6.
    pub const AD1EEV2: &FieldSpec = &super::REGISTERS[15].fields[6];
    /// `AD1EEV3`, bit 7.
    pub const AD1EEV3: &FieldSpec = &super::REGISTERS[15].fields[7];
    /// `AD1EEV4`, bit 8.
    pub const AD1EEV4: &FieldSpec = &super::REGISTERS[15].fields[8];
    /// `AD1EEV5`, bit 9.
    pub const AD1EEV5: &FieldSpec = &super::REGISTERS[15].fields[9];
    /// `AD1TAC2`, bit 10.
    pub const AD1TAC2: &FieldSpec = &super::REGISTERS[15].fields[10];
    /// `AD1TAC3`, bit 11.
    pub const AD1TAC3: &FieldSpec = &super::REGISTERS[15].fields[11];
    /// `AD1TAC4`, bit 12.
    pub const AD1TAC4: &FieldSpec = &super::REGISTERS[15].fields[12];
    /// `AD1TAPER`, bit 13.
    pub const AD1TAPER: &FieldSpec = &super::REGISTERS[15].fields[13];
    /// `AD1TARST`, bit 14.
    pub const AD1TARST: &FieldSpec = &super::REGISTERS[15].fields[14];
    /// `AD1TBC2`, bit 15.
    pub const AD1TBC2: &FieldSpec = &super::REGISTERS[15].fields[15];
    /// `AD1TBC3`, bit 16.
    pub const AD1TBC3: &FieldSpec = &super::REGISTERS[15].fields[16];
    /// `AD1TBC4`, bit 17.
    pub const AD1TBC4: &FieldSpec = &super::REGISTERS[15].fields[17];
    /// `AD1TBPER`, bit 18.
    pub const AD1TBPER: &FieldSpec = &super::REGISTERS[15].fields[18];
    /// `AD1TBRST`, bit 19.
    pub const AD1TBRST: &FieldSpec = &super::REGISTERS[15].fields[19];
    /// `AD1TCC2`, bit 20.
    pub const AD1TCC2: &FieldSpec = &super::REGISTERS[15].fields[20];
    /// `AD1TCC3`, bit 21.
    pub const AD1TCC3: &FieldSpec = &super::REGISTERS[15].fields[21];
    /// `AD1TCC4`, bit 22.
    pub const AD1TCC4: &FieldSpec = &super::REGISTERS[15].fields[22];
    /// `AD1TCPER`, bit 23.
    pub const AD1TCPER: &FieldSpec = &super::REGISTERS[15].fields[23];
    /// `AD1TDC2`, bit 24.
    pub const AD1TDC2: &FieldSpec = &super::REGISTERS[15].fields[24];
    /// `AD1TDC3`, bit 25.
    pub const AD1TDC3: &FieldSpec = &super::REGISTERS[15].fields[25];
    /// `AD1TDC4`, bit 26.
    pub const AD1TDC4: &FieldSpec = &super::REGISTERS[15].fields[26];
    /// `AD1TDPER`, bit 27.
    pub const AD1TDPER: &FieldSpec = &super::REGISTERS[15].fields[27];
    /// `AD1TEC2`, bit 28.
    pub const AD1TEC2: &FieldSpec = &super::REGISTERS[15].fields[28];
    /// `AD1TEC3`, bit 29.
    pub const AD1TEC3: &FieldSpec = &super::REGISTERS[15].fields[29];
    /// `AD1TEC4`, bit 30.
    pub const AD1TEC4: &FieldSpec = &super::REGISTERS[15].fields[30];
    /// `AD1TEPER`, bit 31.
    pub const AD1TEPER: &FieldSpec = &super::REGISTERS[15].fields[31];
}

/// The fields of `ADC2R`.
pub mod adc2r {
    use super::FieldSpec;
    /// `AD2MC1`, bit 0.
    pub const AD2MC1: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `AD2MC2`, bit 1.
    pub const AD2MC2: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `AD2MC3`, bit 2.
    pub const AD2MC3: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `AD2MC4`, bit 3.
    pub const AD2MC4: &FieldSpec = &super::REGISTERS[16].fields[3];
    /// `AD2MPER`, bit 4.
    pub const AD2MPER: &FieldSpec = &super::REGISTERS[16].fields[4];
    /// `AD2EEV6`, bit 5.
    pub const AD2EEV6: &FieldSpec = &super::REGISTERS[16].fields[5];
    /// `AD2EEV7`, bit 6.
    pub const AD2EEV7: &FieldSpec = &super::REGISTERS[16].fields[6];
    /// `AD2EEV8`, bit 7.
    pub const AD2EEV8: &FieldSpec = &super::REGISTERS[16].fields[7];
    /// `AD2EEV9`, bit 8.
    pub const AD2EEV9: &FieldSpec = &super::REGISTERS[16].fields[8];
    /// `AD2EEV10`, bit 9.
    pub const AD2EEV10: &FieldSpec = &super::REGISTERS[16].fields[9];
    /// `AD2TAC2`, bit 10.
    pub const AD2TAC2: &FieldSpec = &super::REGISTERS[16].fields[10];
    /// `AD2TAC3`, bit 11.
    pub const AD2TAC3: &FieldSpec = &super::REGISTERS[16].fields[11];
    /// `AD2TAC4`, bit 12.
    pub const AD2TAC4: &FieldSpec = &super::REGISTERS[16].fields[12];
    /// `AD2TAPER`, bit 13.
    pub const AD2TAPER: &FieldSpec = &super::REGISTERS[16].fields[13];
    /// `AD2TBC2`, bit 14.
    pub const AD2TBC2: &FieldSpec = &super::REGISTERS[16].fields[14];
    /// `AD2TBC3`, bit 15.
    pub const AD2TBC3: &FieldSpec = &super::REGISTERS[16].fields[15];
    /// `AD2TBC4`, bit 16.
    pub const AD2TBC4: &FieldSpec = &super::REGISTERS[16].fields[16];
    /// `AD2TBPER`, bit 17.
    pub const AD2TBPER: &FieldSpec = &super::REGISTERS[16].fields[17];
    /// `AD2TCC2`, bit 18.
    pub const AD2TCC2: &FieldSpec = &super::REGISTERS[16].fields[18];
    /// `AD2TCC3`, bit 19.
    pub const AD2TCC3: &FieldSpec = &super::REGISTERS[16].fields[19];
    /// `AD2TCC4`, bit 20.
    pub const AD2TCC4: &FieldSpec = &super::REGISTERS[16].fields[20];
    /// `AD2TCPER`, bit 21.
    pub const AD2TCPER: &FieldSpec = &super::REGISTERS[16].fields[21];
    /// `AD2TCRST`, bit 22.
    pub const AD2TCRST: &FieldSpec = &super::REGISTERS[16].fields[22];
    /// `AD2TDC2`, bit 23.
    pub const AD2TDC2: &FieldSpec = &super::REGISTERS[16].fields[23];
    /// `AD2TDC3`, bit 24.
    pub const AD2TDC3: &FieldSpec = &super::REGISTERS[16].fields[24];
    /// `AD2TDC4`, bit 25.
    pub const AD2TDC4: &FieldSpec = &super::REGISTERS[16].fields[25];
    /// `AD2TDPER`, bit 26.
    pub const AD2TDPER: &FieldSpec = &super::REGISTERS[16].fields[26];
    /// `AD2TDRST`, bit 27.
    pub const AD2TDRST: &FieldSpec = &super::REGISTERS[16].fields[27];
    /// `AD2TEC2`, bit 28.
    pub const AD2TEC2: &FieldSpec = &super::REGISTERS[16].fields[28];
    /// `AD2TEC3`, bit 29.
    pub const AD2TEC3: &FieldSpec = &super::REGISTERS[16].fields[29];
    /// `AD2TEC4`, bit 30.
    pub const AD2TEC4: &FieldSpec = &super::REGISTERS[16].fields[30];
    /// `AD2TERST`, bit 31.
    pub const AD2TERST: &FieldSpec = &super::REGISTERS[16].fields[31];
}

/// The fields of `ADC3R`.
pub mod adc3r {
    use super::FieldSpec;
    /// `AD1MC1`, bit 0.
    pub const AD1MC1: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `AD1MC2`, bit 1.
    pub const AD1MC2: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `AD1MC3`, bit 2.
    pub const AD1MC3: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `AD1MC4`, bit 3.
    pub const AD1MC4: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `AD1MPER`, bit 4.
    pub const AD1MPER: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `AD1EEV1`, bit 5.
    pub const AD1EEV1: &FieldSpec = &super::REGISTERS[17].fields[5];
    /// `AD1EEV2`, bit 6.
    pub const AD1EEV2: &FieldSpec = &super::REGISTERS[17].fields[6];
    /// `AD1EEV3`, bit 7.
    pub const AD1EEV3: &FieldSpec = &super::REGISTERS[17].fields[7];
    /// `AD1EEV4`, bit 8.
    pub const AD1EEV4: &FieldSpec = &super::REGISTERS[17].fields[8];
    /// `AD1EEV5`, bit 9.
    pub const AD1EEV5: &FieldSpec = &super::REGISTERS[17].fields[9];
    /// `AD1TAC2`, bit 10.
    pub const AD1TAC2: &FieldSpec = &super::REGISTERS[17].fields[10];
    /// `AD1TAC3`, bit 11.
    pub const AD1TAC3: &FieldSpec = &super::REGISTERS[17].fields[11];
    /// `AD1TAC4`, bit 12.
    pub const AD1TAC4: &FieldSpec = &super::REGISTERS[17].fields[12];
    /// `AD1TAPER`, bit 13.
    pub const AD1TAPER: &FieldSpec = &super::REGISTERS[17].fields[13];
    /// `AD1TARST`, bit 14.
    pub const AD1TARST: &FieldSpec = &super::REGISTERS[17].fields[14];
    /// `AD1TBC2`, bit 15.
    pub const AD1TBC2: &FieldSpec = &super::REGISTERS[17].fields[15];
    /// `AD1TBC3`, bit 16.
    pub const AD1TBC3: &FieldSpec = &super::REGISTERS[17].fields[16];
    /// `AD1TBC4`, bit 17.
    pub const AD1TBC4: &FieldSpec = &super::REGISTERS[17].fields[17];
    /// `AD1TBPER`, bit 18.
    pub const AD1TBPER: &FieldSpec = &super::REGISTERS[17].fields[18];
    /// `AD1TBRST`, bit 19.
    pub const AD1TBRST: &FieldSpec = &super::REGISTERS[17].fields[19];
    /// `AD1TCC2`, bit 20.
    pub const AD1TCC2: &FieldSpec = &super::REGISTERS[17].fields[20];
    /// `AD1TCC3`, bit 21.
    pub const AD1TCC3: &FieldSpec = &super::REGISTERS[17].fields[21];
    /// `AD1TCC4`, bit 22.
    pub const AD1TCC4: &FieldSpec = &super::REGISTERS[17].fields[22];
    /// `AD1TCPER`, bit 23.
    pub const AD1TCPER: &FieldSpec = &super::REGISTERS[17].fields[23];
    /// `AD1TDC2`, bit 24.
    pub const AD1TDC2: &FieldSpec = &super::REGISTERS[17].fields[24];
    /// `AD1TDC3`, bit 25.
    pub const AD1TDC3: &FieldSpec = &super::REGISTERS[17].fields[25];
    /// `AD1TDC4`, bit 26.
    pub const AD1TDC4: &FieldSpec = &super::REGISTERS[17].fields[26];
    /// `AD1TDPER`, bit 27.
    pub const AD1TDPER: &FieldSpec = &super::REGISTERS[17].fields[27];
    /// `AD1TEC2`, bit 28.
    pub const AD1TEC2: &FieldSpec = &super::REGISTERS[17].fields[28];
    /// `AD1TEC3`, bit 29.
    pub const AD1TEC3: &FieldSpec = &super::REGISTERS[17].fields[29];
    /// `AD1TEC4`, bit 30.
    pub const AD1TEC4: &FieldSpec = &super::REGISTERS[17].fields[30];
    /// `AD1TEPER`, bit 31.
    pub const AD1TEPER: &FieldSpec = &super::REGISTERS[17].fields[31];
}

/// The fields of `ADC4R`.
pub mod adc4r {
    use super::FieldSpec;
    /// `AD2MC1`, bit 0.
    pub const AD2MC1: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `AD2MC2`, bit 1.
    pub const AD2MC2: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `AD2MC3`, bit 2.
    pub const AD2MC3: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `AD2MC4`, bit 3.
    pub const AD2MC4: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `AD2MPER`, bit 4.
    pub const AD2MPER: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `AD2EEV6`, bit 5.
    pub const AD2EEV6: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `AD2EEV7`, bit 6.
    pub const AD2EEV7: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `AD2EEV8`, bit 7.
    pub const AD2EEV8: &FieldSpec = &super::REGISTERS[18].fields[7];
    /// `AD2EEV9`, bit 8.
    pub const AD2EEV9: &FieldSpec = &super::REGISTERS[18].fields[8];
    /// `AD2EEV10`, bit 9.
    pub const AD2EEV10: &FieldSpec = &super::REGISTERS[18].fields[9];
    /// `AD2TAC2`, bit 10.
    pub const AD2TAC2: &FieldSpec = &super::REGISTERS[18].fields[10];
    /// `AD2TAC3`, bit 11.
    pub const AD2TAC3: &FieldSpec = &super::REGISTERS[18].fields[11];
    /// `AD2TAC4`, bit 12.
    pub const AD2TAC4: &FieldSpec = &super::REGISTERS[18].fields[12];
    /// `AD2TAPER`, bit 13.
    pub const AD2TAPER: &FieldSpec = &super::REGISTERS[18].fields[13];
    /// `AD2TBC2`, bit 14.
    pub const AD2TBC2: &FieldSpec = &super::REGISTERS[18].fields[14];
    /// `AD2TBC3`, bit 15.
    pub const AD2TBC3: &FieldSpec = &super::REGISTERS[18].fields[15];
    /// `AD2TBC4`, bit 16.
    pub const AD2TBC4: &FieldSpec = &super::REGISTERS[18].fields[16];
    /// `AD2TBPER`, bit 17.
    pub const AD2TBPER: &FieldSpec = &super::REGISTERS[18].fields[17];
    /// `AD2TCC2`, bit 18.
    pub const AD2TCC2: &FieldSpec = &super::REGISTERS[18].fields[18];
    /// `AD2TCC3`, bit 19.
    pub const AD2TCC3: &FieldSpec = &super::REGISTERS[18].fields[19];
    /// `AD2TCC4`, bit 20.
    pub const AD2TCC4: &FieldSpec = &super::REGISTERS[18].fields[20];
    /// `AD2TCPER`, bit 21.
    pub const AD2TCPER: &FieldSpec = &super::REGISTERS[18].fields[21];
    /// `AD2TCRST`, bit 22.
    pub const AD2TCRST: &FieldSpec = &super::REGISTERS[18].fields[22];
    /// `AD2TDC2`, bit 23.
    pub const AD2TDC2: &FieldSpec = &super::REGISTERS[18].fields[23];
    /// `AD2TDC3`, bit 24.
    pub const AD2TDC3: &FieldSpec = &super::REGISTERS[18].fields[24];
    /// `AD2TDC4`, bit 25.
    pub const AD2TDC4: &FieldSpec = &super::REGISTERS[18].fields[25];
    /// `AD2TDPER`, bit 26.
    pub const AD2TDPER: &FieldSpec = &super::REGISTERS[18].fields[26];
    /// `AD2TDRST`, bit 27.
    pub const AD2TDRST: &FieldSpec = &super::REGISTERS[18].fields[27];
    /// `AD2TEC2`, bit 28.
    pub const AD2TEC2: &FieldSpec = &super::REGISTERS[18].fields[28];
    /// `AD2TEC3`, bit 29.
    pub const AD2TEC3: &FieldSpec = &super::REGISTERS[18].fields[29];
    /// `AD2TEC4`, bit 30.
    pub const AD2TEC4: &FieldSpec = &super::REGISTERS[18].fields[30];
    /// `AD2TERST`, bit 31.
    pub const AD2TERST: &FieldSpec = &super::REGISTERS[18].fields[31];
}

/// The fields of `DLLCR`.
pub mod dllcr {
    use super::FieldSpec;
    /// `CAL`, bit 0.
    pub const CAL: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `CALEN`, bit 1.
    pub const CALEN: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `CALRTE`, bits 2..=3.
    pub const CALRTE: &FieldSpec = &super::REGISTERS[19].fields[2];
}

/// The fields of `FLTINR1`.
pub mod fltinr1 {
    use super::FieldSpec;
    /// `FLT1E`, bit 0.
    pub const FLT1E: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `FLT1P`, bit 1.
    pub const FLT1P: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `FLT1SRC`, bit 2.
    pub const FLT1SRC: &FieldSpec = &super::REGISTERS[20].fields[2];
    /// `FLT1F`, bits 3..=6.
    pub const FLT1F: &FieldSpec = &super::REGISTERS[20].fields[3];
    /// `FLT1LCK`, bit 7.
    pub const FLT1LCK: &FieldSpec = &super::REGISTERS[20].fields[4];
    /// `FLT2E`, bit 8.
    pub const FLT2E: &FieldSpec = &super::REGISTERS[20].fields[5];
    /// `FLT2P`, bit 9.
    pub const FLT2P: &FieldSpec = &super::REGISTERS[20].fields[6];
    /// `FLT2SRC`, bit 10.
    pub const FLT2SRC: &FieldSpec = &super::REGISTERS[20].fields[7];
    /// `FLT2F`, bits 11..=14.
    pub const FLT2F: &FieldSpec = &super::REGISTERS[20].fields[8];
    /// `FLT2LCK`, bit 15.
    pub const FLT2LCK: &FieldSpec = &super::REGISTERS[20].fields[9];
    /// `FLT3E`, bit 16.
    pub const FLT3E: &FieldSpec = &super::REGISTERS[20].fields[10];
    /// `FLT3P`, bit 17.
    pub const FLT3P: &FieldSpec = &super::REGISTERS[20].fields[11];
    /// `FLT3SRC`, bit 18.
    pub const FLT3SRC: &FieldSpec = &super::REGISTERS[20].fields[12];
    /// `FLT3F`, bits 19..=22.
    pub const FLT3F: &FieldSpec = &super::REGISTERS[20].fields[13];
    /// `FLT3LCK`, bit 23.
    pub const FLT3LCK: &FieldSpec = &super::REGISTERS[20].fields[14];
    /// `FLT4E`, bit 24.
    pub const FLT4E: &FieldSpec = &super::REGISTERS[20].fields[15];
    /// `FLT4P`, bit 25.
    pub const FLT4P: &FieldSpec = &super::REGISTERS[20].fields[16];
    /// `FLT4SRC`, bit 26.
    pub const FLT4SRC: &FieldSpec = &super::REGISTERS[20].fields[17];
    /// `FLT4F`, bits 27..=30.
    pub const FLT4F: &FieldSpec = &super::REGISTERS[20].fields[18];
    /// `FLT4LCK`, bit 31.
    pub const FLT4LCK: &FieldSpec = &super::REGISTERS[20].fields[19];
}

/// The fields of `FLTINR2`.
pub mod fltinr2 {
    use super::FieldSpec;
    /// `FLT5E`, bit 0.
    pub const FLT5E: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `FLT5P`, bit 1.
    pub const FLT5P: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `FLT5SRC`, bit 2.
    pub const FLT5SRC: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `FLT5F`, bits 3..=6.
    pub const FLT5F: &FieldSpec = &super::REGISTERS[21].fields[3];
    /// `FLT5LCK`, bit 7.
    pub const FLT5LCK: &FieldSpec = &super::REGISTERS[21].fields[4];
    /// `FLTSD`, bits 24..=25.
    pub const FLTSD: &FieldSpec = &super::REGISTERS[21].fields[5];
}

/// The fields of `BDMUPDR`.
pub mod bdmupdr {
    use super::FieldSpec;
    /// `MCR`, bit 0.
    pub const MCR: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `MICR`, bit 1.
    pub const MICR: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `MDIER`, bit 2.
    pub const MDIER: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `MCNT`, bit 3.
    pub const MCNT: &FieldSpec = &super::REGISTERS[22].fields[3];
    /// `MPER`, bit 4.
    pub const MPER: &FieldSpec = &super::REGISTERS[22].fields[4];
    /// `MREP`, bit 5.
    pub const MREP: &FieldSpec = &super::REGISTERS[22].fields[5];
    /// `MCMP1`, bit 6.
    pub const MCMP1: &FieldSpec = &super::REGISTERS[22].fields[6];
    /// `MCMP2`, bit 7.
    pub const MCMP2: &FieldSpec = &super::REGISTERS[22].fields[7];
    /// `MCMP3`, bit 8.
    pub const MCMP3: &FieldSpec = &super::REGISTERS[22].fields[8];
    /// `MCMP4`, bit 9.
    pub const MCMP4: &FieldSpec = &super::REGISTERS[22].fields[9];
}

/// The fields of `BDTxUPR`.
pub mod bdtxupr {
    use super::FieldSpec;
    /// `TIMxCR`, bit 0.
    pub const TIMXCR: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `TIMxICR`, bit 1.
    pub const TIMXICR: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `TIMxDIER`, bit 2.
    pub const TIMXDIER: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `TIMxCNT`, bit 3.
    pub const TIMXCNT: &FieldSpec = &super::REGISTERS[23].fields[3];
    /// `TIMxPER`, bit 4.
    pub const TIMXPER: &FieldSpec = &super::REGISTERS[23].fields[4];
    /// `TIMxREP`, bit 5.
    pub const TIMXREP: &FieldSpec = &super::REGISTERS[23].fields[5];
    /// `TIMxCMP1`, bit 6.
    pub const TIMXCMP1: &FieldSpec = &super::REGISTERS[23].fields[6];
    /// `TIMxCMP2`, bit 7.
    pub const TIMXCMP2: &FieldSpec = &super::REGISTERS[23].fields[7];
    /// `TIMxCMP3`, bit 8.
    pub const TIMXCMP3: &FieldSpec = &super::REGISTERS[23].fields[8];
    /// `TIMxCMP4`, bit 9.
    pub const TIMXCMP4: &FieldSpec = &super::REGISTERS[23].fields[9];
    /// `TIMx_DTxR`, bit 10.
    pub const TIMX_DTXR: &FieldSpec = &super::REGISTERS[23].fields[10];
    /// `TIMxSET1R`, bit 11.
    pub const TIMXSET1R: &FieldSpec = &super::REGISTERS[23].fields[11];
    /// `TIMxRST1R`, bit 12.
    pub const TIMXRST1R: &FieldSpec = &super::REGISTERS[23].fields[12];
    /// `TIMxSET2R`, bit 13.
    pub const TIMXSET2R: &FieldSpec = &super::REGISTERS[23].fields[13];
    /// `TIMxRST2R`, bit 14.
    pub const TIMXRST2R: &FieldSpec = &super::REGISTERS[23].fields[14];
    /// `TIMxEEFR1`, bit 15.
    pub const TIMXEEFR1: &FieldSpec = &super::REGISTERS[23].fields[15];
    /// `TIMxEEFR2`, bit 16.
    pub const TIMXEEFR2: &FieldSpec = &super::REGISTERS[23].fields[16];
    /// `TIMxRSTR`, bit 17.
    pub const TIMXRSTR: &FieldSpec = &super::REGISTERS[23].fields[17];
    /// `TIMxCHPR`, bit 18.
    pub const TIMXCHPR: &FieldSpec = &super::REGISTERS[23].fields[18];
    /// `TIMxOUTR`, bit 19.
    pub const TIMXOUTR: &FieldSpec = &super::REGISTERS[23].fields[19];
    /// `TIMxFLTR`, bit 20.
    pub const TIMXFLTR: &FieldSpec = &super::REGISTERS[23].fields[20];
}

/// The fields of `BDMADR`.
pub mod bdmadr {
    use super::FieldSpec;
    /// `BDMADR`, bits 0..=31.
    pub const BDMADR: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 25] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MUDIS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TAUDIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBUDIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCUDIS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDUDIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEUDIS", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1USRC", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2USRC", bit: 19, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD3USRC", bit: 22, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD4USRC", bit: 25, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MSWU", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TASWU", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBSWU", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCSWU", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDSWU", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TESWU", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TARST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBRST", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCRST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDRST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TERST", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLT1", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSFLT", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLLRDY", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMPER", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLT1C", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2C", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3C", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4C", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5C", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSFLTC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLLRDYC", bit: 16, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMPERC", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLT1IE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2IE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3IE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4IE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5IE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYSFLTE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLLRDYIE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMPERIE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OENR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TA1OEN", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TA2OEN", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB1OEN", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB2OEN", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC1OEN", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC2OEN", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD1OEN", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD2OEN", bit: 7, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE1OEN", bit: 8, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE2OEN", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DISR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TA1ODIS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TA2ODIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB1ODIS", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB2ODIS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC1ODIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC2ODIS", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD1ODIS", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD2ODIS", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE1ODIS", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE2ODIS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ODSR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TA1ODS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TA2ODS", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB1ODS", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TB2ODS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC1ODS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC2ODS", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD1ODS", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TD2ODS", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE1ODS", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE2ODS", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BMCR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BME", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMOM", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMCLK", bit: 2, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMPRSC", bit: 6, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMPREN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MTBM", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TABM", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBBM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCBM", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDBM", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEBM", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BMSTAT", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BMTRG", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SW", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTRST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTREP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTCMP1", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTCMP2", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTCMP3", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSTCMP4", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TARST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TAREP", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TACMP1", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TACMP2", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBRST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBREP", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBCMP1", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TBCMP2", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCRST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCREP", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCCMP1", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCCMP2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDRST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDREP", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDCMP1", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TDCMP2", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TERST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEREP", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TECMP1", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TECMP2", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OCHPEV", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BMCMPR6", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BMCMP", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BMPER", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BMPER", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EECR1", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EE1SRC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE1POL", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE1SNS", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE1FAST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE2SRC", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE2POL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE2SNS", bit: 9, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE2FAST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE3SRC", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE3POL", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE3SNS", bit: 15, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE3FAST", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE4SRC", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE4POL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE4SNS", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE4FAST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE5SRC", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE5POL", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE5SNS", bit: 27, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE5FAST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EECR2", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EE6SRC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE6POL", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE6SNS", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7SRC", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7POL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7SNS", bit: 9, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8SRC", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8POL", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8SNS", bit: 15, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9SRC", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9POL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9SNS", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10SRC", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10POL", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10SNS", bit: 27, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EECR3", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EE6SRC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE6POL", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE6SNS", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7SRC", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7POL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE7SNS", bit: 9, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8SRC", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8POL", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE8SNS", bit: 15, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9SRC", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9POL", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE9SNS", bit: 21, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10SRC", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10POL", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EE10SNS", bit: 27, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ADC1R", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AD1MC1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV1", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV2", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV3", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV4", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV5", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC2", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC3", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC4", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAPER", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TARST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC2", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC3", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC4", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBPER", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBRST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC2", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC3", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC4", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCPER", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC2", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC3", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC4", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDPER", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC3", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC4", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEPER", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ADC2R", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AD2MC1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV6", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV7", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV8", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV9", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV10", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC2", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC3", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC4", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAPER", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC2", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC3", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC4", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBPER", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC3", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC4", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCPER", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCRST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC3", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC4", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDPER", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDRST", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC3", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC4", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TERST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ADC3R", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AD1MC1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MC4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1MPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV1", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV2", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV3", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV4", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1EEV5", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC2", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC3", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAC4", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TAPER", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TARST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC2", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC3", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBC4", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBPER", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TBRST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC2", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC3", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCC4", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TCPER", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC2", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC3", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDC4", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TDPER", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC3", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEC4", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD1TEPER", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ADC4R", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AD2MC1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MC4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2MPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV6", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV7", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV8", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV9", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2EEV10", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC2", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC3", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAC4", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TAPER", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC2", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC3", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBC4", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TBPER", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC2", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC3", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCC4", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCPER", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TCRST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC3", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDC4", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDPER", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TDRST", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC2", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC3", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TEC4", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AD2TERST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DLLCR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CAL", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALRTE", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FLTINR1", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLT1E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT1P", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT1SRC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT1F", bit: 3, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT1LCK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2E", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2P", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2SRC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2F", bit: 11, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT2LCK", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3E", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3P", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3SRC", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3F", bit: 19, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT3LCK", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4E", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4P", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4SRC", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4F", bit: 27, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT4LCK", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FLTINR2", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FLT5E", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5P", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5SRC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5F", bit: 3, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLT5LCK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLTSD", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMUPDR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MCR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MICR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MDIER", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCNT", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MREP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP2", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP3", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCMP4", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDTxUPR", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIMxCR", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxICR", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxDIER", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCNT", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxPER", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxREP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCMP1", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCMP2", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCMP3", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCMP4", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMx_DTxR", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxSET1R", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxRST1R", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxSET2R", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxRST2R", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxEEFR1", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxEEFR2", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxRSTR", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxCHPR", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxOUTR", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TIMxFLTR", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BDMADR", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BDMADR", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];