rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `LPUART1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr1 = 0,
    /// `CR2` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cr2 = 1,
    /// `CR3` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cr3 = 2,
    /// `BRR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Brr = 3,
    /// `GTPR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Gtpr = 4,
    /// `RTOR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Rtor = 5,
    /// `RQR` at offset `0x18`, resets to `0x0000_0000`, write-only.
    Rqr = 6,
    /// `ISR` at offset `0x1C`, resets to `0x0000_00C0`, read-only.
    Isr = 7,
    /// `ICR` at offset `0x20`, resets to `0x0000_0000`, write-only.
    Icr = 8,
    /// `RDR` at offset `0x24`, resets to `0x0000_0000`, read-only.
    Rdr = 9,
    /// `TDR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Tdr = 10,
    /// `PRESC` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Presc = 11,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 12] = [Self::Cr1, Self::Cr2, Self::Cr3, Self::Brr, Self::Gtpr, Self::Rtor, Self::Rqr, Self::Isr, Self::Icr, Self::Rdr, Self::Tdr, Self::Presc];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `UE`, bit 0.
    pub const UE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `UESM`, bit 1.
    pub const UESM: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `RE`, bit 2.
    pub const RE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TE`, bit 3.
    pub const TE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `IDLEIE`, bit 4.
    pub const IDLEIE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `RXNEIE`, bit 5.
    pub const RXNEIE: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `TCIE`, bit 6.
    pub const TCIE: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `TXEIE`, bit 7.
    pub const TXEIE: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `PEIE`, bit 8.
    pub const PEIE: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `PS`, bit 9.
    pub const PS: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `PCE`, bit 10.
    pub const PCE: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `WAKE`, bit 11.
    pub const WAKE: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `M0`, bit 12.
    pub const M0: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `MME`, bit 13.
    pub const MME: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `CMIE`, bit 14.
    pub const CMIE: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `DEDT`, bits 16..=20.
    pub const DEDT: &FieldSpec = &super::REGISTERS[0].fields[15];
    /// `DEAT`, bits 21..=25.
    pub const DEAT: &FieldSpec = &super::REGISTERS[0].fields[16];
    /// `M1`, bit 28.
    pub const M1: &FieldSpec = &super::REGISTERS[0].fields[17];
    /// `FIFOEN`, bit 29.
    pub const FIFOEN: &FieldSpec = &super::REGISTERS[0].fields[18];
    /// `TXFEIE`, bit 30.
    pub const TXFEIE: &FieldSpec = &super::REGISTERS[0].fields[19];
    /// `RXFFIE`, bit 31.
    pub const RXFFIE: &FieldSpec = &super::REGISTERS[0].fields[20];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `ADDM7`, bit 4.
    pub const ADDM7: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `STOP`, bits 12..=13.
    pub const STOP: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SWAP`, bit 15.
    pub const SWAP: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `RXINV`, bit 16.
    pub const RXINV: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `TXINV`, bit 17.
    pub const TXINV: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `DATAINV`, bit 18.
    pub const DATAINV: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `MSBFIRST`, bit 19.
    pub const MSBFIRST: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `ADD`, bits 24..=31.
    pub const ADD: &FieldSpec = &super::REGISTERS[1].fields[7];
}

/// The fields of `CR3`.
pub mod cr3 {
    use super::FieldSpec;
    /// `EIE`, bit 0.
    pub const EIE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `HDSEL`, bit 3.
    pub const HDSEL: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `DMAR`, bit 6.
    pub const DMAR: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `DMAT`, bit 7.
    pub const DMAT: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `RTSE`, bit 8.
    pub const RTSE: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CTSE`, bit 9.
    pub const CTSE: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `CTSIE`, bit 10.
    pub const CTSIE: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `OVRDIS`, bit 12.
    pub const OVRDIS: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `DDRE`, bit 13.
    pub const DDRE: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `DEM`, bit 14.
    pub const DEM: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `DEP`, bit 15.
    pub const DEP: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `WUS`, bits 20..=21.
    pub const WUS: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `WUFIE`, bit 22.
    pub const WUFIE: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `TXFTIE`, bit 23.
    pub const TXFTIE: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `RXFTCFG`, bits 25..=27.
    pub const RXFTCFG: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `RXFTIE`, bit 28.
    pub const RXFTIE: &FieldSpec = &super::REGISTERS[2].fields[15];
    /// `TXFTCFG`, bits 29..=31.
    pub const TXFTCFG: &FieldSpec = &super::REGISTERS[2].fields[16];
}

/// The fields of `BRR`.
pub mod brr {
    use super::FieldSpec;
    /// `BRR`, bits 0..=19.
    pub const BRR: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `GTPR`.
pub mod gtpr {
    use super::FieldSpec;
    /// `PSC`, bits 0..=7.
    pub const PSC: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `GT`, bits 8..=15.
    pub const GT: &FieldSpec = &super::REGISTERS[4].fields[1];
}

/// The fields of `RTOR`.
pub mod rtor {
    use super::FieldSpec;
    /// `RTO`, bits 0..=23.
    pub const RTO: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `BLEN`, bits 24..=31.
    pub const BLEN: &FieldSpec = &super::REGISTERS[5].fields[1];
}

/// The fields of `RQR`.
pub mod rqr {
    use super::FieldSpec;
    /// `ABRRQ`, bit 0.
    pub const ABRRQ: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `SBKRQ`, bit 1.
    pub const SBKRQ: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `MMRQ`, bit 2.
    pub const MMRQ: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `RXFRQ`, bit 3.
    pub const RXFRQ: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `TXFRQ`, bit 4.
    pub const TXFRQ: &FieldSpec = &super::REGISTERS[6].fields[4];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `PE`, bit 0.
    pub const PE: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `FE`, bit 1.
    pub const FE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `NE`, bit 2.
    pub const NE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `ORE`, bit 3.
    pub const ORE: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `IDLE`, bit 4.
    pub const IDLE: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `RXNE`, bit 5.
    pub const RXNE: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `TC`, bit 6.
    pub const TC: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `TXE`, bit 7.
    pub const TXE: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `CTSIF`, bit 9.
    pub const CTSIF: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `CTS`, bit 10.
    pub const CTS: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `BUSY`, bit 16.
    pub const BUSY: &FieldSpec = &super::REGISTERS[7].fields[10];
    /// `CMF`, bit 17.
    pub const CMF: &FieldSpec = &super::REGISTERS[7].fields[11];
    /// `SBKF`, bit 18.
    pub const SBKF: &FieldSpec = &super::REGISTERS[7].fields[12];
    /// `RWU`, bit 19.
    pub const RWU: &FieldSpec = &super::REGISTERS[7].fields[13];
    /// `WUF`, bit 20.
    pub const WUF: &FieldSpec = &super::REGISTERS[7].fields[14];
    /// `TEACK`, bit 21.
    pub const TEACK: &FieldSpec = &super::REGISTERS[7].fields[15];
    /// `REACK`, bit 22.
    pub const REACK: &FieldSpec = &super::REGISTERS[7].fields[16];
    /// `TXFE`, bit 23.
    pub const TXFE: &FieldSpec = &super::REGISTERS[7].fields[17];
    /// `RXFF`, bit 24.
    pub const RXFF: &FieldSpec = &super::REGISTERS[7].fields[18];
    /// `RXFT`, bit 26.
    pub const RXFT: &FieldSpec = &super::REGISTERS[7].fields[19];
    /// `TXFT`, bit 27.
    pub const TXFT: &FieldSpec = &super::REGISTERS[7].fields[20];
}

/// The fields of `ICR`.
pub mod icr {
    use super::FieldSpec;
    /// `PECF`, bit 0.
    pub const PECF: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `FECF`, bit 1.
    pub const FECF: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `NCF`, bit 2.
    pub const NCF: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `ORECF`, bit 3.
    pub const ORECF: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `IDLECF`, bit 4.
    pub const IDLECF: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `TCCF`, bit 6.
    pub const TCCF: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `CTSCF`, bit 9.
    pub const CTSCF: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `CMCF`, bit 17.
    pub const CMCF: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `WUCF`, bit 20.
    pub const WUCF: &FieldSpec = &super::REGISTERS[8].fields[8];
}

/// The fields of `RDR`.
pub mod rdr {
    use super::FieldSpec;
    /// `RDR`, bits 0..=8.
    pub const RDR: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `TDR`.
pub mod tdr {
    use super::FieldSpec;
    /// `TDR`, bits 0..=8.
    pub const TDR: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `PRESC`.
pub mod presc {
    use super::FieldSpec;
    /// `PRESCALER`, bits 0..=3.
    pub const PRESCALER: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 12] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UESM", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDLEIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNEIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXEIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PEIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WAKE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "M0", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MME", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMIE", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEDT", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEAT", bit: 21, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "M1", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FIFOEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFEIE", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFFIE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDM7", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOP", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SWAP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXINV", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXINV", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATAINV", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MSBFIRST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADD", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR3", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HDSEL", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAR", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAT", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RTSE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTSE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTSIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRDIS", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DDRE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEM", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEP", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WUS", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WUFIE", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFTIE", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFTCFG", bit: 25, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFTIE", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFTCFG", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BRR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BRR", bit: 0, width: 20, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "GTPR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PSC", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GT", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RTOR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RTO", bit: 0, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BLEN", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RQR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ABRRQ", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBKRQ", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MMRQ", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFRQ", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFRQ", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x1C, width: Width::W32, reset: 0x0000_00C0, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NE", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ORE", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDLE", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXNE", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TC", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXE", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTSIF", bit: 9, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTS", bit: 10, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSY", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMF", bit: 17, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBKF", bit: 18, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RWU", bit: 19, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WUF", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEACK", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REACK", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFE", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFF", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXFT", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXFT", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ICR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PECF", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FECF", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NCF", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ORECF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDLECF", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCCF", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTSCF", bit: 9, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMCF", bit: 17, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WUCF", bit: 20, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "RDR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDR", bit: 0, width: 9, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "TDR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TDR", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PRESC", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PRESCALER", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];