rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DELAY_Block_SDMMC1` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `CFGR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Cfgr = 1,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 2] = [Self::Cr, Self::Cfgr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `DEN`, bit 0.
    pub const DEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SEN`, bit 1.
    pub const SEN: &FieldSpec = &super::REGISTERS[0].fields[1];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `SEL`, bits 0..=3.
    pub const SEL: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `UNIT`, bits 8..=14.
    pub const UNIT: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `LNG`, bits 16..=27.
    pub const LNG: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `LNGF`, bit 31.
    pub const LNGF: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 2] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SEL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UNIT", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LNG", bit: 16, width: 12, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LNGF", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];