rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `Ethernet_MTL` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `MTLOMR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Mtlomr = 0,
    /// `MTLISR` at offset `0x20`, resets to `0x0000_0000`, read-only.
    Mtlisr = 1,
    /// `MTLTxQOMR` at offset `0x100`, resets to `0x0007_0008`, read-write.
    Mtltxqomr = 2,
    /// `MTLTxQUR` at offset `0x104`, resets to `0x0000_0000`, read-only.
    Mtltxqur = 3,
    /// `MTLTxQDR` at offset `0x108`, resets to `0x0000_0000`, read-only.
    Mtltxqdr = 4,
    /// `MTLQICSR` at offset `0x12C`, resets to `0x0000_0000`, read-write.
    Mtlqicsr = 5,
    /// `MTLRxQOMR` at offset `0x130`, resets to `0x0070_0000`, read-write.
    Mtlrxqomr = 6,
    /// `MTLRxQMPOCR` at offset `0x134`, resets to `0x0000_0000`, read-only.
    Mtlrxqmpocr = 7,
    /// `MTLRxQDR` at offset `0x138`, resets to `0x0000_0000`, read-only.
    Mtlrxqdr = 8,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 9] = [Self::Mtlomr, Self::Mtlisr, Self::Mtltxqomr, Self::Mtltxqur, Self::Mtltxqdr, Self::Mtlqicsr, Self::Mtlrxqomr, Self::Mtlrxqmpocr, Self::Mtlrxqdr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `MTLOMR`.
pub mod mtlomr {
    use super::FieldSpec;
    /// `DTXSTS`, bit 1.
    pub const DTXSTS: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `CNTPRST`, bit 8.
    pub const CNTPRST: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `CNTCLR`, bit 9.
    pub const CNTCLR: &FieldSpec = &super::REGISTERS[0].fields[2];
}

/// The fields of `MTLISR`.
pub mod mtlisr {
    use super::FieldSpec;
    /// `Q0IS`, bit 0.
    pub const Q0IS: &FieldSpec = &super::REGISTERS[1].fields[0];
}

/// The fields of `MTLTxQOMR`.
pub mod mtltxqomr {
    use super::FieldSpec;
    /// `FTQ`, bit 0.
    pub const FTQ: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TSF`, bit 1.
    pub const TSF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `TXQEN`, bits 2..=3, read-only.
    pub const TXQEN: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `TTC`, bits 4..=6.
    pub const TTC: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `TQS`, bits 16..=18.
    pub const TQS: &FieldSpec = &super::REGISTERS[2].fields[4];
}

/// The fields of `MTLTxQUR`.
pub mod mtltxqur {
    use super::FieldSpec;
    /// `UFFRMCNT`, bits 0..=10.
    pub const UFFRMCNT: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `UFCNTOVF`, bit 11.
    pub const UFCNTOVF: &FieldSpec = &super::REGISTERS[3].fields[1];
}

/// The fields of `MTLTxQDR`.
pub mod mtltxqdr {
    use super::FieldSpec;
    /// `TXQPAUSED`, bit 0.
    pub const TXQPAUSED: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `TRCSTS`, bits 1..=2.
    pub const TRCSTS: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `TWCSTS`, bit 3.
    pub const TWCSTS: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `TXQSTS`, bit 4.
    pub const TXQSTS: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `TXSTSFSTS`, bit 5.
    pub const TXSTSFSTS: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `PTXQ`, bits 16..=18.
    pub const PTXQ: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `STXSTSF`, bits 20..=22.
    pub const STXSTSF: &FieldSpec = &super::REGISTERS[4].fields[6];
}

/// The fields of `MTLQICSR`.
pub mod mtlqicsr {
    use super::FieldSpec;
    /// `TXUNFIS`, bit 0.
    pub const TXUNFIS: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TXUIE`, bit 8.
    pub const TXUIE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `RXOVFIS`, bit 16.
    pub const RXOVFIS: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `RXOIE`, bit 24.
    pub const RXOIE: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `MTLRxQOMR`.
pub mod mtlrxqomr {
    use super::FieldSpec;
    /// `RTC`, bits 0..=1.
    pub const RTC: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `FUP`, bit 3.
    pub const FUP: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `FEP`, bit 4.
    pub const FEP: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `RSF`, bit 5.
    pub const RSF: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `DIS_TCP_EF`, bit 6.
    pub const DIS_TCP_EF: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `EHFC`, bit 7.
    pub const EHFC: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `RFA`, bits 8..=10.
    pub const RFA: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `RFD`, bits 14..=16.
    pub const RFD: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `RQS`, bits 20..=22, read-only.
    pub const RQS: &FieldSpec = &super::REGISTERS[6].fields[8];
}

/// The fields of `MTLRxQMPOCR`.
pub mod mtlrxqmpocr {
    use super::FieldSpec;
    /// `OVFPKTCNT`, bits 0..=10.
    pub const OVFPKTCNT: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `OVFCNTOVF`, bit 11.
    pub const OVFCNTOVF: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `MISPKTCNT`, bits 16..=26.
    pub const MISPKTCNT: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `MISCNTOVF`, bit 27.
    pub const MISCNTOVF: &FieldSpec = &super::REGISTERS[7].fields[3];
}

/// The fields of `MTLRxQDR`.
pub mod mtlrxqdr {
    use super::FieldSpec;
    /// `RWCSTS`, bit 0.
    pub const RWCSTS: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `RRCSTS`, bits 1..=2.
    pub const RRCSTS: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `RXQSTS`, bits 4..=5.
    pub const RXQSTS: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `PRXQ`, bits 16..=29.
    pub const PRXQ: &FieldSpec = &super::REGISTERS[8].fields[3];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 9] = [
    RegisterSpec { name: "MTLOMR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTXSTS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTPRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNTCLR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLISR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "Q0IS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLTxQOMR", offset: 0x100, width: Width::W32, reset: 0x0007_0008, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTQ", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXQEN", bit: 2, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TTC", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TQS", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLTxQUR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "UFFRMCNT", bit: 0, width: 11, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "UFCNTOVF", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLTxQDR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXQPAUSED", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRCSTS", bit: 1, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWCSTS", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXQSTS", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXSTSFSTS", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTXQ", bit: 16, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STXSTSF", bit: 20, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLQICSR", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TXUNFIS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TXUIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOVFIS", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXOIE", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLRxQOMR", offset: 0x130, width: Width::W32, reset: 0x0070_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RTC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FUP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FEP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DIS_TCP_EF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EHFC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFA", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RFD", bit: 14, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RQS", bit: 20, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLRxQMPOCR", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVFPKTCNT", bit: 0, width: 11, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVFCNTOVF", bit: 11, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MISPKTCNT", bit: 16, width: 11, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MISCNTOVF", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "MTLRxQDR", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RWCSTS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RRCSTS", bit: 1, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXQSTS", bit: 4, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRXQ", bit: 16, width: 14, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];