rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `JPEG` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CONFR0` at offset `0x0`, resets to `0x0000_0000`, write-only.
    Confr0 = 0,
    /// `CONFR1` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Confr1 = 1,
    /// `CONFR2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Confr2 = 2,
    /// `CONFR3` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Confr3 = 3,
    /// `CONFRN1` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Confrn1 = 4,
    /// `CONFRN2` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Confrn2 = 5,
    /// `CONFRN3` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Confrn3 = 6,
    /// `CONFRN4` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Confrn4 = 7,
    /// `CR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Cr = 8,
    /// `SR` at offset `0x34`, resets to `0x0000_0006`, read-only.
    Sr = 9,
    /// `CFR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Cfr = 10,
    /// `DIR` at offset `0x40`, resets to `0x0000_0000`, write-only.
    Dir = 11,
    /// `DOR` at offset `0x44`, resets to `0x0000_0000`, read-only.
    Dor = 12,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 13] = [Self::Confr0, Self::Confr1, Self::Confr2, Self::Confr3, Self::Confrn1, Self::Confrn2, Self::Confrn3, Self::Confrn4, Self::Cr, Self::Sr, Self::Cfr, Self::Dir, Self::Dor];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CONFR0`.
pub mod confr0 {
    use super::FieldSpec;
    /// `START`, bit 0.
    pub const START: &FieldSpec = &super::REGISTERS[0].fields[0];
}

/// The fields of `CONFR1`.
pub mod confr1 {
    use super::FieldSpec;
    /// `NF`, bits 0..=1.
    pub const NF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `DE`, bit 3.
    pub const DE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `COLORSPACE`, bits 4..=5.
    pub const COLORSPACE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `NS`, bits 6..=7.
    pub const NS: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `HDR`, bit 8.
    pub const HDR: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `YSIZE`, bits 16..=31.
    pub const YSIZE: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `CONFR2`.
pub mod confr2 {
    use super::FieldSpec;
    /// `NMCU`, bits 0..=25.
    pub const NMCU: &FieldSpec = &super::REGISTERS[2].fields[0];
}

/// The fields of `CONFR3`.
pub mod confr3 {
    use super::FieldSpec;
    /// `XSIZE`, bits 16..=31.
    pub const XSIZE: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `CONFRN1`.
pub mod confrn1 {
    use super::FieldSpec;
    /// `HD`, bit 0.
    pub const HD: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `HA`, bit 1.
    pub const HA: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `QT`, bits 2..=3.
    pub const QT: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `NB`, bits 4..=7.
    pub const NB: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `VSF`, bits 8..=11.
    pub const VSF: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `HSF`, bits 12..=15.
    pub const HSF: &FieldSpec = &super::REGISTERS[4].fields[5];
}

/// The fields of `CONFRN2`.
pub mod confrn2 {
    use super::FieldSpec;
    /// `HD`, bit 0.
    pub const HD: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `HA`, bit 1.
    pub const HA: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `QT`, bits 2..=3.
    pub const QT: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `NB`, bits 4..=7.
    pub const NB: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `VSF`, bits 8..=11.
    pub const VSF: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `HSF`, bits 12..=15.
    pub const HSF: &FieldSpec = &super::REGISTERS[5].fields[5];
}

/// The fields of `CONFRN3`.
pub mod confrn3 {
    use super::FieldSpec;
    /// `HD`, bit 0.
    pub const HD: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `HA`, bit 1.
    pub const HA: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `QT`, bits 2..=3.
    pub const QT: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `NB`, bits 4..=7.
    pub const NB: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `VSF`, bits 8..=11.
    pub const VSF: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `HSF`, bits 12..=15.
    pub const HSF: &FieldSpec = &super::REGISTERS[6].fields[5];
}

/// The fields of `CONFRN4`.
pub mod confrn4 {
    use super::FieldSpec;
    /// `HD`, bit 0.
    pub const HD: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `HA`, bit 1.
    pub const HA: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `QT`, bits 2..=3.
    pub const QT: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `NB`, bits 4..=7.
    pub const NB: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `VSF`, bits 8..=11.
    pub const VSF: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `HSF`, bits 12..=15.
    pub const HSF: &FieldSpec = &super::REGISTERS[7].fields[5];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `JCEN`, bit 0.
    pub const JCEN: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `IFTIE`, bit 1.
    pub const IFTIE: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `IFNFIE`, bit 2.
    pub const IFNFIE: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `OFTIE`, bit 3.
    pub const OFTIE: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `OFNEIE`, bit 4.
    pub const OFNEIE: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `EOCIE`, bit 5.
    pub const EOCIE: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `HPDIE`, bit 6.
    pub const HPDIE: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `IDMAEN`, bit 11.
    pub const IDMAEN: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `ODMAEN`, bit 12.
    pub const ODMAEN: &FieldSpec = &super::REGISTERS[8].fields[8];
    /// `IFF`, bit 13.
    pub const IFF: &FieldSpec = &super::REGISTERS[8].fields[9];
    /// `OFF`, bit 14.
    pub const OFF: &FieldSpec = &super::REGISTERS[8].fields[10];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `IFTF`, bit 1.
    pub const IFTF: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `IFNFF`, bit 2.
    pub const IFNFF: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `OFTF`, bit 3.
    pub const OFTF: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `OFNEF`, bit 4.
    pub const OFNEF: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `EOCF`, bit 5.
    pub const EOCF: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `HPDF`, bit 6.
    pub const HPDF: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `COF`, bit 7.
    pub const COF: &FieldSpec = &super::REGISTERS[9].fields[6];
}

/// The fields of `CFR`.
pub mod cfr {
    use super::FieldSpec;
    /// `CEOCF`, bit 5.
    pub const CEOCF: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `CHPDF`, bit 6.
    pub const CHPDF: &FieldSpec = &super::REGISTERS[10].fields[1];
}

/// The fields of `DIR`.
pub mod dir {
    use super::FieldSpec;
    /// `DATAIN`, bits 0..=31.
    pub const DATAIN: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `DOR`.
pub mod dor {
    use super::FieldSpec;
    /// `DATAOUT`, bits 0..=31.
    pub const DATAOUT: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 13] = [
    RegisterSpec { name: "CONFR0", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "START", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFR1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NF", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COLORSPACE", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NS", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HDR", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "YSIZE", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFR2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NMCU", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFR3", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "XSIZE", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFRN1", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "QT", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSF", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFRN2", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "QT", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSF", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFRN3", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "QT", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSF", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CONFRN4", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HD", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HA", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "QT", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NB", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VSF", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSF", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JCEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFTIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFNFIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFTIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFNEIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPDIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IDMAEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ODMAEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFF", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFF", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x34, width: Width::W32, reset: 0x0000_0006, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IFTF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFNFF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFTF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFNEF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOCF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HPDF", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COF", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CEOCF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHPDF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATAIN", bit: 0, width: 32, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DOR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATAOUT", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];