rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `QUADSPI` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `DCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Dcr = 1,
    /// `SR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Sr = 2,
    /// `FCR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Fcr = 3,
    /// `DLR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Dlr = 4,
    /// `CCR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Ccr = 5,
    /// `AR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Ar = 6,
    /// `ABR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Abr = 7,
    /// `DR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Dr = 8,
    /// `PSMKR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Psmkr = 9,
    /// `PSMAR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Psmar = 10,
    /// `PIR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Pir = 11,
    /// `LPTR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Lptr = 12,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 13] = [Self::Cr, Self::Dcr, Self::Sr, Self::Fcr, Self::Dlr, Self::Ccr, Self::Ar, Self::Abr, Self::Dr, Self::Psmkr, Self::Psmar, Self::Pir, Self::Lptr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `ABORT`, bit 1.
    pub const ABORT: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `DMAEN`, bit 2.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TCEN`, bit 3.
    pub const TCEN: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `SSHIFT`, bit 4.
    pub const SSHIFT: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `DFM`, bit 6.
    pub const DFM: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `FSEL`, bit 7.
    pub const FSEL: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `FTHRES`, bits 8..=12.
    pub const FTHRES: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `TEIE`, bit 16.
    pub const TEIE: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `TCIE`, bit 17.
    pub const TCIE: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `FTIE`, bit 18.
    pub const FTIE: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `SMIE`, bit 19.
    pub const SMIE: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `TOIE`, bit 20.
    pub const TOIE: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `APMS`, bit 22.
    pub const APMS: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `PMM`, bit 23.
    pub const PMM: &FieldSpec = &super::REGISTERS[0].fields[14];
    /// `PRESCALER`, bits 24..=31.
    pub const PRESCALER: &FieldSpec = &super::REGISTERS[0].fields[15];
}

/// The fields of `DCR`.
pub mod dcr {
    use super::FieldSpec;
    /// `CKMODE`, bit 0.
    pub const CKMODE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CSHT`, bits 8..=10.
    pub const CSHT: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `FSIZE`, bits 16..=20.
    pub const FSIZE: &FieldSpec = &super::REGISTERS[1].fields[2];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `TEF`, bit 0.
    pub const TEF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TCF`, bit 1.
    pub const TCF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `FTF`, bit 2.
    pub const FTF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `SMF`, bit 3.
    pub const SMF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `TOF`, bit 4.
    pub const TOF: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `BUSY`, bit 5.
    pub const BUSY: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `FLEVEL`, bits 8..=13.
    pub const FLEVEL: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `FCR`.
pub mod fcr {
    use super::FieldSpec;
    /// `CTEF`, bit 0.
    pub const CTEF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `CTCF`, bit 1.
    pub const CTCF: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `CSMF`, bit 3.
    pub const CSMF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `CTOF`, bit 4.
    pub const CTOF: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `DLR`.
pub mod dlr {
    use super::FieldSpec;
    /// `DL`, bits 0..=31.
    pub const DL: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `CCR`.
pub mod ccr {
    use super::FieldSpec;
    /// `INSTRUCTION`, bits 0..=7.
    pub const INSTRUCTION: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `IMODE`, bits 8..=9.
    pub const IMODE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `ADMODE`, bits 10..=11.
    pub const ADMODE: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `ADSIZE`, bits 12..=13.
    pub const ADSIZE: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `ABMODE`, bits 14..=15.
    pub const ABMODE: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `ABSIZE`, bits 16..=17.
    pub const ABSIZE: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `DCYC`, bits 18..=22.
    pub const DCYC: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `DMODE`, bits 24..=25.
    pub const DMODE: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `FMODE`, bits 26..=27.
    pub const FMODE: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `SIOO`, bit 28.
    pub const SIOO: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `DHHC`, bit 30.
    pub const DHHC: &FieldSpec = &super::REGISTERS[5].fields[10];
    /// `DDRM`, bit 31.
    pub const DDRM: &FieldSpec = &super::REGISTERS[5].fields[11];
}

/// The fields of `AR`.
pub mod ar {
    use super::FieldSpec;
    /// `ADDRESS`, bits 0..=31.
    pub const ADDRESS: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `ABR`.
pub mod abr {
    use super::FieldSpec;
    /// `ALTERNATE`, bits 0..=31.
    pub const ALTERNATE: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=31.
    pub const DATA: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `PSMKR`.
pub mod psmkr {
    use super::FieldSpec;
    /// `MASK`, bits 0..=31.
    pub const MASK: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `PSMAR`.
pub mod psmar {
    use super::FieldSpec;
    /// `MATCH`, bits 0..=31.
    pub const MATCH: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `PIR`.
pub mod pir {
    use super::FieldSpec;
    /// `INTERVAL`, bits 0..=15.
    pub const INTERVAL: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `LPTR`.
pub mod lptr {
    use super::FieldSpec;
    /// `TIMEOUT`, bits 0..=15.
    pub const TIMEOUT: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 13] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ABORT", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSHIFT", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFM", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSEL", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FTHRES", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FTIE", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMIE", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOIE", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "APMS", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PMM", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRESCALER", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CKMODE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSHT", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSIZE", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TEF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FTF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TOF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BUSY", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLEVEL", bit: 8, width: 6, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FCR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CTEF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSMF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTOF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DLR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DL", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INSTRUCTION", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IMODE", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADMODE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADSIZE", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ABMODE", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ABSIZE", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DCYC", bit: 18, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMODE", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FMODE", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SIOO", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DHHC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DDRM", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADDRESS", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ABR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ALTERNATE", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PSMKR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MASK", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PSMAR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MATCH", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PIR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INTERVAL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LPTR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TIMEOUT", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];