rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SYSCFG` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `PMCR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Pmcr = 0,
    /// `EXTICR1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Exticr1 = 1,
    /// `EXTICR2` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Exticr2 = 2,
    /// `EXTICR3` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Exticr3 = 3,
    /// `EXTICR4` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Exticr4 = 4,
    /// `CCCSR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Cccsr = 5,
    /// `CCVR` at offset `0x24`, resets to `0x0000_0000`, read-only.
    Ccvr = 6,
    /// `CCCR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Cccr = 7,
    /// `PWRCR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Pwrcr = 8,
    /// `PKGR` at offset `0x124`, resets to `0x0000_0000`, read-only.
    Pkgr = 9,
    /// `UR0` at offset `0x300`, resets to `0x0000_0000`, read-only.
    Ur0 = 10,
    /// `UR2` at offset `0x308`, resets to `0x0000_0000`, read-write.
    Ur2 = 11,
    /// `UR3` at offset `0x30C`, resets to `0x0000_0000`, read-write.
    Ur3 = 12,
    /// `UR4` at offset `0x310`, resets to `0x0000_0000`, read-only.
    Ur4 = 13,
    /// `UR5` at offset `0x314`, resets to `0x0000_0000`, read-only.
    Ur5 = 14,
    /// `UR6` at offset `0x318`, resets to `0x0000_0000`, read-only.
    Ur6 = 15,
    /// `UR7` at offset `0x31C`, resets to `0x0000_0000`, read-only.
    Ur7 = 16,
    /// `UR8` at offset `0x320`, resets to `0x0000_0000`, read-only.
    Ur8 = 17,
    /// `UR9` at offset `0x324`, resets to `0x0000_0000`, read-only.
    Ur9 = 18,
    /// `UR10` at offset `0x328`, resets to `0x0000_0000`, read-only.
    Ur10 = 19,
    /// `UR11` at offset `0x32C`, resets to `0x0000_0000`, read-only.
    Ur11 = 20,
    /// `UR12` at offset `0x330`, resets to `0x0000_0000`, read-only.
    Ur12 = 21,
    /// `UR13` at offset `0x334`, resets to `0x0000_0000`, read-only.
    Ur13 = 22,
    /// `UR14` at offset `0x338`, resets to `0x0000_0000`, read-write.
    Ur14 = 23,
    /// `UR15` at offset `0x33C`, resets to `0x0000_0000`, read-only.
    Ur15 = 24,
    /// `UR16` at offset `0x340`, resets to `0x0000_0000`, read-only.
    Ur16 = 25,
    /// `UR17` at offset `0x344`, resets to `0x0000_0000`, read-only.
    Ur17 = 26,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 27] = [Self::Pmcr, Self::Exticr1, Self::Exticr2, Self::Exticr3, Self::Exticr4, Self::Cccsr, Self::Ccvr, Self::Cccr, Self::Pwrcr, Self::Pkgr, Self::Ur0, Self::Ur2, Self::Ur3, Self::Ur4, Self::Ur5, Self::Ur6, Self::Ur7, Self::Ur8, Self::Ur9, Self::Ur10, Self::Ur11, Self::Ur12, Self::Ur13, Self::Ur14, Self::Ur15, Self::Ur16, Self::Ur17];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `PMCR`.
pub mod pmcr {
    use super::FieldSpec;
    /// `I2C1FMP`, bit 0.
    pub const I2C1FMP: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `I2C2FMP`, bit 1.
    pub const I2C2FMP: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `I2C3FMP`, bit 2.
    pub const I2C3FMP: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `I2C4FMP`, bit 3.
    pub const I2C4FMP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `PB6FMP`, bit 4.
    pub const PB6FMP: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `PB7FMP`, bit 5.
    pub const PB7FMP: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `PB8FMP`, bit 6.
    pub const PB8FMP: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `PB9FMP`, bit 7.
    pub const PB9FMP: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `BOOSTE`, bit 8.
    pub const BOOSTE: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `BOOSTVDDSEL`, bit 9.
    pub const BOOSTVDDSEL: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `EPIS`, bits 21..=23.
    pub const EPIS: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `PA0SO`, bit 24.
    pub const PA0SO: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `PA1SO`, bit 25.
    pub const PA1SO: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `PC2SO`, bit 26.
    pub const PC2SO: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `PC3SO`, bit 27.
    pub const PC3SO: &FieldSpec = &super::REGISTERS[0].fields[14];
}

/// The fields of `EXTICR1`.
pub mod exticr1 {
    use super::FieldSpec;
    /// `EXTI0`, bits 0..=3.
    pub const EXTI0: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `EXTI1`, bits 4..=7.
    pub const EXTI1: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `EXTI2`, bits 8..=11.
    pub const EXTI2: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `EXTI3`, bits 12..=15.
    pub const EXTI3: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The fields of `EXTICR2`.
pub mod exticr2 {
    use super::FieldSpec;
    /// `EXTI4`, bits 0..=3.
    pub const EXTI4: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `EXTI5`, bits 4..=7.
    pub const EXTI5: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `EXTI6`, bits 8..=11.
    pub const EXTI6: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `EXTI7`, bits 12..=15.
    pub const EXTI7: &FieldSpec = &super::REGISTERS[2].fields[3];
}

/// The fields of `EXTICR3`.
pub mod exticr3 {
    use super::FieldSpec;
    /// `EXTI8`, bits 0..=3.
    pub const EXTI8: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `EXTI9`, bits 4..=7.
    pub const EXTI9: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `EXTI10`, bits 8..=11.
    pub const EXTI10: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `EXTI11`, bits 12..=15.
    pub const EXTI11: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `EXTICR4`.
pub mod exticr4 {
    use super::FieldSpec;
    /// `EXTI12`, bits 0..=3.
    pub const EXTI12: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `EXTI13`, bits 4..=7.
    pub const EXTI13: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `EXTI14`, bits 8..=11.
    pub const EXTI14: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `EXTI15`, bits 12..=15.
    pub const EXTI15: &FieldSpec = &super::REGISTERS[4].fields[3];
}

/// The fields of `CCCSR`.
pub mod cccsr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `CS`, bit 1.
    pub const CS: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `READY`, bit 8.
    pub const READY: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `HSLV`, bit 16.
    pub const HSLV: &FieldSpec = &super::REGISTERS[5].fields[3];
}

/// The fields of `CCVR`.
pub mod ccvr {
    use super::FieldSpec;
    /// `NCV`, bits 0..=3.
    pub const NCV: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `PCV`, bits 4..=7.
    pub const PCV: &FieldSpec = &super::REGISTERS[6].fields[1];
}

/// The fields of `CCCR`.
pub mod cccr {
    use super::FieldSpec;
    /// `NCC`, bits 0..=3.
    pub const NCC: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `PCC`, bits 4..=7.
    pub const PCC: &FieldSpec = &super::REGISTERS[7].fields[1];
}

/// The fields of `PWRCR`.
pub mod pwrcr {
    use super::FieldSpec;
    /// `ODEN`, bits 0..=3.
    pub const ODEN: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `PKGR`.
pub mod pkgr {
    use super::FieldSpec;
    /// `PKG`, bits 0..=3.
    pub const PKG: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `UR0`.
pub mod ur0 {
    use super::FieldSpec;
    /// `BKS`, bit 0.
    pub const BKS: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `RDP`, bits 16..=23.
    pub const RDP: &FieldSpec = &super::REGISTERS[10].fields[1];
}

/// The fields of `UR2`.
pub mod ur2 {
    use super::FieldSpec;
    /// `BORH`, bits 0..=1.
    pub const BORH: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `BOOT_ADD0`, bits 16..=31.
    pub const BOOT_ADD0: &FieldSpec = &super::REGISTERS[11].fields[1];
}

/// The fields of `UR3`.
pub mod ur3 {
    use super::FieldSpec;
    /// `BOOT_ADD1`, bits 16..=31.
    pub const BOOT_ADD1: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `UR4`.
pub mod ur4 {
    use super::FieldSpec;
    /// `MEPAD_1`, bit 16.
    pub const MEPAD_1: &FieldSpec = &super::REGISTERS[13].fields[0];
}

/// The fields of `UR5`.
pub mod ur5 {
    use super::FieldSpec;
    /// `MESAD_1`, bit 0.
    pub const MESAD_1: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `WRPN_1`, bits 16..=23.
    pub const WRPN_1: &FieldSpec = &super::REGISTERS[14].fields[1];
}

/// The fields of `UR6`.
pub mod ur6 {
    use super::FieldSpec;
    /// `PA_BEG_1`, bits 0..=11.
    pub const PA_BEG_1: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `PA_END_1`, bits 16..=27.
    pub const PA_END_1: &FieldSpec = &super::REGISTERS[15].fields[1];
}

/// The fields of `UR7`.
pub mod ur7 {
    use super::FieldSpec;
    /// `SA_BEG_1`, bits 0..=11.
    pub const SA_BEG_1: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `SA_END_1`, bits 16..=27.
    pub const SA_END_1: &FieldSpec = &super::REGISTERS[16].fields[1];
}

/// The fields of `UR8`.
pub mod ur8 {
    use super::FieldSpec;
    /// `MEPAD_2`, bit 0.
    pub const MEPAD_2: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `MESAD_2`, bit 16.
    pub const MESAD_2: &FieldSpec = &super::REGISTERS[17].fields[1];
}

/// The fields of `UR9`.
pub mod ur9 {
    use super::FieldSpec;
    /// `WRPN_2`, bits 0..=7.
    pub const WRPN_2: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `PA_BEG_2`, bits 16..=27.
    pub const PA_BEG_2: &FieldSpec = &super::REGISTERS[18].fields[1];
}

/// The fields of `UR10`.
pub mod ur10 {
    use super::FieldSpec;
    /// `PA_END_2`, bits 0..=11.
    pub const PA_END_2: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `SA_BEG_2`, bits 16..=27.
    pub const SA_BEG_2: &FieldSpec = &super::REGISTERS[19].fields[1];
}

/// The fields of `UR11`.
pub mod ur11 {
    use super::FieldSpec;
    /// `SA_END_2`, bits 0..=11.
    pub const SA_END_2: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `IWDG1M`, bit 16.
    pub const IWDG1M: &FieldSpec = &super::REGISTERS[20].fields[1];
}

/// The fields of `UR12`.
pub mod ur12 {
    use super::FieldSpec;
    /// `SECURE`, bit 16.
    pub const SECURE: &FieldSpec = &super::REGISTERS[21].fields[0];
}

/// The fields of `UR13`.
pub mod ur13 {
    use super::FieldSpec;
    /// `SDRS`, bits 0..=1.
    pub const SDRS: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `D1SBRST`, bit 16.
    pub const D1SBRST: &FieldSpec = &super::REGISTERS[22].fields[1];
}

/// The fields of `UR14`.
pub mod ur14 {
    use super::FieldSpec;
    /// `D1STPRST`, bit 0.
    pub const D1STPRST: &FieldSpec = &super::REGISTERS[23].fields[0];
}

/// The fields of `UR15`.
pub mod ur15 {
    use super::FieldSpec;
    /// `FZIWDGSTB`, bit 16.
    pub const FZIWDGSTB: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The fields of `UR16`.
pub mod ur16 {
    use super::FieldSpec;
    /// `FZIWDGSTP`, bit 0.
    pub const FZIWDGSTP: &FieldSpec = &super::REGISTERS[25].fields[0];
    /// `PKP`, bit 16.
    pub const PKP: &FieldSpec = &super::REGISTERS[25].fields[1];
}

/// The fields of `UR17`.
pub mod ur17 {
    use super::FieldSpec;
    /// `IO_HSLV`, bit 0.
    pub const IO_HSLV: &FieldSpec = &super::REGISTERS[26].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 27] = [
    RegisterSpec { name: "PMCR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "I2C1FMP", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C2FMP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C3FMP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "I2C4FMP", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PB6FMP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PB7FMP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PB8FMP", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PB9FMP", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOSTE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOSTVDDSEL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EPIS", bit: 21, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA0SO", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA1SO", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PC2SO", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PC3SO", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI0", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI1", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI2", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI3", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR2", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI4", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI5", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI6", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI7", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR3", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI8", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI9", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI10", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI11", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "EXTICR4", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXTI12", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI13", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI14", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTI15", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCCSR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "READY", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "HSLV", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCVR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NCV", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCV", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CCCR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NCC", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PCC", bit: 4, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PWRCR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ODEN", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PKGR", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PKG", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR0", offset: 0x300, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKS", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDP", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR2", offset: 0x308, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BORH", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOT_ADD0", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR3", offset: 0x30C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BOOT_ADD1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR4", offset: 0x310, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEPAD_1", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR5", offset: 0x314, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MESAD_1", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WRPN_1", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR6", offset: 0x318, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA_BEG_1", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA_END_1", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR7", offset: 0x31C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SA_BEG_1", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA_END_1", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR8", offset: 0x320, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MEPAD_2", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MESAD_2", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR9", offset: 0x324, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WRPN_2", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PA_BEG_2", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR10", offset: 0x328, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PA_END_2", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SA_BEG_2", bit: 16, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR11", offset: 0x32C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SA_END_2", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IWDG1M", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR12", offset: 0x330, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SECURE", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR13", offset: 0x334, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SDRS", bit: 0, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "D1SBRST", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR14", offset: 0x338, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "D1STPRST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR15", offset: 0x33C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FZIWDGSTB", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR16", offset: 0x340, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FZIWDGSTP", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PKP", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "UR17", offset: 0x344, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IO_HSLV", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];