rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DFSDM` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `DFSDM_CHCFG0R1` at offset `0x0`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg0r1 = 0,
    /// `DFSDM_CHCFG1R1` at offset `0x4`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg1r1 = 1,
    /// `DFSDM_CHCFG2R1` at offset `0x8`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg2r1 = 2,
    /// `DFSDM_CHCFG3R1` at offset `0xC`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg3r1 = 3,
    /// `DFSDM_CHCFG4R1` at offset `0x10`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg4r1 = 4,
    /// `DFSDM_CHCFG5R1` at offset `0x14`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg5r1 = 5,
    /// `DFSDM_CHCFG6R1` at offset `0x18`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg6r1 = 6,
    /// `DFSDM_CHCFG7R1` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg7r1 = 7,
    /// `DFSDM_CHCFG0R2` at offset `0x20`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg0r2 = 8,
    /// `DFSDM_CHCFG1R2` at offset `0x24`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg1r2 = 9,
    /// `DFSDM_CHCFG2R2` at offset `0x28`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg2r2 = 10,
    /// `DFSDM_CHCFG3R2` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg3r2 = 11,
    /// `DFSDM_CHCFG4R2` at offset `0x30`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg4r2 = 12,
    /// `DFSDM_CHCFG5R2` at offset `0x34`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg5r2 = 13,
    /// `DFSDM_CHCFG6R2` at offset `0x38`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg6r2 = 14,
    /// `DFSDM_CHCFG7R2` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    DfsdmChcfg7r2 = 15,
    /// `DFSDM_AWSCD0R` at offset `0x40`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd0r = 16,
    /// `DFSDM_AWSCD1R` at offset `0x44`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd1r = 17,
    /// `DFSDM_AWSCD2R` at offset `0x48`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd2r = 18,
    /// `DFSDM_AWSCD3R` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd3r = 19,
    /// `DFSDM_AWSCD4R` at offset `0x50`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd4r = 20,
    /// `DFSDM_AWSCD5R` at offset `0x54`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd5r = 21,
    /// `DFSDM_AWSCD6R` at offset `0x58`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd6r = 22,
    /// `DFSDM_AWSCD7R` at offset `0x5C`, resets to `0x0000_0000`, read-write.
    DfsdmAwscd7r = 23,
    /// `DFSDM_CHWDAT0R` at offset `0x60`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat0r = 24,
    /// `DFSDM_CHWDAT1R` at offset `0x64`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat1r = 25,
    /// `DFSDM_CHWDAT2R` at offset `0x68`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat2r = 26,
    /// `DFSDM_CHWDAT3R` at offset `0x6C`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat3r = 27,
    /// `DFSDM_CHWDAT4R` at offset `0x70`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat4r = 28,
    /// `DFSDM_CHWDAT5R` at offset `0x74`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat5r = 29,
    /// `DFSDM_CHWDAT6R` at offset `0x78`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat6r = 30,
    /// `DFSDM_CHWDAT7R` at offset `0x7C`, resets to `0x0000_0000`, read-only.
    DfsdmChwdat7r = 31,
    /// `DFSDM_CHDATIN0R` at offset `0x80`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin0r = 32,
    /// `DFSDM_CHDATIN1R` at offset `0x84`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin1r = 33,
    /// `DFSDM_CHDATIN2R` at offset `0x88`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin2r = 34,
    /// `DFSDM_CHDATIN3R` at offset `0x8C`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin3r = 35,
    /// `DFSDM_CHDATIN4R` at offset `0x90`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin4r = 36,
    /// `DFSDM_CHDATIN5R` at offset `0x94`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin5r = 37,
    /// `DFSDM_CHDATIN6R` at offset `0x98`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin6r = 38,
    /// `DFSDM_CHDATIN7R` at offset `0x9C`, resets to `0x0000_0000`, read-write.
    DfsdmChdatin7r = 39,
    /// `DFSDM0_CR1` at offset `0xA0`, resets to `0x0000_0000`, read-write.
    Dfsdm0Cr1 = 40,
    /// `DFSDM1_CR1` at offset `0xA4`, resets to `0x0000_0000`, read-write.
    Dfsdm1Cr1 = 41,
    /// `DFSDM2_CR1` at offset `0xA8`, resets to `0x0000_0000`, read-write.
    Dfsdm2Cr1 = 42,
    /// `DFSDM3_CR1` at offset `0xAC`, resets to `0x0000_0000`, read-write.
    Dfsdm3Cr1 = 43,
    /// `DFSDM0_CR2` at offset `0xB0`, resets to `0x0000_0000`, read-write.
    Dfsdm0Cr2 = 44,
    /// `DFSDM1_CR2` at offset `0xB4`, resets to `0x0000_0000`, read-write.
    Dfsdm1Cr2 = 45,
    /// `DFSDM2_CR2` at offset `0xB8`, resets to `0x0000_0000`, read-write.
    Dfsdm2Cr2 = 46,
    /// `DFSDM3_CR2` at offset `0xBC`, resets to `0x0000_0000`, read-write.
    Dfsdm3Cr2 = 47,
    /// `DFSDM0_ISR` at offset `0xC0`, resets to `0x0000_0000`, read-only.
    Dfsdm0Isr = 48,
    /// `DFSDM1_ISR` at offset `0xC4`, resets to `0x0000_0000`, read-only.
    Dfsdm1Isr = 49,
    /// `DFSDM2_ISR` at offset `0xC8`, resets to `0x0000_0000`, read-only.
    Dfsdm2Isr = 50,
    /// `DFSDM3_ISR` at offset `0xCC`, resets to `0x0000_0000`, read-only.
    Dfsdm3Isr = 51,
    /// `DFSDM0_ICR` at offset `0xD0`, resets to `0x0000_0000`, read-write.
    Dfsdm0Icr = 52,
    /// `DFSDM1_ICR` at offset `0xD4`, resets to `0x0000_0000`, read-write.
    Dfsdm1Icr = 53,
    /// `DFSDM2_ICR` at offset `0xD8`, resets to `0x0000_0000`, read-write.
    Dfsdm2Icr = 54,
    /// `DFSDM3_ICR` at offset `0xDC`, resets to `0x0000_0000`, read-write.
    Dfsdm3Icr = 55,
    /// `DFSDM0_JCHGR` at offset `0xE0`, resets to `0x0000_0000`, read-write.
    Dfsdm0Jchgr = 56,
    /// `DFSDM1_JCHGR` at offset `0xE4`, resets to `0x0000_0000`, read-write.
    Dfsdm1Jchgr = 57,
    /// `DFSDM2_JCHGR` at offset `0xE8`, resets to `0x0000_0000`, read-write.
    Dfsdm2Jchgr = 58,
    /// `DFSDM3_JCHGR` at offset `0xEC`, resets to `0x0000_0000`, read-write.
    Dfsdm3Jchgr = 59,
    /// `DFSDM0_FCR` at offset `0xF0`, resets to `0x0000_0000`, read-write.
    Dfsdm0Fcr = 60,
    /// `DFSDM1_FCR` at offset `0xF4`, resets to `0x0000_0000`, read-write.
    Dfsdm1Fcr = 61,
    /// `DFSDM2_FCR` at offset `0xF8`, resets to `0x0000_0000`, read-write.
    Dfsdm2Fcr = 62,
    /// `DFSDM3_FCR` at offset `0xFC`, resets to `0x0000_0000`, read-write.
    Dfsdm3Fcr = 63,
    /// `DFSDM0_JDATAR` at offset `0x100`, resets to `0x0000_0000`, read-only.
    Dfsdm0Jdatar = 64,
    /// `DFSDM1_JDATAR` at offset `0x104`, resets to `0x0000_0000`, read-only.
    Dfsdm1Jdatar = 65,
    /// `DFSDM2_JDATAR` at offset `0x108`, resets to `0x0000_0000`, read-only.
    Dfsdm2Jdatar = 66,
    /// `DFSDM3_JDATAR` at offset `0x10C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Jdatar = 67,
    /// `DFSDM0_RDATAR` at offset `0x110`, resets to `0x0000_0000`, read-only.
    Dfsdm0Rdatar = 68,
    /// `DFSDM1_RDATAR` at offset `0x114`, resets to `0x0000_0000`, read-only.
    Dfsdm1Rdatar = 69,
    /// `DFSDM2_RDATAR` at offset `0x118`, resets to `0x0000_0000`, read-only.
    Dfsdm2Rdatar = 70,
    /// `DFSDM3_RDATAR` at offset `0x11C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Rdatar = 71,
    /// `DFSDM0_AWHTR` at offset `0x120`, resets to `0x0000_0000`, read-write.
    Dfsdm0Awhtr = 72,
    /// `DFSDM1_AWHTR` at offset `0x124`, resets to `0x0000_0000`, read-write.
    Dfsdm1Awhtr = 73,
    /// `DFSDM2_AWHTR` at offset `0x128`, resets to `0x0000_0000`, read-write.
    Dfsdm2Awhtr = 74,
    /// `DFSDM3_AWHTR` at offset `0x12C`, resets to `0x0000_0000`, read-write.
    Dfsdm3Awhtr = 75,
    /// `DFSDM0_AWLTR` at offset `0x130`, resets to `0x0000_0000`, read-write.
    Dfsdm0Awltr = 76,
    /// `DFSDM1_AWLTR` at offset `0x134`, resets to `0x0000_0000`, read-write.
    Dfsdm1Awltr = 77,
    /// `DFSDM2_AWLTR` at offset `0x138`, resets to `0x0000_0000`, read-write.
    Dfsdm2Awltr = 78,
    /// `DFSDM3_AWLTR` at offset `0x13C`, resets to `0x0000_0000`, read-write.
    Dfsdm3Awltr = 79,
    /// `DFSDM0_AWSR` at offset `0x140`, resets to `0x0000_0000`, read-only.
    Dfsdm0Awsr = 80,
    /// `DFSDM1_AWSR` at offset `0x144`, resets to `0x0000_0000`, read-only.
    Dfsdm1Awsr = 81,
    /// `DFSDM2_AWSR` at offset `0x148`, resets to `0x0000_0000`, read-only.
    Dfsdm2Awsr = 82,
    /// `DFSDM3_AWSR` at offset `0x14C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Awsr = 83,
    /// `DFSDM0_AWCFR` at offset `0x150`, resets to `0x0000_0000`, read-write.
    Dfsdm0Awcfr = 84,
    /// `DFSDM1_AWCFR` at offset `0x154`, resets to `0x0000_0000`, read-write.
    Dfsdm1Awcfr = 85,
    /// `DFSDM2_AWCFR` at offset `0x158`, resets to `0x0000_0000`, read-write.
    Dfsdm2Awcfr = 86,
    /// `DFSDM3_AWCFR` at offset `0x15C`, resets to `0x0000_0000`, read-write.
    Dfsdm3Awcfr = 87,
    /// `DFSDM0_EXMAX` at offset `0x160`, resets to `0x0000_0000`, read-only.
    Dfsdm0Exmax = 88,
    /// `DFSDM1_EXMAX` at offset `0x164`, resets to `0x0000_0000`, read-only.
    Dfsdm1Exmax = 89,
    /// `DFSDM2_EXMAX` at offset `0x168`, resets to `0x0000_0000`, read-only.
    Dfsdm2Exmax = 90,
    /// `DFSDM3_EXMAX` at offset `0x16C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Exmax = 91,
    /// `DFSDM0_EXMIN` at offset `0x170`, resets to `0x0000_0000`, read-only.
    Dfsdm0Exmin = 92,
    /// `DFSDM1_EXMIN` at offset `0x174`, resets to `0x0000_0000`, read-only.
    Dfsdm1Exmin = 93,
    /// `DFSDM2_EXMIN` at offset `0x178`, resets to `0x0000_0000`, read-only.
    Dfsdm2Exmin = 94,
    /// `DFSDM3_EXMIN` at offset `0x17C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Exmin = 95,
    /// `DFSDM0_CNVTIMR` at offset `0x180`, resets to `0x0000_0000`, read-only.
    Dfsdm0Cnvtimr = 96,
    /// `DFSDM1_CNVTIMR` at offset `0x184`, resets to `0x0000_0000`, read-only.
    Dfsdm1Cnvtimr = 97,
    /// `DFSDM2_CNVTIMR` at offset `0x188`, resets to `0x0000_0000`, read-only.
    Dfsdm2Cnvtimr = 98,
    /// `DFSDM3_CNVTIMR` at offset `0x18C`, resets to `0x0000_0000`, read-only.
    Dfsdm3Cnvtimr = 99,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 100] = [Self::DfsdmChcfg0r1, Self::DfsdmChcfg1r1, Self::DfsdmChcfg2r1, Self::DfsdmChcfg3r1, Self::DfsdmChcfg4r1, Self::DfsdmChcfg5r1, Self::DfsdmChcfg6r1, Self::DfsdmChcfg7r1, Self::DfsdmChcfg0r2, Self::DfsdmChcfg1r2, Self::DfsdmChcfg2r2, Self::DfsdmChcfg3r2, Self::DfsdmChcfg4r2, Self::DfsdmChcfg5r2, Self::DfsdmChcfg6r2, Self::DfsdmChcfg7r2, Self::DfsdmAwscd0r, Self::DfsdmAwscd1r, Self::DfsdmAwscd2r, Self::DfsdmAwscd3r, Self::DfsdmAwscd4r, Self::DfsdmAwscd5r, Self::DfsdmAwscd6r, Self::DfsdmAwscd7r, Self::DfsdmChwdat0r, Self::DfsdmChwdat1r, Self::DfsdmChwdat2r, Self::DfsdmChwdat3r, Self::DfsdmChwdat4r, Self::DfsdmChwdat5r, Self::DfsdmChwdat6r, Self::DfsdmChwdat7r, Self::DfsdmChdatin0r, Self::DfsdmChdatin1r, Self::DfsdmChdatin2r, Self::DfsdmChdatin3r, Self::DfsdmChdatin4r, Self::DfsdmChdatin5r, Self::DfsdmChdatin6r, Self::DfsdmChdatin7r, Self::Dfsdm0Cr1, Self::Dfsdm1Cr1, Self::Dfsdm2Cr1, Self::Dfsdm3Cr1, Self::Dfsdm0Cr2, Self::Dfsdm1Cr2, Self::Dfsdm2Cr2, Self::Dfsdm3Cr2, Self::Dfsdm0Isr, Self::Dfsdm1Isr, Self::Dfsdm2Isr, Self::Dfsdm3Isr, Self::Dfsdm0Icr, Self::Dfsdm1Icr, Self::Dfsdm2Icr, Self::Dfsdm3Icr, Self::Dfsdm0Jchgr, Self::Dfsdm1Jchgr, Self::Dfsdm2Jchgr, Self::Dfsdm3Jchgr, Self::Dfsdm0Fcr, Self::Dfsdm1Fcr, Self::Dfsdm2Fcr, Self::Dfsdm3Fcr, Self::Dfsdm0Jdatar, Self::Dfsdm1Jdatar, Self::Dfsdm2Jdatar, Self::Dfsdm3Jdatar, Self::Dfsdm0Rdatar, Self::Dfsdm1Rdatar, Self::Dfsdm2Rdatar, Self::Dfsdm3Rdatar, Self::Dfsdm0Awhtr, Self::Dfsdm1Awhtr, Self::Dfsdm2Awhtr, Self::Dfsdm3Awhtr, Self::Dfsdm0Awltr, Self::Dfsdm1Awltr, Self::Dfsdm2Awltr, Self::Dfsdm3Awltr, Self::Dfsdm0Awsr, Self::Dfsdm1Awsr, Self::Dfsdm2Awsr, Self::Dfsdm3Awsr, Self::Dfsdm0Awcfr, Self::Dfsdm1Awcfr, Self::Dfsdm2Awcfr, Self::Dfsdm3Awcfr, Self::Dfsdm0Exmax, Self::Dfsdm1Exmax, Self::Dfsdm2Exmax, Self::Dfsdm3Exmax, Self::Dfsdm0Exmin, Self::Dfsdm1Exmin, Self::Dfsdm2Exmin, Self::Dfsdm3Exmin, Self::Dfsdm0Cnvtimr, Self::Dfsdm1Cnvtimr, Self::Dfsdm2Cnvtimr, Self::Dfsdm3Cnvtimr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `DFSDM_CHCFG0R1`.
pub mod dfsdm_chcfg0r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[0].fields[10];
}

/// The fields of `DFSDM_CHCFG1R1`.
pub mod dfsdm_chcfg1r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[1].fields[10];
}

/// The fields of `DFSDM_CHCFG2R1`.
pub mod dfsdm_chcfg2r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[2].fields[10];
}

/// The fields of `DFSDM_CHCFG3R1`.
pub mod dfsdm_chcfg3r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[3].fields[10];
}

/// The fields of `DFSDM_CHCFG4R1`.
pub mod dfsdm_chcfg4r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[4].fields[10];
}

/// The fields of `DFSDM_CHCFG5R1`.
pub mod dfsdm_chcfg5r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[5].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[5].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[5].fields[10];
}

/// The fields of `DFSDM_CHCFG6R1`.
pub mod dfsdm_chcfg6r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[6].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[6].fields[10];
}

/// The fields of `DFSDM_CHCFG7R1`.
pub mod dfsdm_chcfg7r1 {
    use super::FieldSpec;
    /// `SITP`, bits 0..=1.
    pub const SITP: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `SPICKSEL`, bits 2..=3.
    pub const SPICKSEL: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `SCDEN`, bit 5.
    pub const SCDEN: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `CKABEN`, bit 6.
    pub const CKABEN: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `CHEN`, bit 7.
    pub const CHEN: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CHINSEL`, bit 8.
    pub const CHINSEL: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `DATMPX`, bits 12..=13.
    pub const DATMPX: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `DATPACK`, bits 14..=15.
    pub const DATPACK: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `CKOUTDIV`, bits 16..=23.
    pub const CKOUTDIV: &FieldSpec = &super::REGISTERS[7].fields[8];
    /// `CKOUTSRC`, bit 30.
    pub const CKOUTSRC: &FieldSpec = &super::REGISTERS[7].fields[9];
    /// `DFSDMEN`, bit 31.
    pub const DFSDMEN: &FieldSpec = &super::REGISTERS[7].fields[10];
}

/// The fields of `DFSDM_CHCFG0R2`.
pub mod dfsdm_chcfg0r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `DFSDM_CHCFG1R2`.
pub mod dfsdm_chcfg1r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[9].fields[1];
}

/// The fields of `DFSDM_CHCFG2R2`.
pub mod dfsdm_chcfg2r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[10].fields[1];
}

/// The fields of `DFSDM_CHCFG3R2`.
pub mod dfsdm_chcfg3r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[11].fields[1];
}

/// The fields of `DFSDM_CHCFG4R2`.
pub mod dfsdm_chcfg4r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[12].fields[1];
}

/// The fields of `DFSDM_CHCFG5R2`.
pub mod dfsdm_chcfg5r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[13].fields[1];
}

/// The fields of `DFSDM_CHCFG6R2`.
pub mod dfsdm_chcfg6r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[14].fields[1];
}

/// The fields of `DFSDM_CHCFG7R2`.
pub mod dfsdm_chcfg7r2 {
    use super::FieldSpec;
    /// `DTRBS`, bits 3..=7.
    pub const DTRBS: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `OFFSET`, bits 8..=31.
    pub const OFFSET: &FieldSpec = &super::REGISTERS[15].fields[1];
}

/// The fields of `DFSDM_AWSCD0R`.
pub mod dfsdm_awscd0r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[16].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[16].fields[3];
}

/// The fields of `DFSDM_AWSCD1R`.
pub mod dfsdm_awscd1r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[17].fields[3];
}

/// The fields of `DFSDM_AWSCD2R`.
pub mod dfsdm_awscd2r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[18].fields[3];
}

/// The fields of `DFSDM_AWSCD3R`.
pub mod dfsdm_awscd3r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[19].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[19].fields[3];
}

/// The fields of `DFSDM_AWSCD4R`.
pub mod dfsdm_awscd4r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[20].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[20].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[20].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[20].fields[3];
}

/// The fields of `DFSDM_AWSCD5R`.
pub mod dfsdm_awscd5r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[21].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[21].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[21].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[21].fields[3];
}

/// The fields of `DFSDM_AWSCD6R`.
pub mod dfsdm_awscd6r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[22].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[22].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[22].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[22].fields[3];
}

/// The fields of `DFSDM_AWSCD7R`.
pub mod dfsdm_awscd7r {
    use super::FieldSpec;
    /// `SCDT`, bits 0..=7.
    pub const SCDT: &FieldSpec = &super::REGISTERS[23].fields[0];
    /// `BKSCD`, bits 12..=15.
    pub const BKSCD: &FieldSpec = &super::REGISTERS[23].fields[1];
    /// `AWFOSR`, bits 16..=20.
    pub const AWFOSR: &FieldSpec = &super::REGISTERS[23].fields[2];
    /// `AWFORD`, bits 22..=23.
    pub const AWFORD: &FieldSpec = &super::REGISTERS[23].fields[3];
}

/// The fields of `DFSDM_CHWDAT0R`.
pub mod dfsdm_chwdat0r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The fields of `DFSDM_CHWDAT1R`.
pub mod dfsdm_chwdat1r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[25].fields[0];
}

/// The fields of `DFSDM_CHWDAT2R`.
pub mod dfsdm_chwdat2r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[26].fields[0];
}

/// The fields of `DFSDM_CHWDAT3R`.
pub mod dfsdm_chwdat3r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[27].fields[0];
}

/// The fields of `DFSDM_CHWDAT4R`.
pub mod dfsdm_chwdat4r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[28].fields[0];
}

/// The fields of `DFSDM_CHWDAT5R`.
pub mod dfsdm_chwdat5r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[29].fields[0];
}

/// The fields of `DFSDM_CHWDAT6R`.
pub mod dfsdm_chwdat6r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[30].fields[0];
}

/// The fields of `DFSDM_CHWDAT7R`.
pub mod dfsdm_chwdat7r {
    use super::FieldSpec;
    /// `WDATA`, bits 0..=15.
    pub const WDATA: &FieldSpec = &super::REGISTERS[31].fields[0];
}

/// The fields of `DFSDM_CHDATIN0R`.
pub mod dfsdm_chdatin0r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[32].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[32].fields[1];
}

/// The fields of `DFSDM_CHDATIN1R`.
pub mod dfsdm_chdatin1r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[33].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[33].fields[1];
}

/// The fields of `DFSDM_CHDATIN2R`.
pub mod dfsdm_chdatin2r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[34].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[34].fields[1];
}

/// The fields of `DFSDM_CHDATIN3R`.
pub mod dfsdm_chdatin3r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[35].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[35].fields[1];
}

/// The fields of `DFSDM_CHDATIN4R`.
pub mod dfsdm_chdatin4r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[36].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[36].fields[1];
}

/// The fields of `DFSDM_CHDATIN5R`.
pub mod dfsdm_chdatin5r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[37].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[37].fields[1];
}

/// The fields of `DFSDM_CHDATIN6R`.
pub mod dfsdm_chdatin6r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[38].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[38].fields[1];
}

/// The fields of `DFSDM_CHDATIN7R`.
pub mod dfsdm_chdatin7r {
    use super::FieldSpec;
    /// `INDAT0`, bits 0..=15.
    pub const INDAT0: &FieldSpec = &super::REGISTERS[39].fields[0];
    /// `INDAT1`, bits 16..=31.
    pub const INDAT1: &FieldSpec = &super::REGISTERS[39].fields[1];
}

/// The fields of `DFSDM0_CR1`.
pub mod dfsdm0_cr1 {
    use super::FieldSpec;
    /// `DFEN`, bit 0.
    pub const DFEN: &FieldSpec = &super::REGISTERS[40].fields[0];
    /// `JSWSTART`, bit 1.
    pub const JSWSTART: &FieldSpec = &super::REGISTERS[40].fields[1];
    /// `JSYNC`, bit 3.
    pub const JSYNC: &FieldSpec = &super::REGISTERS[40].fields[2];
    /// `JSCAN`, bit 4.
    pub const JSCAN: &FieldSpec = &super::REGISTERS[40].fields[3];
    /// `JDMAEN`, bit 5.
    pub const JDMAEN: &FieldSpec = &super::REGISTERS[40].fields[4];
    /// `JEXTSEL`, bits 8..=12.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[40].fields[5];
    /// `JEXTEN`, bits 13..=14.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[40].fields[6];
    /// `RSWSTART`, bit 17.
    pub const RSWSTART: &FieldSpec = &super::REGISTERS[40].fields[7];
    /// `RCONT`, bit 18.
    pub const RCONT: &FieldSpec = &super::REGISTERS[40].fields[8];
    /// `RSYNC`, bit 19.
    pub const RSYNC: &FieldSpec = &super::REGISTERS[40].fields[9];
    /// `RDMAEN`, bit 21.
    pub const RDMAEN: &FieldSpec = &super::REGISTERS[40].fields[10];
    /// `RCH`, bits 24..=26.
    pub const RCH: &FieldSpec = &super::REGISTERS[40].fields[11];
    /// `FAST`, bit 29.
    pub const FAST: &FieldSpec = &super::REGISTERS[40].fields[12];
    /// `AWFSEL`, bit 30.
    pub const AWFSEL: &FieldSpec = &super::REGISTERS[40].fields[13];
}

/// The fields of `DFSDM1_CR1`.
pub mod dfsdm1_cr1 {
    use super::FieldSpec;
    /// `DFEN`, bit 0.
    pub const DFEN: &FieldSpec = &super::REGISTERS[41].fields[0];
    /// `JSWSTART`, bit 1.
    pub const JSWSTART: &FieldSpec = &super::REGISTERS[41].fields[1];
    /// `JSYNC`, bit 3.
    pub const JSYNC: &FieldSpec = &super::REGISTERS[41].fields[2];
    /// `JSCAN`, bit 4.
    pub const JSCAN: &FieldSpec = &super::REGISTERS[41].fields[3];
    /// `JDMAEN`, bit 5.
    pub const JDMAEN: &FieldSpec = &super::REGISTERS[41].fields[4];
    /// `JEXTSEL`, bits 8..=12.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[41].fields[5];
    /// `JEXTEN`, bits 13..=14.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[41].fields[6];
    /// `RSWSTART`, bit 17.
    pub const RSWSTART: &FieldSpec = &super::REGISTERS[41].fields[7];
    /// `RCONT`, bit 18.
    pub const RCONT: &FieldSpec = &super::REGISTERS[41].fields[8];
    /// `RSYNC`, bit 19.
    pub const RSYNC: &FieldSpec = &super::REGISTERS[41].fields[9];
    /// `RDMAEN`, bit 21.
    pub const RDMAEN: &FieldSpec = &super::REGISTERS[41].fields[10];
    /// `RCH`, bits 24..=26.
    pub const RCH: &FieldSpec = &super::REGISTERS[41].fields[11];
    /// `FAST`, bit 29.
    pub const FAST: &FieldSpec = &super::REGISTERS[41].fields[12];
    /// `AWFSEL`, bit 30.
    pub const AWFSEL: &FieldSpec = &super::REGISTERS[41].fields[13];
}

/// The fields of `DFSDM2_CR1`.
pub mod dfsdm2_cr1 {
    use super::FieldSpec;
    /// `DFEN`, bit 0.
    pub const DFEN: &FieldSpec = &super::REGISTERS[42].fields[0];
    /// `JSWSTART`, bit 1.
    pub const JSWSTART: &FieldSpec = &super::REGISTERS[42].fields[1];
    /// `JSYNC`, bit 3.
    pub const JSYNC: &FieldSpec = &super::REGISTERS[42].fields[2];
    /// `JSCAN`, bit 4.
    pub const JSCAN: &FieldSpec = &super::REGISTERS[42].fields[3];
    /// `JDMAEN`, bit 5.
    pub const JDMAEN: &FieldSpec = &super::REGISTERS[42].fields[4];
    /// `JEXTSEL`, bits 8..=12.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[42].fields[5];
    /// `JEXTEN`, bits 13..=14.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[42].fields[6];
    /// `RSWSTART`, bit 17.
    pub const RSWSTART: &FieldSpec = &super::REGISTERS[42].fields[7];
    /// `RCONT`, bit 18.
    pub const RCONT: &FieldSpec = &super::REGISTERS[42].fields[8];
    /// `RSYNC`, bit 19.
    pub const RSYNC: &FieldSpec = &super::REGISTERS[42].fields[9];
    /// `RDMAEN`, bit 21.
    pub const RDMAEN: &FieldSpec = &super::REGISTERS[42].fields[10];
    /// `RCH`, bits 24..=26.
    pub const RCH: &FieldSpec = &super::REGISTERS[42].fields[11];
    /// `FAST`, bit 29.
    pub const FAST: &FieldSpec = &super::REGISTERS[42].fields[12];
    /// `AWFSEL`, bit 30.
    pub const AWFSEL: &FieldSpec = &super::REGISTERS[42].fields[13];
}

/// The fields of `DFSDM3_CR1`.
pub mod dfsdm3_cr1 {
    use super::FieldSpec;
    /// `DFEN`, bit 0.
    pub const DFEN: &FieldSpec = &super::REGISTERS[43].fields[0];
    /// `JSWSTART`, bit 1.
    pub const JSWSTART: &FieldSpec = &super::REGISTERS[43].fields[1];
    /// `JSYNC`, bit 3.
    pub const JSYNC: &FieldSpec = &super::REGISTERS[43].fields[2];
    /// `JSCAN`, bit 4.
    pub const JSCAN: &FieldSpec = &super::REGISTERS[43].fields[3];
    /// `JDMAEN`, bit 5.
    pub const JDMAEN: &FieldSpec = &super::REGISTERS[43].fields[4];
    /// `JEXTSEL`, bits 8..=12.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[43].fields[5];
    /// `JEXTEN`, bits 13..=14.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[43].fields[6];
    /// `RSWSTART`, bit 17.
    pub const RSWSTART: &FieldSpec = &super::REGISTERS[43].fields[7];
    /// `RCONT`, bit 18.
    pub const RCONT: &FieldSpec = &super::REGISTERS[43].fields[8];
    /// `RSYNC`, bit 19.
    pub const RSYNC: &FieldSpec = &super::REGISTERS[43].fields[9];
    /// `RDMAEN`, bit 21.
    pub const RDMAEN: &FieldSpec = &super::REGISTERS[43].fields[10];
    /// `RCH`, bits 24..=26.
    pub const RCH: &FieldSpec = &super::REGISTERS[43].fields[11];
    /// `FAST`, bit 29.
    pub const FAST: &FieldSpec = &super::REGISTERS[43].fields[12];
    /// `AWFSEL`, bit 30.
    pub const AWFSEL: &FieldSpec = &super::REGISTERS[43].fields[13];
}

/// The fields of `DFSDM0_CR2`.
pub mod dfsdm0_cr2 {
    use super::FieldSpec;
    /// `JEOCIE`, bit 0.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[44].fields[0];
    /// `REOCIE`, bit 1.
    pub const REOCIE: &FieldSpec = &super::REGISTERS[44].fields[1];
    /// `JOVRIE`, bit 2.
    pub const JOVRIE: &FieldSpec = &super::REGISTERS[44].fields[2];
    /// `ROVRIE`, bit 3.
    pub const ROVRIE: &FieldSpec = &super::REGISTERS[44].fields[3];
    /// `AWDIE`, bit 4.
    pub const AWDIE: &FieldSpec = &super::REGISTERS[44].fields[4];
    /// `SCDIE`, bit 5.
    pub const SCDIE: &FieldSpec = &super::REGISTERS[44].fields[5];
    /// `CKABIE`, bit 6.
    pub const CKABIE: &FieldSpec = &super::REGISTERS[44].fields[6];
    /// `EXCH`, bits 8..=15.
    pub const EXCH: &FieldSpec = &super::REGISTERS[44].fields[7];
    /// `AWDCH`, bits 16..=23.
    pub const AWDCH: &FieldSpec = &super::REGISTERS[44].fields[8];
}

/// The fields of `DFSDM1_CR2`.
pub mod dfsdm1_cr2 {
    use super::FieldSpec;
    /// `JEOCIE`, bit 0.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[45].fields[0];
    /// `REOCIE`, bit 1.
    pub const REOCIE: &FieldSpec = &super::REGISTERS[45].fields[1];
    /// `JOVRIE`, bit 2.
    pub const JOVRIE: &FieldSpec = &super::REGISTERS[45].fields[2];
    /// `ROVRIE`, bit 3.
    pub const ROVRIE: &FieldSpec = &super::REGISTERS[45].fields[3];
    /// `AWDIE`, bit 4.
    pub const AWDIE: &FieldSpec = &super::REGISTERS[45].fields[4];
    /// `SCDIE`, bit 5.
    pub const SCDIE: &FieldSpec = &super::REGISTERS[45].fields[5];
    /// `CKABIE`, bit 6.
    pub const CKABIE: &FieldSpec = &super::REGISTERS[45].fields[6];
    /// `EXCH`, bits 8..=15.
    pub const EXCH: &FieldSpec = &super::REGISTERS[45].fields[7];
    /// `AWDCH`, bits 16..=23.
    pub const AWDCH: &FieldSpec = &super::REGISTERS[45].fields[8];
}

/// The fields of `DFSDM2_CR2`.
pub mod dfsdm2_cr2 {
    use super::FieldSpec;
    /// `JEOCIE`, bit 0.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[46].fields[0];
    /// `REOCIE`, bit 1.
    pub const REOCIE: &FieldSpec = &super::REGISTERS[46].fields[1];
    /// `JOVRIE`, bit 2.
    pub const JOVRIE: &FieldSpec = &super::REGISTERS[46].fields[2];
    /// `ROVRIE`, bit 3.
    pub const ROVRIE: &FieldSpec = &super::REGISTERS[46].fields[3];
    /// `AWDIE`, bit 4.
    pub const AWDIE: &FieldSpec = &super::REGISTERS[46].fields[4];
    /// `SCDIE`, bit 5.
    pub const SCDIE: &FieldSpec = &super::REGISTERS[46].fields[5];
    /// `CKABIE`, bit 6.
    pub const CKABIE: &FieldSpec = &super::REGISTERS[46].fields[6];
    /// `EXCH`, bits 8..=15.
    pub const EXCH: &FieldSpec = &super::REGISTERS[46].fields[7];
    /// `AWDCH`, bits 16..=23.
    pub const AWDCH: &FieldSpec = &super::REGISTERS[46].fields[8];
}

/// The fields of `DFSDM3_CR2`.
pub mod dfsdm3_cr2 {
    use super::FieldSpec;
    /// `JEOCIE`, bit 0.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[47].fields[0];
    /// `REOCIE`, bit 1.
    pub const REOCIE: &FieldSpec = &super::REGISTERS[47].fields[1];
    /// `JOVRIE`, bit 2.
    pub const JOVRIE: &FieldSpec = &super::REGISTERS[47].fields[2];
    /// `ROVRIE`, bit 3.
    pub const ROVRIE: &FieldSpec = &super::REGISTERS[47].fields[3];
    /// `AWDIE`, bit 4.
    pub const AWDIE: &FieldSpec = &super::REGISTERS[47].fields[4];
    /// `SCDIE`, bit 5.
    pub const SCDIE: &FieldSpec = &super::REGISTERS[47].fields[5];
    /// `CKABIE`, bit 6.
    pub const CKABIE: &FieldSpec = &super::REGISTERS[47].fields[6];
    /// `EXCH`, bits 8..=15.
    pub const EXCH: &FieldSpec = &super::REGISTERS[47].fields[7];
    /// `AWDCH`, bits 16..=23.
    pub const AWDCH: &FieldSpec = &super::REGISTERS[47].fields[8];
}

/// The fields of `DFSDM0_ISR`.
pub mod dfsdm0_isr {
    use super::FieldSpec;
    /// `JEOCF`, bit 0.
    pub const JEOCF: &FieldSpec = &super::REGISTERS[48].fields[0];
    /// `REOCF`, bit 1.
    pub const REOCF: &FieldSpec = &super::REGISTERS[48].fields[1];
    /// `JOVRF`, bit 2.
    pub const JOVRF: &FieldSpec = &super::REGISTERS[48].fields[2];
    /// `ROVRF`, bit 3.
    pub const ROVRF: &FieldSpec = &super::REGISTERS[48].fields[3];
    /// `AWDF`, bit 4.
    pub const AWDF: &FieldSpec = &super::REGISTERS[48].fields[4];
    /// `JCIP`, bit 13.
    pub const JCIP: &FieldSpec = &super::REGISTERS[48].fields[5];
    /// `RCIP`, bit 14.
    pub const RCIP: &FieldSpec = &super::REGISTERS[48].fields[6];
    /// `CKABF`, bits 16..=23.
    pub const CKABF: &FieldSpec = &super::REGISTERS[48].fields[7];
    /// `SCDF`, bits 24..=31.
    pub const SCDF: &FieldSpec = &super::REGISTERS[48].fields[8];
}

/// The fields of `DFSDM1_ISR`.
pub mod dfsdm1_isr {
    use super::FieldSpec;
    /// `JEOCF`, bit 0.
    pub const JEOCF: &FieldSpec = &super::REGISTERS[49].fields[0];
    /// `REOCF`, bit 1.
    pub const REOCF: &FieldSpec = &super::REGISTERS[49].fields[1];
    /// `JOVRF`, bit 2.
    pub const JOVRF: &FieldSpec = &super::REGISTERS[49].fields[2];
    /// `ROVRF`, bit 3.
    pub const ROVRF: &FieldSpec = &super::REGISTERS[49].fields[3];
    /// `AWDF`, bit 4.
    pub const AWDF: &FieldSpec = &super::REGISTERS[49].fields[4];
    /// `JCIP`, bit 13.
    pub const JCIP: &FieldSpec = &super::REGISTERS[49].fields[5];
    /// `RCIP`, bit 14.
    pub const RCIP: &FieldSpec = &super::REGISTERS[49].fields[6];
    /// `CKABF`, bits 16..=23.
    pub const CKABF: &FieldSpec = &super::REGISTERS[49].fields[7];
    /// `SCDF`, bits 24..=31.
    pub const SCDF: &FieldSpec = &super::REGISTERS[49].fields[8];
}

/// The fields of `DFSDM2_ISR`.
pub mod dfsdm2_isr {
    use super::FieldSpec;
    /// `JEOCF`, bit 0.
    pub const JEOCF: &FieldSpec = &super::REGISTERS[50].fields[0];
    /// `REOCF`, bit 1.
    pub const REOCF: &FieldSpec = &super::REGISTERS[50].fields[1];
    /// `JOVRF`, bit 2.
    pub const JOVRF: &FieldSpec = &super::REGISTERS[50].fields[2];
    /// `ROVRF`, bit 3.
    pub const ROVRF: &FieldSpec = &super::REGISTERS[50].fields[3];
    /// `AWDF`, bit 4.
    pub const AWDF: &FieldSpec = &super::REGISTERS[50].fields[4];
    /// `JCIP`, bit 13.
    pub const JCIP: &FieldSpec = &super::REGISTERS[50].fields[5];
    /// `RCIP`, bit 14.
    pub const RCIP: &FieldSpec = &super::REGISTERS[50].fields[6];
    /// `CKABF`, bits 16..=23.
    pub const CKABF: &FieldSpec = &super::REGISTERS[50].fields[7];
    /// `SCDF`, bits 24..=31.
    pub const SCDF: &FieldSpec = &super::REGISTERS[50].fields[8];
}

/// The fields of `DFSDM3_ISR`.
pub mod dfsdm3_isr {
    use super::FieldSpec;
    /// `JEOCF`, bit 0.
    pub const JEOCF: &FieldSpec = &super::REGISTERS[51].fields[0];
    /// `REOCF`, bit 1.
    pub const REOCF: &FieldSpec = &super::REGISTERS[51].fields[1];
    /// `JOVRF`, bit 2.
    pub const JOVRF: &FieldSpec = &super::REGISTERS[51].fields[2];
    /// `ROVRF`, bit 3.
    pub const ROVRF: &FieldSpec = &super::REGISTERS[51].fields[3];
    /// `AWDF`, bit 4.
    pub const AWDF: &FieldSpec = &super::REGISTERS[51].fields[4];
    /// `JCIP`, bit 13.
    pub const JCIP: &FieldSpec = &super::REGISTERS[51].fields[5];
    /// `RCIP`, bit 14.
    pub const RCIP: &FieldSpec = &super::REGISTERS[51].fields[6];
    /// `CKABF`, bits 16..=23.
    pub const CKABF: &FieldSpec = &super::REGISTERS[51].fields[7];
    /// `SCDF`, bits 24..=31.
    pub const SCDF: &FieldSpec = &super::REGISTERS[51].fields[8];
}

/// The fields of `DFSDM0_ICR`.
pub mod dfsdm0_icr {
    use super::FieldSpec;
    /// `CLRJOVRF`, bit 2.
    pub const CLRJOVRF: &FieldSpec = &super::REGISTERS[52].fields[0];
    /// `CLRROVRF`, bit 3.
    pub const CLRROVRF: &FieldSpec = &super::REGISTERS[52].fields[1];
    /// `CLRCKABF`, bits 16..=23.
    pub const CLRCKABF: &FieldSpec = &super::REGISTERS[52].fields[2];
    /// `CLRSCDF`, bits 24..=31.
    pub const CLRSCDF: &FieldSpec = &super::REGISTERS[52].fields[3];
}

/// The fields of `DFSDM1_ICR`.
pub mod dfsdm1_icr {
    use super::FieldSpec;
    /// `CLRJOVRF`, bit 2.
    pub const CLRJOVRF: &FieldSpec = &super::REGISTERS[53].fields[0];
    /// `CLRROVRF`, bit 3.
    pub const CLRROVRF: &FieldSpec = &super::REGISTERS[53].fields[1];
    /// `CLRCKABF`, bits 16..=23.
    pub const CLRCKABF: &FieldSpec = &super::REGISTERS[53].fields[2];
    /// `CLRSCDF`, bits 24..=31.
    pub const CLRSCDF: &FieldSpec = &super::REGISTERS[53].fields[3];
}

/// The fields of `DFSDM2_ICR`.
pub mod dfsdm2_icr {
    use super::FieldSpec;
    /// `CLRJOVRF`, bit 2.
    pub const CLRJOVRF: &FieldSpec = &super::REGISTERS[54].fields[0];
    /// `CLRROVRF`, bit 3.
    pub const CLRROVRF: &FieldSpec = &super::REGISTERS[54].fields[1];
    /// `CLRCKABF`, bits 16..=23.
    pub const CLRCKABF: &FieldSpec = &super::REGISTERS[54].fields[2];
    /// `CLRSCDF`, bits 24..=31.
    pub const CLRSCDF: &FieldSpec = &super::REGISTERS[54].fields[3];
}

/// The fields of `DFSDM3_ICR`.
pub mod dfsdm3_icr {
    use super::FieldSpec;
    /// `CLRJOVRF`, bit 2.
    pub const CLRJOVRF: &FieldSpec = &super::REGISTERS[55].fields[0];
    /// `CLRROVRF`, bit 3.
    pub const CLRROVRF: &FieldSpec = &super::REGISTERS[55].fields[1];
    /// `CLRCKABF`, bits 16..=23.
    pub const CLRCKABF: &FieldSpec = &super::REGISTERS[55].fields[2];
    /// `CLRSCDF`, bits 24..=31.
    pub const CLRSCDF: &FieldSpec = &super::REGISTERS[55].fields[3];
}

/// The fields of `DFSDM0_JCHGR`.
pub mod dfsdm0_jchgr {
    use super::FieldSpec;
    /// `JCHG`, bits 0..=7.
    pub const JCHG: &FieldSpec = &super::REGISTERS[56].fields[0];
}

/// The fields of `DFSDM1_JCHGR`.
pub mod dfsdm1_jchgr {
    use super::FieldSpec;
    /// `JCHG`, bits 0..=7.
    pub const JCHG: &FieldSpec = &super::REGISTERS[57].fields[0];
}

/// The fields of `DFSDM2_JCHGR`.
pub mod dfsdm2_jchgr {
    use super::FieldSpec;
    /// `JCHG`, bits 0..=7.
    pub const JCHG: &FieldSpec = &super::REGISTERS[58].fields[0];
}

/// The fields of `DFSDM3_JCHGR`.
pub mod dfsdm3_jchgr {
    use super::FieldSpec;
    /// `JCHG`, bits 0..=7.
    pub const JCHG: &FieldSpec = &super::REGISTERS[59].fields[0];
}

/// The fields of `DFSDM0_FCR`.
pub mod dfsdm0_fcr {
    use super::FieldSpec;
    /// `IOSR`, bits 0..=7.
    pub const IOSR: &FieldSpec = &super::REGISTERS[60].fields[0];
    /// `FOSR`, bits 16..=25.
    pub const FOSR: &FieldSpec = &super::REGISTERS[60].fields[1];
    /// `FORD`, bits 29..=31.
    pub const FORD: &FieldSpec = &super::REGISTERS[60].fields[2];
}

/// The fields of `DFSDM1_FCR`.
pub mod dfsdm1_fcr {
    use super::FieldSpec;
    /// `IOSR`, bits 0..=7.
    pub const IOSR: &FieldSpec = &super::REGISTERS[61].fields[0];
    /// `FOSR`, bits 16..=25.
    pub const FOSR: &FieldSpec = &super::REGISTERS[61].fields[1];
    /// `FORD`, bits 29..=31.
    pub const FORD: &FieldSpec = &super::REGISTERS[61].fields[2];
}

/// The fields of `DFSDM2_FCR`.
pub mod dfsdm2_fcr {
    use super::FieldSpec;
    /// `IOSR`, bits 0..=7.
    pub const IOSR: &FieldSpec = &super::REGISTERS[62].fields[0];
    /// `FOSR`, bits 16..=25.
    pub const FOSR: &FieldSpec = &super::REGISTERS[62].fields[1];
    /// `FORD`, bits 29..=31.
    pub const FORD: &FieldSpec = &super::REGISTERS[62].fields[2];
}

/// The fields of `DFSDM3_FCR`.
pub mod dfsdm3_fcr {
    use super::FieldSpec;
    /// `IOSR`, bits 0..=7.
    pub const IOSR: &FieldSpec = &super::REGISTERS[63].fields[0];
    /// `FOSR`, bits 16..=25.
    pub const FOSR: &FieldSpec = &super::REGISTERS[63].fields[1];
    /// `FORD`, bits 29..=31.
    pub const FORD: &FieldSpec = &super::REGISTERS[63].fields[2];
}

/// The fields of `DFSDM0_JDATAR`.
pub mod dfsdm0_jdatar {
    use super::FieldSpec;
    /// `JDATACH`, bits 0..=2.
    pub const JDATACH: &FieldSpec = &super::REGISTERS[64].fields[0];
    /// `JDATA`, bits 8..=31.
    pub const JDATA: &FieldSpec = &super::REGISTERS[64].fields[1];
}

/// The fields of `DFSDM1_JDATAR`.
pub mod dfsdm1_jdatar {
    use super::FieldSpec;
    /// `JDATACH`, bits 0..=2.
    pub const JDATACH: &FieldSpec = &super::REGISTERS[65].fields[0];
    /// `JDATA`, bits 8..=31.
    pub const JDATA: &FieldSpec = &super::REGISTERS[65].fields[1];
}

/// The fields of `DFSDM2_JDATAR`.
pub mod dfsdm2_jdatar {
    use super::FieldSpec;
    /// `JDATACH`, bits 0..=2.
    pub const JDATACH: &FieldSpec = &super::REGISTERS[66].fields[0];
    /// `JDATA`, bits 8..=31.
    pub const JDATA: &FieldSpec = &super::REGISTERS[66].fields[1];
}

/// The fields of `DFSDM3_JDATAR`.
pub mod dfsdm3_jdatar {
    use super::FieldSpec;
    /// `JDATACH`, bits 0..=2.
    pub const JDATACH: &FieldSpec = &super::REGISTERS[67].fields[0];
    /// `JDATA`, bits 8..=31.
    pub const JDATA: &FieldSpec = &super::REGISTERS[67].fields[1];
}

/// The fields of `DFSDM0_RDATAR`.
pub mod dfsdm0_rdatar {
    use super::FieldSpec;
    /// `RDATACH`, bits 0..=2.
    pub const RDATACH: &FieldSpec = &super::REGISTERS[68].fields[0];
    /// `RPEND`, bit 4.
    pub const RPEND: &FieldSpec = &super::REGISTERS[68].fields[1];
    /// `RDATA`, bits 8..=31.
    pub const RDATA: &FieldSpec = &super::REGISTERS[68].fields[2];
}

/// The fields of `DFSDM1_RDATAR`.
pub mod dfsdm1_rdatar {
    use super::FieldSpec;
    /// `RDATACH`, bits 0..=2.
    pub const RDATACH: &FieldSpec = &super::REGISTERS[69].fields[0];
    /// `RPEND`, bit 4.
    pub const RPEND: &FieldSpec = &super::REGISTERS[69].fields[1];
    /// `RDATA`, bits 8..=31.
    pub const RDATA: &FieldSpec = &super::REGISTERS[69].fields[2];
}

/// The fields of `DFSDM2_RDATAR`.
pub mod dfsdm2_rdatar {
    use super::FieldSpec;
    /// `RDATACH`, bits 0..=2.
    pub const RDATACH: &FieldSpec = &super::REGISTERS[70].fields[0];
    /// `RPEND`, bit 4.
    pub const RPEND: &FieldSpec = &super::REGISTERS[70].fields[1];
    /// `RDATA`, bits 8..=31.
    pub const RDATA: &FieldSpec = &super::REGISTERS[70].fields[2];
}

/// The fields of `DFSDM3_RDATAR`.
pub mod dfsdm3_rdatar {
    use super::FieldSpec;
    /// `RDATACH`, bits 0..=2.
    pub const RDATACH: &FieldSpec = &super::REGISTERS[71].fields[0];
    /// `RPEND`, bit 4.
    pub const RPEND: &FieldSpec = &super::REGISTERS[71].fields[1];
    /// `RDATA`, bits 8..=31.
    pub const RDATA: &FieldSpec = &super::REGISTERS[71].fields[2];
}

/// The fields of `DFSDM0_AWHTR`.
pub mod dfsdm0_awhtr {
    use super::FieldSpec;
    /// `BKAWH`, bits 0..=3.
    pub const BKAWH: &FieldSpec = &super::REGISTERS[72].fields[0];
    /// `AWHT`, bits 8..=31.
    pub const AWHT: &FieldSpec = &super::REGISTERS[72].fields[1];
}

/// The fields of `DFSDM1_AWHTR`.
pub mod dfsdm1_awhtr {
    use super::FieldSpec;
    /// `BKAWH`, bits 0..=3.
    pub const BKAWH: &FieldSpec = &super::REGISTERS[73].fields[0];
    /// `AWHT`, bits 8..=31.
    pub const AWHT: &FieldSpec = &super::REGISTERS[73].fields[1];
}

/// The fields of `DFSDM2_AWHTR`.
pub mod dfsdm2_awhtr {
    use super::FieldSpec;
    /// `BKAWH`, bits 0..=3.
    pub const BKAWH: &FieldSpec = &super::REGISTERS[74].fields[0];
    /// `AWHT`, bits 8..=31.
    pub const AWHT: &FieldSpec = &super::REGISTERS[74].fields[1];
}

/// The fields of `DFSDM3_AWHTR`.
pub mod dfsdm3_awhtr {
    use super::FieldSpec;
    /// `BKAWH`, bits 0..=3.
    pub const BKAWH: &FieldSpec = &super::REGISTERS[75].fields[0];
    /// `AWHT`, bits 8..=31.
    pub const AWHT: &FieldSpec = &super::REGISTERS[75].fields[1];
}

/// The fields of `DFSDM0_AWLTR`.
pub mod dfsdm0_awltr {
    use super::FieldSpec;
    /// `BKAWL`, bits 0..=3.
    pub const BKAWL: &FieldSpec = &super::REGISTERS[76].fields[0];
    /// `AWLT`, bits 8..=31.
    pub const AWLT: &FieldSpec = &super::REGISTERS[76].fields[1];
}

/// The fields of `DFSDM1_AWLTR`.
pub mod dfsdm1_awltr {
    use super::FieldSpec;
    /// `BKAWL`, bits 0..=3.
    pub const BKAWL: &FieldSpec = &super::REGISTERS[77].fields[0];
    /// `AWLT`, bits 8..=31.
    pub const AWLT: &FieldSpec = &super::REGISTERS[77].fields[1];
}

/// The fields of `DFSDM2_AWLTR`.
pub mod dfsdm2_awltr {
    use super::FieldSpec;
    /// `BKAWL`, bits 0..=3.
    pub const BKAWL: &FieldSpec = &super::REGISTERS[78].fields[0];
    /// `AWLT`, bits 8..=31.
    pub const AWLT: &FieldSpec = &super::REGISTERS[78].fields[1];
}

/// The fields of `DFSDM3_AWLTR`.
pub mod dfsdm3_awltr {
    use super::FieldSpec;
    /// `BKAWL`, bits 0..=3.
    pub const BKAWL: &FieldSpec = &super::REGISTERS[79].fields[0];
    /// `AWLT`, bits 8..=31.
    pub const AWLT: &FieldSpec = &super::REGISTERS[79].fields[1];
}

/// The fields of `DFSDM0_AWSR`.
pub mod dfsdm0_awsr {
    use super::FieldSpec;
    /// `AWLTF`, bits 0..=7.
    pub const AWLTF: &FieldSpec = &super::REGISTERS[80].fields[0];
    /// `AWHTF`, bits 8..=15.
    pub const AWHTF: &FieldSpec = &super::REGISTERS[80].fields[1];
}

/// The fields of `DFSDM1_AWSR`.
pub mod dfsdm1_awsr {
    use super::FieldSpec;
    /// `AWLTF`, bits 0..=7.
    pub const AWLTF: &FieldSpec = &super::REGISTERS[81].fields[0];
    /// `AWHTF`, bits 8..=15.
    pub const AWHTF: &FieldSpec = &super::REGISTERS[81].fields[1];
}

/// The fields of `DFSDM2_AWSR`.
pub mod dfsdm2_awsr {
    use super::FieldSpec;
    /// `AWLTF`, bits 0..=7.
    pub const AWLTF: &FieldSpec = &super::REGISTERS[82].fields[0];
    /// `AWHTF`, bits 8..=15.
    pub const AWHTF: &FieldSpec = &super::REGISTERS[82].fields[1];
}

/// The fields of `DFSDM3_AWSR`.
pub mod dfsdm3_awsr {
    use super::FieldSpec;
    /// `AWLTF`, bits 0..=7.
    pub const AWLTF: &FieldSpec = &super::REGISTERS[83].fields[0];
    /// `AWHTF`, bits 8..=15.
    pub const AWHTF: &FieldSpec = &super::REGISTERS[83].fields[1];
}

/// The fields of `DFSDM0_AWCFR`.
pub mod dfsdm0_awcfr {
    use super::FieldSpec;
    /// `CLRAWLTF`, bits 0..=7.
    pub const CLRAWLTF: &FieldSpec = &super::REGISTERS[84].fields[0];
    /// `CLRAWHTF`, bits 8..=15.
    pub const CLRAWHTF: &FieldSpec = &super::REGISTERS[84].fields[1];
}

/// The fields of `DFSDM1_AWCFR`.
pub mod dfsdm1_awcfr {
    use super::FieldSpec;
    /// `CLRAWLTF`, bits 0..=7.
    pub const CLRAWLTF: &FieldSpec = &super::REGISTERS[85].fields[0];
    /// `CLRAWHTF`, bits 8..=15.
    pub const CLRAWHTF: &FieldSpec = &super::REGISTERS[85].fields[1];
}

/// The fields of `DFSDM2_AWCFR`.
pub mod dfsdm2_awcfr {
    use super::FieldSpec;
    /// `CLRAWLTF`, bits 0..=7.
    pub const CLRAWLTF: &FieldSpec = &super::REGISTERS[86].fields[0];
    /// `CLRAWHTF`, bits 8..=15.
    pub const CLRAWHTF: &FieldSpec = &super::REGISTERS[86].fields[1];
}

/// The fields of `DFSDM3_AWCFR`.
pub mod dfsdm3_awcfr {
    use super::FieldSpec;
    /// `CLRAWLTF`, bits 0..=7.
    pub const CLRAWLTF: &FieldSpec = &super::REGISTERS[87].fields[0];
    /// `CLRAWHTF`, bits 8..=15.
    pub const CLRAWHTF: &FieldSpec = &super::REGISTERS[87].fields[1];
}

/// The fields of `DFSDM0_EXMAX`.
pub mod dfsdm0_exmax {
    use super::FieldSpec;
    /// `EXMAXCH`, bits 0..=2.
    pub const EXMAXCH: &FieldSpec = &super::REGISTERS[88].fields[0];
    /// `EXMAX`, bits 8..=31.
    pub const EXMAX: &FieldSpec = &super::REGISTERS[88].fields[1];
}

/// The fields of `DFSDM1_EXMAX`.
pub mod dfsdm1_exmax {
    use super::FieldSpec;
    /// `EXMAXCH`, bits 0..=2.
    pub const EXMAXCH: &FieldSpec = &super::REGISTERS[89].fields[0];
    /// `EXMAX`, bits 8..=31.
    pub const EXMAX: &FieldSpec = &super::REGISTERS[89].fields[1];
}

/// The fields of `DFSDM2_EXMAX`.
pub mod dfsdm2_exmax {
    use super::FieldSpec;
    /// `EXMAXCH`, bits 0..=2.
    pub const EXMAXCH: &FieldSpec = &super::REGISTERS[90].fields[0];
    /// `EXMAX`, bits 8..=31.
    pub const EXMAX: &FieldSpec = &super::REGISTERS[90].fields[1];
}

/// The fields of `DFSDM3_EXMAX`.
pub mod dfsdm3_exmax {
    use super::FieldSpec;
    /// `EXMAXCH`, bits 0..=2.
    pub const EXMAXCH: &FieldSpec = &super::REGISTERS[91].fields[0];
    /// `EXMAX`, bits 8..=31.
    pub const EXMAX: &FieldSpec = &super::REGISTERS[91].fields[1];
}

/// The fields of `DFSDM0_EXMIN`.
pub mod dfsdm0_exmin {
    use super::FieldSpec;
    /// `EXMINCH`, bits 0..=2.
    pub const EXMINCH: &FieldSpec = &super::REGISTERS[92].fields[0];
    /// `EXMIN`, bits 8..=31.
    pub const EXMIN: &FieldSpec = &super::REGISTERS[92].fields[1];
}

/// The fields of `DFSDM1_EXMIN`.
pub mod dfsdm1_exmin {
    use super::FieldSpec;
    /// `EXMINCH`, bits 0..=2.
    pub const EXMINCH: &FieldSpec = &super::REGISTERS[93].fields[0];
    /// `EXMIN`, bits 8..=31.
    pub const EXMIN: &FieldSpec = &super::REGISTERS[93].fields[1];
}

/// The fields of `DFSDM2_EXMIN`.
pub mod dfsdm2_exmin {
    use super::FieldSpec;
    /// `EXMINCH`, bits 0..=2.
    pub const EXMINCH: &FieldSpec = &super::REGISTERS[94].fields[0];
    /// `EXMIN`, bits 8..=31.
    pub const EXMIN: &FieldSpec = &super::REGISTERS[94].fields[1];
}

/// The fields of `DFSDM3_EXMIN`.
pub mod dfsdm3_exmin {
    use super::FieldSpec;
    /// `EXMINCH`, bits 0..=2.
    pub const EXMINCH: &FieldSpec = &super::REGISTERS[95].fields[0];
    /// `EXMIN`, bits 8..=31.
    pub const EXMIN: &FieldSpec = &super::REGISTERS[95].fields[1];
}

/// The fields of `DFSDM0_CNVTIMR`.
pub mod dfsdm0_cnvtimr {
    use super::FieldSpec;
    /// `CNVCNT`, bits 4..=31.
    pub const CNVCNT: &FieldSpec = &super::REGISTERS[96].fields[0];
}

/// The fields of `DFSDM1_CNVTIMR`.
pub mod dfsdm1_cnvtimr {
    use super::FieldSpec;
    /// `CNVCNT`, bits 4..=31.
    pub const CNVCNT: &FieldSpec = &super::REGISTERS[97].fields[0];
}

/// The fields of `DFSDM2_CNVTIMR`.
pub mod dfsdm2_cnvtimr {
    use super::FieldSpec;
    /// `CNVCNT`, bits 4..=31.
    pub const CNVCNT: &FieldSpec = &super::REGISTERS[98].fields[0];
}

/// The fields of `DFSDM3_CNVTIMR`.
pub mod dfsdm3_cnvtimr {
    use super::FieldSpec;
    /// `CNVCNT`, bits 4..=31.
    pub const CNVCNT: &FieldSpec = &super::REGISTERS[99].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 100] = [
    RegisterSpec { name: "DFSDM_CHCFG0R1", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG1R1", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG2R1", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG3R1", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG4R1", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG5R1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG6R1", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG7R1", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SITP", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SPICKSEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHINSEL", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATMPX", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DATPACK", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTDIV", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKOUTSRC", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DFSDMEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG0R2", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG1R2", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG2R2", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG3R2", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG4R2", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG5R2", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG6R2", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHCFG7R2", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DTRBS", bit: 3, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD0R", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD1R", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD2R", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD3R", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD4R", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD5R", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD6R", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_AWSCD7R", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SCDT", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BKSCD", bit: 12, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFOSR", bit: 16, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFORD", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT0R", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT1R", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT2R", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT3R", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT4R", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT5R", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT6R", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHWDAT7R", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN0R", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN1R", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN2R", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN3R", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN4R", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN5R", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN6R", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM_CHDATIN7R", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "INDAT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INDAT1", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_CR1", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DFEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSWSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSYNC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSCAN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDMAEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSWSTART", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCONT", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSYNC", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCH", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FAST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_CR1", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DFEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSWSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSYNC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSCAN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDMAEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSWSTART", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCONT", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSYNC", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCH", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FAST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_CR1", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DFEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSWSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSYNC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSCAN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDMAEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSWSTART", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCONT", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSYNC", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCH", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FAST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_CR1", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DFEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSWSTART", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSYNC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSCAN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDMAEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 13, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSWSTART", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCONT", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSYNC", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCH", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FAST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWFSEL", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_CR2", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXCH", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDCH", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_CR2", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXCH", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDCH", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_CR2", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXCH", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDCH", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_CR2", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXCH", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDCH", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_ISR", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JCIP", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCIP", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABF", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDF", bit: 24, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_ISR", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JCIP", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCIP", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABF", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDF", bit: 24, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_ISR", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JCIP", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCIP", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABF", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDF", bit: 24, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_ISR", offset: 0xCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JEOCF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "REOCF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVRF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVRF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JCIP", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RCIP", bit: 14, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKABF", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCDF", bit: 24, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_ICR", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRJOVRF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRROVRF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRCKABF", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRSCDF", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_ICR", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRJOVRF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRROVRF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRCKABF", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRSCDF", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_ICR", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRJOVRF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRROVRF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRCKABF", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRSCDF", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_ICR", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRJOVRF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRROVRF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRCKABF", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRSCDF", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_JCHGR", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JCHG", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_JCHGR", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JCHG", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_JCHGR", offset: 0xE8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JCHG", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_JCHGR", offset: 0xEC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JCHG", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_FCR", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IOSR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FOSR", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORD", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_FCR", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IOSR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FOSR", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORD", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_FCR", offset: 0xF8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IOSR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FOSR", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORD", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_FCR", offset: 0xFC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "IOSR", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FOSR", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORD", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_JDATAR", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_JDATAR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_JDATAR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_JDATAR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_RDATAR", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPEND", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_RDATAR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPEND", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_RDATAR", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPEND", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_RDATAR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATACH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RPEND", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RDATA", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_AWHTR", offset: 0x120, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWH", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_AWHTR", offset: 0x124, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWH", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_AWHTR", offset: 0x128, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWH", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_AWHTR", offset: 0x12C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWH", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_AWLTR", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWLT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_AWLTR", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWLT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_AWLTR", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWLT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_AWLTR", offset: 0x13C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BKAWL", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWLT", bit: 8, width: 24, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_AWSR", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWLTF", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHTF", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_AWSR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWLTF", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHTF", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_AWSR", offset: 0x148, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWLTF", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHTF", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_AWSR", offset: 0x14C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWLTF", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWHTF", bit: 8, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_AWCFR", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRAWLTF", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRAWHTF", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_AWCFR", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRAWLTF", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRAWHTF", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_AWCFR", offset: 0x158, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRAWLTF", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRAWHTF", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_AWCFR", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CLRAWLTF", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLRAWHTF", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_EXMAX", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMAXCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMAX", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_EXMAX", offset: 0x164, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMAXCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMAX", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_EXMAX", offset: 0x168, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMAXCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMAX", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_EXMAX", offset: 0x16C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMAXCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMAX", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_EXMIN", offset: 0x170, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMINCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMIN", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_EXMIN", offset: 0x174, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMINCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMIN", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_EXMIN", offset: 0x178, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMINCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMIN", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_EXMIN", offset: 0x17C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EXMINCH", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXMIN", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM0_CNVTIMR", offset: 0x180, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNVCNT", bit: 4, width: 28, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM1_CNVTIMR", offset: 0x184, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNVCNT", bit: 4, width: 28, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM2_CNVTIMR", offset: 0x188, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNVCNT", bit: 4, width: 28, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DFSDM3_CNVTIMR", offset: 0x18C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CNVCNT", bit: 4, width: 28, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];