// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `MDIOS` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
Cr = 0,
/// `WRFR` at offset `0x4`, resets to `0x0000_0000`, read-only.
Wrfr = 1,
/// `CWRFR` at offset `0x8`, resets to `0x0000_0000`, read-write.
Cwrfr = 2,
/// `RDFR` at offset `0xC`, resets to `0x0000_0000`, read-only.
Rdfr = 3,
/// `CRDFR` at offset `0x10`, resets to `0x0000_0000`, read-write.
Crdfr = 4,
/// `SR` at offset `0x14`, resets to `0x0000_0000`, read-only.
Sr = 5,
/// `CLRFR` at offset `0x18`, resets to `0x0000_0000`, read-write.
Clrfr = 6,
/// `DINR0` at offset `0x1C`, resets to `0x0000_0000`, read-only.
Dinr0 = 7,
/// `DINR1` at offset `0x20`, resets to `0x0000_0000`, read-only.
Dinr1 = 8,
/// `DINR2` at offset `0x24`, resets to `0x0000_0000`, read-only.
Dinr2 = 9,
/// `DINR3` at offset `0x28`, resets to `0x0000_0000`, read-only.
Dinr3 = 10,
/// `DINR4` at offset `0x2C`, resets to `0x0000_0000`, read-only.
Dinr4 = 11,
/// `DINR5` at offset `0x30`, resets to `0x0000_0000`, read-only.
Dinr5 = 12,
/// `DINR6` at offset `0x34`, resets to `0x0000_0000`, read-only.
Dinr6 = 13,
/// `DINR7` at offset `0x38`, resets to `0x0000_0000`, read-only.
Dinr7 = 14,
/// `DINR8` at offset `0x3C`, resets to `0x0000_0000`, read-only.
Dinr8 = 15,
/// `DINR9` at offset `0x40`, resets to `0x0000_0000`, read-only.
Dinr9 = 16,
/// `DINR10` at offset `0x44`, resets to `0x0000_0000`, read-only.
Dinr10 = 17,
/// `DINR11` at offset `0x48`, resets to `0x0000_0000`, read-only.
Dinr11 = 18,
/// `DINR12` at offset `0x4C`, resets to `0x0000_0000`, read-only.
Dinr12 = 19,
/// `DINR13` at offset `0x50`, resets to `0x0000_0000`, read-only.
Dinr13 = 20,
/// `DINR14` at offset `0x54`, resets to `0x0000_0000`, read-only.
Dinr14 = 21,
/// `DINR15` at offset `0x58`, resets to `0x0000_0000`, read-only.
Dinr15 = 22,
/// `DINR16` at offset `0x5C`, resets to `0x0000_0000`, read-only.
Dinr16 = 23,
/// `DINR17` at offset `0x60`, resets to `0x0000_0000`, read-only.
Dinr17 = 24,
/// `DINR18` at offset `0x64`, resets to `0x0000_0000`, read-only.
Dinr18 = 25,
/// `DINR19` at offset `0x68`, resets to `0x0000_0000`, read-only.
Dinr19 = 26,
/// `DINR20` at offset `0x6C`, resets to `0x0000_0000`, read-only.
Dinr20 = 27,
/// `DINR21` at offset `0x70`, resets to `0x0000_0000`, read-only.
Dinr21 = 28,
/// `DINR22` at offset `0x74`, resets to `0x0000_0000`, read-only.
Dinr22 = 29,
/// `DINR23` at offset `0x78`, resets to `0x0000_0000`, read-only.
Dinr23 = 30,
/// `DINR24` at offset `0x7C`, resets to `0x0000_0000`, read-only.
Dinr24 = 31,
/// `DINR25` at offset `0x80`, resets to `0x0000_0000`, read-only.
Dinr25 = 32,
/// `DINR26` at offset `0x84`, resets to `0x0000_0000`, read-only.
Dinr26 = 33,
/// `DINR27` at offset `0x88`, resets to `0x0000_0000`, read-only.
Dinr27 = 34,
/// `DINR28` at offset `0x8C`, resets to `0x0000_0000`, read-only.
Dinr28 = 35,
/// `DINR29` at offset `0x90`, resets to `0x0000_0000`, read-only.
Dinr29 = 36,
/// `DINR30` at offset `0x94`, resets to `0x0000_0000`, read-only.
Dinr30 = 37,
/// `DINR31` at offset `0x98`, resets to `0x0000_0000`, read-only.
Dinr31 = 38,
/// `DOUTR0` at offset `0x9C`, resets to `0x0000_0000`, read-write.
Doutr0 = 39,
/// `DOUTR1` at offset `0xA0`, resets to `0x0000_0000`, read-write.
Doutr1 = 40,
/// `DOUTR2` at offset `0xA4`, resets to `0x0000_0000`, read-write.
Doutr2 = 41,
/// `DOUTR3` at offset `0xA8`, resets to `0x0000_0000`, read-write.
Doutr3 = 42,
/// `DOUTR4` at offset `0xAC`, resets to `0x0000_0000`, read-write.
Doutr4 = 43,
/// `DOUTR5` at offset `0xB0`, resets to `0x0000_0000`, read-write.
Doutr5 = 44,
/// `DOUTR6` at offset `0xB4`, resets to `0x0000_0000`, read-write.
Doutr6 = 45,
/// `DOUTR7` at offset `0xB8`, resets to `0x0000_0000`, read-write.
Doutr7 = 46,
/// `DOUTR8` at offset `0xBC`, resets to `0x0000_0000`, read-write.
Doutr8 = 47,
/// `DOUTR9` at offset `0xC0`, resets to `0x0000_0000`, read-write.
Doutr9 = 48,
/// `DOUTR10` at offset `0xC4`, resets to `0x0000_0000`, read-write.
Doutr10 = 49,
/// `DOUTR11` at offset `0xC8`, resets to `0x0000_0000`, read-write.
Doutr11 = 50,
/// `DOUTR12` at offset `0xCC`, resets to `0x0000_0000`, read-write.
Doutr12 = 51,
/// `DOUTR13` at offset `0xD0`, resets to `0x0000_0000`, read-write.
Doutr13 = 52,
/// `DOUTR14` at offset `0xD4`, resets to `0x0000_0000`, read-write.
Doutr14 = 53,
/// `DOUTR15` at offset `0xD8`, resets to `0x0000_0000`, read-write.
Doutr15 = 54,
/// `DOUTR16` at offset `0xDC`, resets to `0x0000_0000`, read-write.
Doutr16 = 55,
/// `DOUTR17` at offset `0xE0`, resets to `0x0000_0000`, read-write.
Doutr17 = 56,
/// `DOUTR18` at offset `0xE4`, resets to `0x0000_0000`, read-write.
Doutr18 = 57,
/// `DOUTR19` at offset `0xE8`, resets to `0x0000_0000`, read-write.
Doutr19 = 58,
/// `DOUTR20` at offset `0xEC`, resets to `0x0000_0000`, read-write.
Doutr20 = 59,
/// `DOUTR21` at offset `0xF0`, resets to `0x0000_0000`, read-write.
Doutr21 = 60,
/// `DOUTR22` at offset `0xF4`, resets to `0x0000_0000`, read-write.
Doutr22 = 61,
/// `DOUTR23` at offset `0xF8`, resets to `0x0000_0000`, read-write.
Doutr23 = 62,
/// `DOUTR24` at offset `0xFC`, resets to `0x0000_0000`, read-write.
Doutr24 = 63,
/// `DOUTR25` at offset `0x100`, resets to `0x0000_0000`, read-write.
Doutr25 = 64,
/// `DOUTR26` at offset `0x104`, resets to `0x0000_0000`, read-write.
Doutr26 = 65,
/// `DOUTR27` at offset `0x108`, resets to `0x0000_0000`, read-write.
Doutr27 = 66,
/// `DOUTR28` at offset `0x10C`, resets to `0x0000_0000`, read-write.
Doutr28 = 67,
/// `DOUTR29` at offset `0x110`, resets to `0x0000_0000`, read-write.
Doutr29 = 68,
/// `DOUTR30` at offset `0x114`, resets to `0x0000_0000`, read-write.
Doutr30 = 69,
/// `DOUTR31` at offset `0x118`, resets to `0x0000_0000`, read-write.
Doutr31 = 70,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 71] = [Self::Cr, Self::Wrfr, Self::Cwrfr, Self::Rdfr, Self::Crdfr, Self::Sr, Self::Clrfr, Self::Dinr0, Self::Dinr1, Self::Dinr2, Self::Dinr3, Self::Dinr4, Self::Dinr5, Self::Dinr6, Self::Dinr7, Self::Dinr8, Self::Dinr9, Self::Dinr10, Self::Dinr11, Self::Dinr12, Self::Dinr13, Self::Dinr14, Self::Dinr15, Self::Dinr16, Self::Dinr17, Self::Dinr18, Self::Dinr19, Self::Dinr20, Self::Dinr21, Self::Dinr22, Self::Dinr23, Self::Dinr24, Self::Dinr25, Self::Dinr26, Self::Dinr27, Self::Dinr28, Self::Dinr29, Self::Dinr30, Self::Dinr31, Self::Doutr0, Self::Doutr1, Self::Doutr2, Self::Doutr3, Self::Doutr4, Self::Doutr5, Self::Doutr6, Self::Doutr7, Self::Doutr8, Self::Doutr9, Self::Doutr10, Self::Doutr11, Self::Doutr12, Self::Doutr13, Self::Doutr14, Self::Doutr15, Self::Doutr16, Self::Doutr17, Self::Doutr18, Self::Doutr19, Self::Doutr20, Self::Doutr21, Self::Doutr22, Self::Doutr23, Self::Doutr24, Self::Doutr25, Self::Doutr26, Self::Doutr27, Self::Doutr28, Self::Doutr29, Self::Doutr30, Self::Doutr31];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `CR`.
pub mod cr {
use super::FieldSpec;
/// `EN`, bit 0.
pub const EN: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `WRIE`, bit 1.
pub const WRIE: &FieldSpec = &super::REGISTERS[0].fields[1];
/// `RDIE`, bit 2.
pub const RDIE: &FieldSpec = &super::REGISTERS[0].fields[2];
/// `EIE`, bit 3.
pub const EIE: &FieldSpec = &super::REGISTERS[0].fields[3];
/// `DPC`, bit 7.
pub const DPC: &FieldSpec = &super::REGISTERS[0].fields[4];
/// `PORT_ADDRESS`, bits 8..=12.
pub const PORT_ADDRESS: &FieldSpec = &super::REGISTERS[0].fields[5];
}
/// The fields of `WRFR`.
pub mod wrfr {
use super::FieldSpec;
/// `WRF`, bits 0..=31.
pub const WRF: &FieldSpec = &super::REGISTERS[1].fields[0];
}
/// The fields of `CWRFR`.
pub mod cwrfr {
use super::FieldSpec;
/// `CWRF`, bits 0..=31.
pub const CWRF: &FieldSpec = &super::REGISTERS[2].fields[0];
}
/// The fields of `RDFR`.
pub mod rdfr {
use super::FieldSpec;
/// `RDF`, bits 0..=31.
pub const RDF: &FieldSpec = &super::REGISTERS[3].fields[0];
}
/// The fields of `CRDFR`.
pub mod crdfr {
use super::FieldSpec;
/// `CRDF`, bits 0..=31.
pub const CRDF: &FieldSpec = &super::REGISTERS[4].fields[0];
}
/// The fields of `SR`.
pub mod sr {
use super::FieldSpec;
/// `PERF`, bit 0.
pub const PERF: &FieldSpec = &super::REGISTERS[5].fields[0];
/// `SERF`, bit 1.
pub const SERF: &FieldSpec = &super::REGISTERS[5].fields[1];
/// `TERF`, bit 2.
pub const TERF: &FieldSpec = &super::REGISTERS[5].fields[2];
}
/// The fields of `CLRFR`.
pub mod clrfr {
use super::FieldSpec;
/// `CPERF`, bit 0.
pub const CPERF: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `CSERF`, bit 1.
pub const CSERF: &FieldSpec = &super::REGISTERS[6].fields[1];
/// `CTERF`, bit 2.
pub const CTERF: &FieldSpec = &super::REGISTERS[6].fields[2];
}
/// The fields of `DINR0`.
pub mod dinr0 {
use super::FieldSpec;
/// `DIN0`, bits 0..=15.
pub const DIN0: &FieldSpec = &super::REGISTERS[7].fields[0];
}
/// The fields of `DINR1`.
pub mod dinr1 {
use super::FieldSpec;
/// `DIN1`, bits 0..=15.
pub const DIN1: &FieldSpec = &super::REGISTERS[8].fields[0];
}
/// The fields of `DINR2`.
pub mod dinr2 {
use super::FieldSpec;
/// `DIN2`, bits 0..=15.
pub const DIN2: &FieldSpec = &super::REGISTERS[9].fields[0];
}
/// The fields of `DINR3`.
pub mod dinr3 {
use super::FieldSpec;
/// `DIN3`, bits 0..=15.
pub const DIN3: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `DINR4`.
pub mod dinr4 {
use super::FieldSpec;
/// `DIN4`, bits 0..=15.
pub const DIN4: &FieldSpec = &super::REGISTERS[11].fields[0];
}
/// The fields of `DINR5`.
pub mod dinr5 {
use super::FieldSpec;
/// `DIN5`, bits 0..=15.
pub const DIN5: &FieldSpec = &super::REGISTERS[12].fields[0];
}
/// The fields of `DINR6`.
pub mod dinr6 {
use super::FieldSpec;
/// `DIN6`, bits 0..=15.
pub const DIN6: &FieldSpec = &super::REGISTERS[13].fields[0];
}
/// The fields of `DINR7`.
pub mod dinr7 {
use super::FieldSpec;
/// `DIN7`, bits 0..=15.
pub const DIN7: &FieldSpec = &super::REGISTERS[14].fields[0];
}
/// The fields of `DINR8`.
pub mod dinr8 {
use super::FieldSpec;
/// `DIN8`, bits 0..=15.
pub const DIN8: &FieldSpec = &super::REGISTERS[15].fields[0];
}
/// The fields of `DINR9`.
pub mod dinr9 {
use super::FieldSpec;
/// `DIN9`, bits 0..=15.
pub const DIN9: &FieldSpec = &super::REGISTERS[16].fields[0];
}
/// The fields of `DINR10`.
pub mod dinr10 {
use super::FieldSpec;
/// `DIN10`, bits 0..=15.
pub const DIN10: &FieldSpec = &super::REGISTERS[17].fields[0];
}
/// The fields of `DINR11`.
pub mod dinr11 {
use super::FieldSpec;
/// `DIN11`, bits 0..=15.
pub const DIN11: &FieldSpec = &super::REGISTERS[18].fields[0];
}
/// The fields of `DINR12`.
pub mod dinr12 {
use super::FieldSpec;
/// `DIN12`, bits 0..=15.
pub const DIN12: &FieldSpec = &super::REGISTERS[19].fields[0];
}
/// The fields of `DINR13`.
pub mod dinr13 {
use super::FieldSpec;
/// `DIN13`, bits 0..=15.
pub const DIN13: &FieldSpec = &super::REGISTERS[20].fields[0];
}
/// The fields of `DINR14`.
pub mod dinr14 {
use super::FieldSpec;
/// `DIN14`, bits 0..=15.
pub const DIN14: &FieldSpec = &super::REGISTERS[21].fields[0];
}
/// The fields of `DINR15`.
pub mod dinr15 {
use super::FieldSpec;
/// `DIN15`, bits 0..=15.
pub const DIN15: &FieldSpec = &super::REGISTERS[22].fields[0];
}
/// The fields of `DINR16`.
pub mod dinr16 {
use super::FieldSpec;
/// `DIN16`, bits 0..=15.
pub const DIN16: &FieldSpec = &super::REGISTERS[23].fields[0];
}
/// The fields of `DINR17`.
pub mod dinr17 {
use super::FieldSpec;
/// `DIN17`, bits 0..=15.
pub const DIN17: &FieldSpec = &super::REGISTERS[24].fields[0];
}
/// The fields of `DINR18`.
pub mod dinr18 {
use super::FieldSpec;
/// `DIN18`, bits 0..=15.
pub const DIN18: &FieldSpec = &super::REGISTERS[25].fields[0];
}
/// The fields of `DINR19`.
pub mod dinr19 {
use super::FieldSpec;
/// `DIN19`, bits 0..=15.
pub const DIN19: &FieldSpec = &super::REGISTERS[26].fields[0];
}
/// The fields of `DINR20`.
pub mod dinr20 {
use super::FieldSpec;
/// `DIN20`, bits 0..=15.
pub const DIN20: &FieldSpec = &super::REGISTERS[27].fields[0];
}
/// The fields of `DINR21`.
pub mod dinr21 {
use super::FieldSpec;
/// `DIN21`, bits 0..=15.
pub const DIN21: &FieldSpec = &super::REGISTERS[28].fields[0];
}
/// The fields of `DINR22`.
pub mod dinr22 {
use super::FieldSpec;
/// `DIN22`, bits 0..=15.
pub const DIN22: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `DINR23`.
pub mod dinr23 {
use super::FieldSpec;
/// `DIN23`, bits 0..=15.
pub const DIN23: &FieldSpec = &super::REGISTERS[30].fields[0];
}
/// The fields of `DINR24`.
pub mod dinr24 {
use super::FieldSpec;
/// `DIN24`, bits 0..=15.
pub const DIN24: &FieldSpec = &super::REGISTERS[31].fields[0];
}
/// The fields of `DINR25`.
pub mod dinr25 {
use super::FieldSpec;
/// `DIN25`, bits 0..=15.
pub const DIN25: &FieldSpec = &super::REGISTERS[32].fields[0];
}
/// The fields of `DINR26`.
pub mod dinr26 {
use super::FieldSpec;
/// `DIN26`, bits 0..=15.
pub const DIN26: &FieldSpec = &super::REGISTERS[33].fields[0];
}
/// The fields of `DINR27`.
pub mod dinr27 {
use super::FieldSpec;
/// `DIN27`, bits 0..=15.
pub const DIN27: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `DINR28`.
pub mod dinr28 {
use super::FieldSpec;
/// `DIN28`, bits 0..=15.
pub const DIN28: &FieldSpec = &super::REGISTERS[35].fields[0];
}
/// The fields of `DINR29`.
pub mod dinr29 {
use super::FieldSpec;
/// `DIN29`, bits 0..=15.
pub const DIN29: &FieldSpec = &super::REGISTERS[36].fields[0];
}
/// The fields of `DINR30`.
pub mod dinr30 {
use super::FieldSpec;
/// `DIN30`, bits 0..=15.
pub const DIN30: &FieldSpec = &super::REGISTERS[37].fields[0];
}
/// The fields of `DINR31`.
pub mod dinr31 {
use super::FieldSpec;
/// `DIN31`, bits 0..=15.
pub const DIN31: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The fields of `DOUTR0`.
pub mod doutr0 {
use super::FieldSpec;
/// `DOUT0`, bits 0..=15.
pub const DOUT0: &FieldSpec = &super::REGISTERS[39].fields[0];
}
/// The fields of `DOUTR1`.
pub mod doutr1 {
use super::FieldSpec;
/// `DOUT1`, bits 0..=15.
pub const DOUT1: &FieldSpec = &super::REGISTERS[40].fields[0];
}
/// The fields of `DOUTR2`.
pub mod doutr2 {
use super::FieldSpec;
/// `DOUT2`, bits 0..=15.
pub const DOUT2: &FieldSpec = &super::REGISTERS[41].fields[0];
}
/// The fields of `DOUTR3`.
pub mod doutr3 {
use super::FieldSpec;
/// `DOUT3`, bits 0..=15.
pub const DOUT3: &FieldSpec = &super::REGISTERS[42].fields[0];
}
/// The fields of `DOUTR4`.
pub mod doutr4 {
use super::FieldSpec;
/// `DOUT4`, bits 0..=15.
pub const DOUT4: &FieldSpec = &super::REGISTERS[43].fields[0];
}
/// The fields of `DOUTR5`.
pub mod doutr5 {
use super::FieldSpec;
/// `DOUT5`, bits 0..=15.
pub const DOUT5: &FieldSpec = &super::REGISTERS[44].fields[0];
}
/// The fields of `DOUTR6`.
pub mod doutr6 {
use super::FieldSpec;
/// `DOUT6`, bits 0..=15.
pub const DOUT6: &FieldSpec = &super::REGISTERS[45].fields[0];
}
/// The fields of `DOUTR7`.
pub mod doutr7 {
use super::FieldSpec;
/// `DOUT7`, bits 0..=15.
pub const DOUT7: &FieldSpec = &super::REGISTERS[46].fields[0];
}
/// The fields of `DOUTR8`.
pub mod doutr8 {
use super::FieldSpec;
/// `DOUT8`, bits 0..=15.
pub const DOUT8: &FieldSpec = &super::REGISTERS[47].fields[0];
}
/// The fields of `DOUTR9`.
pub mod doutr9 {
use super::FieldSpec;
/// `DOUT9`, bits 0..=15.
pub const DOUT9: &FieldSpec = &super::REGISTERS[48].fields[0];
}
/// The fields of `DOUTR10`.
pub mod doutr10 {
use super::FieldSpec;
/// `DOUT10`, bits 0..=15.
pub const DOUT10: &FieldSpec = &super::REGISTERS[49].fields[0];
}
/// The fields of `DOUTR11`.
pub mod doutr11 {
use super::FieldSpec;
/// `DOUT11`, bits 0..=15.
pub const DOUT11: &FieldSpec = &super::REGISTERS[50].fields[0];
}
/// The fields of `DOUTR12`.
pub mod doutr12 {
use super::FieldSpec;
/// `DOUT12`, bits 0..=15.
pub const DOUT12: &FieldSpec = &super::REGISTERS[51].fields[0];
}
/// The fields of `DOUTR13`.
pub mod doutr13 {
use super::FieldSpec;
/// `DOUT13`, bits 0..=15.
pub const DOUT13: &FieldSpec = &super::REGISTERS[52].fields[0];
}
/// The fields of `DOUTR14`.
pub mod doutr14 {
use super::FieldSpec;
/// `DOUT14`, bits 0..=15.
pub const DOUT14: &FieldSpec = &super::REGISTERS[53].fields[0];
}
/// The fields of `DOUTR15`.
pub mod doutr15 {
use super::FieldSpec;
/// `DOUT15`, bits 0..=15.
pub const DOUT15: &FieldSpec = &super::REGISTERS[54].fields[0];
}
/// The fields of `DOUTR16`.
pub mod doutr16 {
use super::FieldSpec;
/// `DOUT16`, bits 0..=15.
pub const DOUT16: &FieldSpec = &super::REGISTERS[55].fields[0];
}
/// The fields of `DOUTR17`.
pub mod doutr17 {
use super::FieldSpec;
/// `DOUT17`, bits 0..=15.
pub const DOUT17: &FieldSpec = &super::REGISTERS[56].fields[0];
}
/// The fields of `DOUTR18`.
pub mod doutr18 {
use super::FieldSpec;
/// `DOUT18`, bits 0..=15.
pub const DOUT18: &FieldSpec = &super::REGISTERS[57].fields[0];
}
/// The fields of `DOUTR19`.
pub mod doutr19 {
use super::FieldSpec;
/// `DOUT19`, bits 0..=15.
pub const DOUT19: &FieldSpec = &super::REGISTERS[58].fields[0];
}
/// The fields of `DOUTR20`.
pub mod doutr20 {
use super::FieldSpec;
/// `DOUT20`, bits 0..=15.
pub const DOUT20: &FieldSpec = &super::REGISTERS[59].fields[0];
}
/// The fields of `DOUTR21`.
pub mod doutr21 {
use super::FieldSpec;
/// `DOUT21`, bits 0..=15.
pub const DOUT21: &FieldSpec = &super::REGISTERS[60].fields[0];
}
/// The fields of `DOUTR22`.
pub mod doutr22 {
use super::FieldSpec;
/// `DOUT22`, bits 0..=15.
pub const DOUT22: &FieldSpec = &super::REGISTERS[61].fields[0];
}
/// The fields of `DOUTR23`.
pub mod doutr23 {
use super::FieldSpec;
/// `DOUT23`, bits 0..=15.
pub const DOUT23: &FieldSpec = &super::REGISTERS[62].fields[0];
}
/// The fields of `DOUTR24`.
pub mod doutr24 {
use super::FieldSpec;
/// `DOUT24`, bits 0..=15.
pub const DOUT24: &FieldSpec = &super::REGISTERS[63].fields[0];
}
/// The fields of `DOUTR25`.
pub mod doutr25 {
use super::FieldSpec;
/// `DOUT25`, bits 0..=15.
pub const DOUT25: &FieldSpec = &super::REGISTERS[64].fields[0];
}
/// The fields of `DOUTR26`.
pub mod doutr26 {
use super::FieldSpec;
/// `DOUT26`, bits 0..=15.
pub const DOUT26: &FieldSpec = &super::REGISTERS[65].fields[0];
}
/// The fields of `DOUTR27`.
pub mod doutr27 {
use super::FieldSpec;
/// `DOUT27`, bits 0..=15.
pub const DOUT27: &FieldSpec = &super::REGISTERS[66].fields[0];
}
/// The fields of `DOUTR28`.
pub mod doutr28 {
use super::FieldSpec;
/// `DOUT28`, bits 0..=15.
pub const DOUT28: &FieldSpec = &super::REGISTERS[67].fields[0];
}
/// The fields of `DOUTR29`.
pub mod doutr29 {
use super::FieldSpec;
/// `DOUT29`, bits 0..=15.
pub const DOUT29: &FieldSpec = &super::REGISTERS[68].fields[0];
}
/// The fields of `DOUTR30`.
pub mod doutr30 {
use super::FieldSpec;
/// `DOUT30`, bits 0..=15.
pub const DOUT30: &FieldSpec = &super::REGISTERS[69].fields[0];
}
/// The fields of `DOUTR31`.
pub mod doutr31 {
use super::FieldSpec;
/// `DOUT31`, bits 0..=15.
pub const DOUT31: &FieldSpec = &super::REGISTERS[70].fields[0];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 71] = [
RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RDIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "EIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DPC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PORT_ADDRESS", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "WRFR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WRF", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CWRFR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CWRF", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "RDFR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RDF", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRDFR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRDF", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "SR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PERF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SERF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TERF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CLRFR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CPERF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSERF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CTERF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR0", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN0", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR1", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN1", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR2", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN2", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR3", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN3", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR4", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN4", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR5", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN5", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR6", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN6", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR7", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN7", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR8", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN8", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR9", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN9", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR10", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN10", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR11", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN11", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR12", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN12", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR13", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN13", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR14", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN14", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR15", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN15", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR16", offset: 0x5C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN16", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR17", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN17", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR18", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN18", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR19", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN19", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR20", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN20", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR21", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN21", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR22", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN22", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR23", offset: 0x78, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN23", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR24", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN24", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR25", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN25", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR26", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN26", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR27", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN27", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR28", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN28", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR29", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN29", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR30", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN30", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DINR31", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIN31", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR0", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT0", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR1", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT1", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR2", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT2", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR3", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT3", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR4", offset: 0xAC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT4", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR5", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT5", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR6", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT6", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR7", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT7", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR8", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT8", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR9", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT9", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR10", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT10", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR11", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT11", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR12", offset: 0xCC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT12", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR13", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT13", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR14", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT14", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR15", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT15", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR16", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT16", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR17", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT17", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR18", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT18", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR19", offset: 0xE8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT19", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR20", offset: 0xEC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT20", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR21", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT21", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR22", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT22", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR23", offset: 0xF8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT23", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR24", offset: 0xFC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT24", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR25", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT25", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR26", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT26", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR27", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT27", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR28", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT28", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR29", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT29", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR30", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT30", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "DOUTR31", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DOUT31", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
];