rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `DMA2D` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `ISR` at offset `0x4`, resets to `0x0000_0000`, read-only.
    Isr = 1,
    /// `IFCR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Ifcr = 2,
    /// `FGMAR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Fgmar = 3,
    /// `FGOR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Fgor = 4,
    /// `BGMAR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Bgmar = 5,
    /// `BGOR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Bgor = 6,
    /// `FGPFCCR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Fgpfccr = 7,
    /// `FGCOLR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Fgcolr = 8,
    /// `BGPFCCR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Bgpfccr = 9,
    /// `BGCOLR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Bgcolr = 10,
    /// `FGCMAR` at offset `0x2C`, resets to `0x0000_0000`, read-write.
    Fgcmar = 11,
    /// `BGCMAR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Bgcmar = 12,
    /// `OPFCCR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Opfccr = 13,
    /// `OCOLR` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Ocolr = 14,
    /// `OMAR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Omar = 15,
    /// `OOR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    Oor = 16,
    /// `NLR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    Nlr = 17,
    /// `LWR` at offset `0x48`, resets to `0x0000_0000`, read-write.
    Lwr = 18,
    /// `AMTCR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Amtcr = 19,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 20] = [Self::Cr, Self::Isr, Self::Ifcr, Self::Fgmar, Self::Fgor, Self::Bgmar, Self::Bgor, Self::Fgpfccr, Self::Fgcolr, Self::Bgpfccr, Self::Bgcolr, Self::Fgcmar, Self::Bgcmar, Self::Opfccr, Self::Ocolr, Self::Omar, Self::Oor, Self::Nlr, Self::Lwr, Self::Amtcr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `START`, bit 0.
    pub const START: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SUSP`, bit 1.
    pub const SUSP: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `ABORT`, bit 2.
    pub const ABORT: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `TEIE`, bit 8.
    pub const TEIE: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `TCIE`, bit 9.
    pub const TCIE: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `TWIE`, bit 10.
    pub const TWIE: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `CAEIE`, bit 11.
    pub const CAEIE: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `CTCIE`, bit 12.
    pub const CTCIE: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `CEIE`, bit 13.
    pub const CEIE: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `MODE`, bits 16..=17.
    pub const MODE: &FieldSpec = &super::REGISTERS[0].fields[9];
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `TEIF`, bit 0.
    pub const TEIF: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TCIF`, bit 1.
    pub const TCIF: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `TWIF`, bit 2.
    pub const TWIF: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `CAEIF`, bit 3.
    pub const CAEIF: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CTCIF`, bit 4.
    pub const CTCIF: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `CEIF`, bit 5.
    pub const CEIF: &FieldSpec = &super::REGISTERS[1].fields[5];
}

/// The fields of `IFCR`.
pub mod ifcr {
    use super::FieldSpec;
    /// `CTEIF`, bit 0.
    pub const CTEIF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CTCIF`, bit 1.
    pub const CTCIF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `CTWIF`, bit 2.
    pub const CTWIF: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `CAECIF`, bit 3.
    pub const CAECIF: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `CCTCIF`, bit 4.
    pub const CCTCIF: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `CCEIF`, bit 5.
    pub const CCEIF: &FieldSpec = &super::REGISTERS[2].fields[5];
}

/// The fields of `FGMAR`.
pub mod fgmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `FGOR`.
pub mod fgor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `BGMAR`.
pub mod bgmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `BGOR`.
pub mod bgor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `FGPFCCR`.
pub mod fgpfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=3.
    pub const CM: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `CCM`, bit 4.
    pub const CCM: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `START`, bit 5.
    pub const START: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `CS`, bits 8..=15.
    pub const CS: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `AM`, bits 16..=17.
    pub const AM: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CSS`, bits 18..=19.
    pub const CSS: &FieldSpec = &super::REGISTERS[7].fields[5];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[7].fields[6];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[7].fields[7];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[7].fields[8];
}

/// The fields of `FGCOLR`.
pub mod fgcolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[8].fields[2];
}

/// The fields of `BGPFCCR`.
pub mod bgpfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=3.
    pub const CM: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `CCM`, bit 4.
    pub const CCM: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `START`, bit 5.
    pub const START: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `CS`, bits 8..=15.
    pub const CS: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `AM`, bits 16..=17.
    pub const AM: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[9].fields[7];
}

/// The fields of `BGCOLR`.
pub mod bgcolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[10].fields[2];
}

/// The fields of `FGCMAR`.
pub mod fgcmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `BGCMAR`.
pub mod bgcmar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The fields of `OPFCCR`.
pub mod opfccr {
    use super::FieldSpec;
    /// `CM`, bits 0..=2.
    pub const CM: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `AI`, bit 20.
    pub const AI: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `RBS`, bit 21.
    pub const RBS: &FieldSpec = &super::REGISTERS[13].fields[2];
}

/// The fields of `OCOLR`.
pub mod ocolr {
    use super::FieldSpec;
    /// `BLUE`, bits 0..=7.
    pub const BLUE: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `GREEN`, bits 8..=15.
    pub const GREEN: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `RED`, bits 16..=23.
    pub const RED: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `ALPHA`, bits 24..=31.
    pub const ALPHA: &FieldSpec = &super::REGISTERS[14].fields[3];
}

/// The fields of `OMAR`.
pub mod omar {
    use super::FieldSpec;
    /// `MA`, bits 0..=31.
    pub const MA: &FieldSpec = &super::REGISTERS[15].fields[0];
}

/// The fields of `OOR`.
pub mod oor {
    use super::FieldSpec;
    /// `LO`, bits 0..=13.
    pub const LO: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `NLR`.
pub mod nlr {
    use super::FieldSpec;
    /// `NL`, bits 0..=15.
    pub const NL: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `PL`, bits 16..=29.
    pub const PL: &FieldSpec = &super::REGISTERS[17].fields[1];
}

/// The fields of `LWR`.
pub mod lwr {
    use super::FieldSpec;
    /// `LW`, bits 0..=15.
    pub const LW: &FieldSpec = &super::REGISTERS[18].fields[0];
}

/// The fields of `AMTCR`.
pub mod amtcr {
    use super::FieldSpec;
    /// `EN`, bit 0.
    pub const EN: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `DT`, bits 8..=15.
    pub const DT: &FieldSpec = &super::REGISTERS[19].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 20] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "START", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SUSP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ABORT", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAEIE", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIE", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEIE", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MODE", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "ISR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TEIF", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TCIF", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TWIF", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAEIF", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CEIF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IFCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CTEIF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTCIF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CTWIF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAECIF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCTCIF", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCEIF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FGMAR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FGOR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BGMAR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BGOR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FGPFCCR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AM", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSS", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FGCOLR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BGPFCCR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCM", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "START", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AM", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BGCOLR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "FGCMAR", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "BGCMAR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPFCCR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CM", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AI", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RBS", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OCOLR", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BLUE", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GREEN", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RED", bit: 16, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALPHA", bit: 24, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OMAR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OOR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LO", bit: 0, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "NLR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "NL", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PL", bit: 16, width: 14, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LWR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LW", bit: 0, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AMTCR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DT", bit: 8, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];