// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `AXI` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `AXI_PERIPH_ID_4` at offset `0x1FD0`, resets to `0x0000_0004`, read-only.
AxiPeriphId4 = 0,
/// `AXI_PERIPH_ID_0` at offset `0x1FE0`, resets to `0x0000_0004`, read-only.
AxiPeriphId0 = 1,
/// `AXI_PERIPH_ID_1` at offset `0x1FE4`, resets to `0x0000_0004`, read-only.
AxiPeriphId1 = 2,
/// `AXI_PERIPH_ID_2` at offset `0x1FE8`, resets to `0x0000_0004`, read-only.
AxiPeriphId2 = 3,
/// `AXI_PERIPH_ID_3` at offset `0x1FEC`, resets to `0x0000_0004`, read-only.
AxiPeriphId3 = 4,
/// `AXI_COMP_ID_0` at offset `0x1FF0`, resets to `0x0000_0004`, read-only.
AxiCompId0 = 5,
/// `AXI_COMP_ID_1` at offset `0x1FF4`, resets to `0x0000_0004`, read-only.
AxiCompId1 = 6,
/// `AXI_COMP_ID_2` at offset `0x1FF8`, resets to `0x0000_0004`, read-only.
AxiCompId2 = 7,
/// `AXI_COMP_ID_3` at offset `0x1FFC`, resets to `0x0000_0004`, read-only.
AxiCompId3 = 8,
/// `AXI_TARG1_FN_MOD_ISS_BM` at offset `0x2008`, resets to `0x0000_0004`, read-write.
AxiTarg1FnModIssBm = 9,
/// `AXI_TARG1_FN_MOD2` at offset `0x2024`, resets to `0x0000_0004`, read-write.
AxiTarg1FnMod2 = 10,
/// `AXI_TARG1_FN_MOD_LB` at offset `0x202C`, resets to `0x0000_0004`, read-write.
AxiTarg1FnModLb = 11,
/// `AXI_TARG1_FN_MOD` at offset `0x2108`, resets to `0x0000_0004`, read-write.
AxiTarg1FnMod = 12,
/// `AXI_TARG2_FN_MOD_ISS_BM` at offset `0x3008`, resets to `0x0000_0004`, read-write.
AxiTarg2FnModIssBm = 13,
/// `AXI_TARG2_FN_MOD2` at offset `0x3024`, resets to `0x0000_0004`, read-write.
AxiTarg2FnMod2 = 14,
/// `AXI_TARG2_FN_MOD_LB` at offset `0x302C`, resets to `0x0000_0004`, read-write.
AxiTarg2FnModLb = 15,
/// `AXI_TARG2_FN_MOD` at offset `0x3108`, resets to `0x0000_0004`, read-write.
AxiTarg2FnMod = 16,
/// `AXI_TARG3_FN_MOD_ISS_BM` at offset `0x4008`, resets to `0x0000_0004`, read-write.
AxiTarg3FnModIssBm = 17,
/// `AXI_TARG4_FN_MOD_ISS_BM` at offset `0x5008`, resets to `0x0000_0004`, read-write.
AxiTarg4FnModIssBm = 18,
/// `AXI_TARG5_FN_MOD_ISS_BM` at offset `0x6008`, resets to `0x0000_0004`, read-write.
AxiTarg5FnModIssBm = 19,
/// `AXI_TARG6_FN_MOD_ISS_BM` at offset `0x7008`, resets to `0x0000_0004`, read-write.
AxiTarg6FnModIssBm = 20,
/// `AXI_TARG7_FN_MOD_ISS_BM` at offset `0x800C`, resets to `0x0000_0004`, read-write.
AxiTarg7FnModIssBm = 21,
/// `AXI_TARG7_FN_MOD2` at offset `0x8024`, resets to `0x0000_0004`, read-write.
AxiTarg7FnMod2 = 22,
/// `AXI_TARG7_FN_MOD` at offset `0x8108`, resets to `0x0000_0004`, read-write.
AxiTarg7FnMod = 23,
/// `AXI_INI1_FN_MOD2` at offset `0x4_2024`, resets to `0x0000_0004`, read-write.
AxiIni1FnMod2 = 24,
/// `AXI_INI1_FN_MOD_AHB` at offset `0x4_2028`, resets to `0x0000_0004`, read-write.
AxiIni1FnModAhb = 25,
/// `AXI_INI1_READ_QOS` at offset `0x4_2100`, resets to `0x0000_0004`, read-write.
AxiIni1ReadQos = 26,
/// `AXI_INI1_WRITE_QOS` at offset `0x4_2104`, resets to `0x0000_0004`, read-write.
AxiIni1WriteQos = 27,
/// `AXI_INI1_FN_MOD` at offset `0x4_2108`, resets to `0x0000_0004`, read-write.
AxiIni1FnMod = 28,
/// `AXI_INI2_READ_QOS` at offset `0x4_3100`, resets to `0x0000_0004`, read-write.
AxiIni2ReadQos = 29,
/// `AXI_INI2_WRITE_QOS` at offset `0x4_3104`, resets to `0x0000_0004`, read-write.
AxiIni2WriteQos = 30,
/// `AXI_INI2_FN_MOD` at offset `0x4_3108`, resets to `0x0000_0004`, read-write.
AxiIni2FnMod = 31,
/// `AXI_INI3_FN_MOD2` at offset `0x4_4024`, resets to `0x0000_0004`, read-write.
AxiIni3FnMod2 = 32,
/// `AXI_INI3_FN_MOD_AHB` at offset `0x4_4028`, resets to `0x0000_0004`, read-write.
AxiIni3FnModAhb = 33,
/// `AXI_INI3_READ_QOS` at offset `0x4_4100`, resets to `0x0000_0004`, read-write.
AxiIni3ReadQos = 34,
/// `AXI_INI3_WRITE_QOS` at offset `0x4_4104`, resets to `0x0000_0004`, read-write.
AxiIni3WriteQos = 35,
/// `AXI_INI3_FN_MOD` at offset `0x4_4108`, resets to `0x0000_0004`, read-write.
AxiIni3FnMod = 36,
/// `AXI_INI4_READ_QOS` at offset `0x4_5100`, resets to `0x0000_0004`, read-write.
AxiIni4ReadQos = 37,
/// `AXI_INI4_WRITE_QOS` at offset `0x4_5104`, resets to `0x0000_0004`, read-write.
AxiIni4WriteQos = 38,
/// `AXI_INI4_FN_MOD` at offset `0x4_5108`, resets to `0x0000_0004`, read-write.
AxiIni4FnMod = 39,
/// `AXI_INI5_READ_QOS` at offset `0x4_6100`, resets to `0x0000_0004`, read-write.
AxiIni5ReadQos = 40,
/// `AXI_INI5_WRITE_QOS` at offset `0x4_6104`, resets to `0x0000_0004`, read-write.
AxiIni5WriteQos = 41,
/// `AXI_INI5_FN_MOD` at offset `0x4_6108`, resets to `0x0000_0004`, read-write.
AxiIni5FnMod = 42,
/// `AXI_INI6_READ_QOS` at offset `0x4_7100`, resets to `0x0000_0004`, read-write.
AxiIni6ReadQos = 43,
/// `AXI_INI6_WRITE_QOS` at offset `0x4_7104`, resets to `0x0000_0004`, read-write.
AxiIni6WriteQos = 44,
/// `AXI_INI6_FN_MOD` at offset `0x4_7108`, resets to `0x0000_0004`, read-write.
AxiIni6FnMod = 45,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 46] = [Self::AxiPeriphId4, Self::AxiPeriphId0, Self::AxiPeriphId1, Self::AxiPeriphId2, Self::AxiPeriphId3, Self::AxiCompId0, Self::AxiCompId1, Self::AxiCompId2, Self::AxiCompId3, Self::AxiTarg1FnModIssBm, Self::AxiTarg1FnMod2, Self::AxiTarg1FnModLb, Self::AxiTarg1FnMod, Self::AxiTarg2FnModIssBm, Self::AxiTarg2FnMod2, Self::AxiTarg2FnModLb, Self::AxiTarg2FnMod, Self::AxiTarg3FnModIssBm, Self::AxiTarg4FnModIssBm, Self::AxiTarg5FnModIssBm, Self::AxiTarg6FnModIssBm, Self::AxiTarg7FnModIssBm, Self::AxiTarg7FnMod2, Self::AxiTarg7FnMod, Self::AxiIni1FnMod2, Self::AxiIni1FnModAhb, Self::AxiIni1ReadQos, Self::AxiIni1WriteQos, Self::AxiIni1FnMod, Self::AxiIni2ReadQos, Self::AxiIni2WriteQos, Self::AxiIni2FnMod, Self::AxiIni3FnMod2, Self::AxiIni3FnModAhb, Self::AxiIni3ReadQos, Self::AxiIni3WriteQos, Self::AxiIni3FnMod, Self::AxiIni4ReadQos, Self::AxiIni4WriteQos, Self::AxiIni4FnMod, Self::AxiIni5ReadQos, Self::AxiIni5WriteQos, Self::AxiIni5FnMod, Self::AxiIni6ReadQos, Self::AxiIni6WriteQos, Self::AxiIni6FnMod];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `AXI_PERIPH_ID_4`.
pub mod axi_periph_id_4 {
use super::FieldSpec;
/// `JEP106CON`, bits 0..=3.
pub const JEP106CON: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `KCOUNT4`, bits 4..=7.
pub const KCOUNT4: &FieldSpec = &super::REGISTERS[0].fields[1];
}
/// The fields of `AXI_PERIPH_ID_0`.
pub mod axi_periph_id_0 {
use super::FieldSpec;
/// `PARTNUM`, bits 0..=7.
pub const PARTNUM: &FieldSpec = &super::REGISTERS[1].fields[0];
}
/// The fields of `AXI_PERIPH_ID_1`.
pub mod axi_periph_id_1 {
use super::FieldSpec;
/// `PARTNUM`, bits 0..=3.
pub const PARTNUM: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `JEP106I`, bits 4..=7.
pub const JEP106I: &FieldSpec = &super::REGISTERS[2].fields[1];
}
/// The fields of `AXI_PERIPH_ID_2`.
pub mod axi_periph_id_2 {
use super::FieldSpec;
/// `JEP106ID`, bits 0..=2.
pub const JEP106ID: &FieldSpec = &super::REGISTERS[3].fields[0];
/// `JEDEC`, bit 3.
pub const JEDEC: &FieldSpec = &super::REGISTERS[3].fields[1];
/// `REVISION`, bits 4..=7.
pub const REVISION: &FieldSpec = &super::REGISTERS[3].fields[2];
}
/// The fields of `AXI_PERIPH_ID_3`.
pub mod axi_periph_id_3 {
use super::FieldSpec;
/// `CUST_MOD_NUM`, bits 0..=3.
pub const CUST_MOD_NUM: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `REV_AND`, bits 4..=7.
pub const REV_AND: &FieldSpec = &super::REGISTERS[4].fields[1];
}
/// The fields of `AXI_COMP_ID_0`.
pub mod axi_comp_id_0 {
use super::FieldSpec;
/// `PREAMBLE`, bits 0..=7.
pub const PREAMBLE: &FieldSpec = &super::REGISTERS[5].fields[0];
}
/// The fields of `AXI_COMP_ID_1`.
pub mod axi_comp_id_1 {
use super::FieldSpec;
/// `PREAMBLE`, bits 0..=3.
pub const PREAMBLE: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `CLASS`, bits 4..=7.
pub const CLASS: &FieldSpec = &super::REGISTERS[6].fields[1];
}
/// The fields of `AXI_COMP_ID_2`.
pub mod axi_comp_id_2 {
use super::FieldSpec;
/// `PREAMBLE`, bits 0..=7.
pub const PREAMBLE: &FieldSpec = &super::REGISTERS[7].fields[0];
}
/// The fields of `AXI_COMP_ID_3`.
pub mod axi_comp_id_3 {
use super::FieldSpec;
/// `PREAMBLE`, bits 0..=7.
pub const PREAMBLE: &FieldSpec = &super::REGISTERS[8].fields[0];
}
/// The fields of `AXI_TARG1_FN_MOD_ISS_BM`.
pub mod axi_targ1_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[9].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[9].fields[1];
}
/// The fields of `AXI_TARG1_FN_MOD2`.
pub mod axi_targ1_fn_mod2 {
use super::FieldSpec;
/// `BYPASS_MERGE`, bit 0.
pub const BYPASS_MERGE: &FieldSpec = &super::REGISTERS[10].fields[0];
}
/// The fields of `AXI_TARG1_FN_MOD_LB`.
pub mod axi_targ1_fn_mod_lb {
use super::FieldSpec;
/// `FN_MOD_LB`, bit 0.
pub const FN_MOD_LB: &FieldSpec = &super::REGISTERS[11].fields[0];
}
/// The fields of `AXI_TARG1_FN_MOD`.
pub mod axi_targ1_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[12].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[12].fields[1];
}
/// The fields of `AXI_TARG2_FN_MOD_ISS_BM`.
pub mod axi_targ2_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[13].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[13].fields[1];
}
/// The fields of `AXI_TARG2_FN_MOD2`.
pub mod axi_targ2_fn_mod2 {
use super::FieldSpec;
/// `BYPASS_MERGE`, bit 0.
pub const BYPASS_MERGE: &FieldSpec = &super::REGISTERS[14].fields[0];
}
/// The fields of `AXI_TARG2_FN_MOD_LB`.
pub mod axi_targ2_fn_mod_lb {
use super::FieldSpec;
/// `FN_MOD_LB`, bit 0.
pub const FN_MOD_LB: &FieldSpec = &super::REGISTERS[15].fields[0];
}
/// The fields of `AXI_TARG2_FN_MOD`.
pub mod axi_targ2_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[16].fields[1];
}
/// The fields of `AXI_TARG3_FN_MOD_ISS_BM`.
pub mod axi_targ3_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[17].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[17].fields[1];
}
/// The fields of `AXI_TARG4_FN_MOD_ISS_BM`.
pub mod axi_targ4_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[18].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[18].fields[1];
}
/// The fields of `AXI_TARG5_FN_MOD_ISS_BM`.
pub mod axi_targ5_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[19].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[19].fields[1];
}
/// The fields of `AXI_TARG6_FN_MOD_ISS_BM`.
pub mod axi_targ6_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[20].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[20].fields[1];
}
/// The fields of `AXI_TARG7_FN_MOD_ISS_BM`.
pub mod axi_targ7_fn_mod_iss_bm {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[21].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[21].fields[1];
}
/// The fields of `AXI_TARG7_FN_MOD2`.
pub mod axi_targ7_fn_mod2 {
use super::FieldSpec;
/// `BYPASS_MERGE`, bit 0.
pub const BYPASS_MERGE: &FieldSpec = &super::REGISTERS[22].fields[0];
}
/// The fields of `AXI_TARG7_FN_MOD`.
pub mod axi_targ7_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[23].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[23].fields[1];
}
/// The fields of `AXI_INI1_FN_MOD2`.
pub mod axi_ini1_fn_mod2 {
use super::FieldSpec;
/// `BYPASS_MERGE`, bit 0.
pub const BYPASS_MERGE: &FieldSpec = &super::REGISTERS[24].fields[0];
}
/// The fields of `AXI_INI1_FN_MOD_AHB`.
pub mod axi_ini1_fn_mod_ahb {
use super::FieldSpec;
/// `RD_INC_OVERRIDE`, bit 0.
pub const RD_INC_OVERRIDE: &FieldSpec = &super::REGISTERS[25].fields[0];
/// `WR_INC_OVERRIDE`, bit 1.
pub const WR_INC_OVERRIDE: &FieldSpec = &super::REGISTERS[25].fields[1];
}
/// The fields of `AXI_INI1_READ_QOS`.
pub mod axi_ini1_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[26].fields[0];
}
/// The fields of `AXI_INI1_WRITE_QOS`.
pub mod axi_ini1_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[27].fields[0];
}
/// The fields of `AXI_INI1_FN_MOD`.
pub mod axi_ini1_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[28].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[28].fields[1];
}
/// The fields of `AXI_INI2_READ_QOS`.
pub mod axi_ini2_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `AXI_INI2_WRITE_QOS`.
pub mod axi_ini2_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[30].fields[0];
}
/// The fields of `AXI_INI2_FN_MOD`.
pub mod axi_ini2_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[31].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[31].fields[1];
}
/// The fields of `AXI_INI3_FN_MOD2`.
pub mod axi_ini3_fn_mod2 {
use super::FieldSpec;
/// `BYPASS_MERGE`, bit 0.
pub const BYPASS_MERGE: &FieldSpec = &super::REGISTERS[32].fields[0];
}
/// The fields of `AXI_INI3_FN_MOD_AHB`.
pub mod axi_ini3_fn_mod_ahb {
use super::FieldSpec;
/// `RD_INC_OVERRIDE`, bit 0.
pub const RD_INC_OVERRIDE: &FieldSpec = &super::REGISTERS[33].fields[0];
/// `WR_INC_OVERRIDE`, bit 1.
pub const WR_INC_OVERRIDE: &FieldSpec = &super::REGISTERS[33].fields[1];
}
/// The fields of `AXI_INI3_READ_QOS`.
pub mod axi_ini3_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `AXI_INI3_WRITE_QOS`.
pub mod axi_ini3_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[35].fields[0];
}
/// The fields of `AXI_INI3_FN_MOD`.
pub mod axi_ini3_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[36].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[36].fields[1];
}
/// The fields of `AXI_INI4_READ_QOS`.
pub mod axi_ini4_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[37].fields[0];
}
/// The fields of `AXI_INI4_WRITE_QOS`.
pub mod axi_ini4_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[38].fields[0];
}
/// The fields of `AXI_INI4_FN_MOD`.
pub mod axi_ini4_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[39].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[39].fields[1];
}
/// The fields of `AXI_INI5_READ_QOS`.
pub mod axi_ini5_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[40].fields[0];
}
/// The fields of `AXI_INI5_WRITE_QOS`.
pub mod axi_ini5_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[41].fields[0];
}
/// The fields of `AXI_INI5_FN_MOD`.
pub mod axi_ini5_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[42].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[42].fields[1];
}
/// The fields of `AXI_INI6_READ_QOS`.
pub mod axi_ini6_read_qos {
use super::FieldSpec;
/// `AR_QOS`, bits 0..=3.
pub const AR_QOS: &FieldSpec = &super::REGISTERS[43].fields[0];
}
/// The fields of `AXI_INI6_WRITE_QOS`.
pub mod axi_ini6_write_qos {
use super::FieldSpec;
/// `AW_QOS`, bits 0..=3.
pub const AW_QOS: &FieldSpec = &super::REGISTERS[44].fields[0];
}
/// The fields of `AXI_INI6_FN_MOD`.
pub mod axi_ini6_fn_mod {
use super::FieldSpec;
/// `READ_ISS_OVERRIDE`, bit 0.
pub const READ_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[45].fields[0];
/// `WRITE_ISS_OVERRIDE`, bit 1.
pub const WRITE_ISS_OVERRIDE: &FieldSpec = &super::REGISTERS[45].fields[1];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 46] = [
RegisterSpec { name: "AXI_PERIPH_ID_4", offset: 0x1FD0, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "JEP106CON", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "KCOUNT4", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_PERIPH_ID_0", offset: 0x1FE0, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PARTNUM", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_PERIPH_ID_1", offset: 0x1FE4, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PARTNUM", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JEP106I", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_PERIPH_ID_2", offset: 0x1FE8, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "JEP106ID", bit: 0, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JEDEC", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "REVISION", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_PERIPH_ID_3", offset: 0x1FEC, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CUST_MOD_NUM", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "REV_AND", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_COMP_ID_0", offset: 0x1FF0, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PREAMBLE", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_COMP_ID_1", offset: 0x1FF4, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PREAMBLE", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CLASS", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_COMP_ID_2", offset: 0x1FF8, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PREAMBLE", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_COMP_ID_3", offset: 0x1FFC, width: Width::W32, reset: 0x0000_0004, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PREAMBLE", bit: 0, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG1_FN_MOD_ISS_BM", offset: 0x2008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG1_FN_MOD2", offset: 0x2024, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BYPASS_MERGE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG1_FN_MOD_LB", offset: 0x202C, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FN_MOD_LB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG1_FN_MOD", offset: 0x2108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG2_FN_MOD_ISS_BM", offset: 0x3008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG2_FN_MOD2", offset: 0x3024, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BYPASS_MERGE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG2_FN_MOD_LB", offset: 0x302C, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FN_MOD_LB", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG2_FN_MOD", offset: 0x3108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG3_FN_MOD_ISS_BM", offset: 0x4008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG4_FN_MOD_ISS_BM", offset: 0x5008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG5_FN_MOD_ISS_BM", offset: 0x6008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG6_FN_MOD_ISS_BM", offset: 0x7008, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG7_FN_MOD_ISS_BM", offset: 0x800C, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG7_FN_MOD2", offset: 0x8024, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BYPASS_MERGE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_TARG7_FN_MOD", offset: 0x8108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI1_FN_MOD2", offset: 0x4_2024, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BYPASS_MERGE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI1_FN_MOD_AHB", offset: 0x4_2028, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RD_INC_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WR_INC_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI1_READ_QOS", offset: 0x4_2100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI1_WRITE_QOS", offset: 0x4_2104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI1_FN_MOD", offset: 0x4_2108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI2_READ_QOS", offset: 0x4_3100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI2_WRITE_QOS", offset: 0x4_3104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI2_FN_MOD", offset: 0x4_3108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI3_FN_MOD2", offset: 0x4_4024, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BYPASS_MERGE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI3_FN_MOD_AHB", offset: 0x4_4028, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RD_INC_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WR_INC_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI3_READ_QOS", offset: 0x4_4100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI3_WRITE_QOS", offset: 0x4_4104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI3_FN_MOD", offset: 0x4_4108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI4_READ_QOS", offset: 0x4_5100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI4_WRITE_QOS", offset: 0x4_5104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI4_FN_MOD", offset: 0x4_5108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI5_READ_QOS", offset: 0x4_6100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI5_WRITE_QOS", offset: 0x4_6104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI5_FN_MOD", offset: 0x4_6108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI6_READ_QOS", offset: 0x4_7100, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AR_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI6_WRITE_QOS", offset: 0x4_7104, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "AW_QOS", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AXI_INI6_FN_MOD", offset: 0x4_7108, width: Width::W32, reset: 0x0000_0004, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "READ_ISS_OVERRIDE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WRITE_ISS_OVERRIDE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
];