// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `RCC` and the instances derived from it.
use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};
/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
/// `CR` at offset `0x0`, resets to `0x0000_0083`, read-write.
Cr = 0,
/// `HSICFGR` at offset `0x4`, resets to `0x4000_0000`, read-write.
Hsicfgr = 1,
/// `ICSCR` at offset `0x4`, resets to `0x4000_0000`, read-write.
Icscr = 2,
/// `CRRCR` at offset `0x8`, resets to `0x0000_0000`, read-only.
Crrcr = 3,
/// `CFGR` at offset `0x10`, resets to `0x0000_0000`, read-write.
Cfgr = 4,
/// `D1CFGR` at offset `0x18`, resets to `0x0000_0000`, read-write.
D1cfgr = 5,
/// `D2CFGR` at offset `0x1C`, resets to `0x0000_0000`, read-write.
D2cfgr = 6,
/// `D3CFGR` at offset `0x20`, resets to `0x0000_0000`, read-write.
D3cfgr = 7,
/// `PLLCKSELR` at offset `0x28`, resets to `0x0202_0200`, read-write.
Pllckselr = 8,
/// `PLLCFGR` at offset `0x2C`, resets to `0x01FF_0000`, read-write.
Pllcfgr = 9,
/// `PLL1DIVR` at offset `0x30`, resets to `0x0101_0280`, read-write.
Pll1divr = 10,
/// `PLL1FRACR` at offset `0x34`, resets to `0x0000_0000`, read-write.
Pll1fracr = 11,
/// `PLL2DIVR` at offset `0x38`, resets to `0x0101_0280`, read-write.
Pll2divr = 12,
/// `PLL2FRACR` at offset `0x3C`, resets to `0x0000_0000`, read-write.
Pll2fracr = 13,
/// `PLL3DIVR` at offset `0x40`, resets to `0x0101_0280`, read-write.
Pll3divr = 14,
/// `PLL3FRACR` at offset `0x44`, resets to `0x0000_0000`, read-write.
Pll3fracr = 15,
/// `D1CCIPR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
D1ccipr = 16,
/// `D2CCIP1R` at offset `0x50`, resets to `0x0000_0000`, read-write.
D2ccip1r = 17,
/// `D2CCIP2R` at offset `0x54`, resets to `0x0000_0000`, read-write.
D2ccip2r = 18,
/// `D3CCIPR` at offset `0x58`, resets to `0x0000_0000`, read-write.
D3ccipr = 19,
/// `CIER` at offset `0x60`, resets to `0x0000_0000`, read-write.
Cier = 20,
/// `CIFR` at offset `0x64`, resets to `0x0000_0000`, read-write.
Cifr = 21,
/// `CICR` at offset `0x68`, resets to `0x0000_0000`, read-write.
Cicr = 22,
/// `BDCR` at offset `0x70`, resets to `0x0000_0000`, read-write.
Bdcr = 23,
/// `CSR` at offset `0x74`, resets to `0x0000_0000`, read-write.
Csr = 24,
/// `AHB3RSTR` at offset `0x7C`, resets to `0x0000_0000`, read-write.
Ahb3rstr = 25,
/// `AHB1RSTR` at offset `0x80`, resets to `0x0000_0000`, read-write.
Ahb1rstr = 26,
/// `AHB2RSTR` at offset `0x84`, resets to `0x0000_0000`, read-write.
Ahb2rstr = 27,
/// `AHB4RSTR` at offset `0x88`, resets to `0x0000_0000`, read-write.
Ahb4rstr = 28,
/// `APB3RSTR` at offset `0x8C`, resets to `0x0000_0000`, read-write.
Apb3rstr = 29,
/// `APB1LRSTR` at offset `0x90`, resets to `0x0000_0000`, read-write.
Apb1lrstr = 30,
/// `APB1HRSTR` at offset `0x94`, resets to `0x0000_0000`, read-write.
Apb1hrstr = 31,
/// `APB2RSTR` at offset `0x98`, resets to `0x0000_0000`, read-write.
Apb2rstr = 32,
/// `APB4RSTR` at offset `0x9C`, resets to `0x0000_0000`, read-write.
Apb4rstr = 33,
/// `GCR` at offset `0xA0`, resets to `0x0000_0000`, read-write.
Gcr = 34,
/// `D3AMR` at offset `0xA8`, resets to `0x0000_0000`, read-write.
D3amr = 35,
/// `RSR` at offset `0xD0`, resets to `0x0000_0000`, read-write.
Rsr = 36,
/// `AHB3ENR` at offset `0xD4`, resets to `0x0000_0000`, read-write.
Ahb3enr = 37,
/// `AHB1ENR` at offset `0xD8`, resets to `0x0000_0000`, read-write.
Ahb1enr = 38,
/// `AHB2ENR` at offset `0xDC`, resets to `0x0000_0000`, read-write.
Ahb2enr = 39,
/// `AHB4ENR` at offset `0xE0`, resets to `0x0000_0000`, read-write.
Ahb4enr = 40,
/// `APB3ENR` at offset `0xE4`, resets to `0x0000_0000`, read-write.
Apb3enr = 41,
/// `APB1LENR` at offset `0xE8`, resets to `0x0000_0000`, read-write.
Apb1lenr = 42,
/// `APB1HENR` at offset `0xEC`, resets to `0x0000_0000`, read-write.
Apb1henr = 43,
/// `APB2ENR` at offset `0xF0`, resets to `0x0000_0000`, read-write.
Apb2enr = 44,
/// `APB4ENR` at offset `0xF4`, resets to `0x0000_0000`, read-write.
Apb4enr = 45,
/// `AHB3LPENR` at offset `0xFC`, resets to `0x0000_0000`, read-write.
Ahb3lpenr = 46,
/// `AHB1LPENR` at offset `0x100`, resets to `0x0000_0000`, read-write.
Ahb1lpenr = 47,
/// `AHB2LPENR` at offset `0x104`, resets to `0x0000_0000`, read-write.
Ahb2lpenr = 48,
/// `AHB4LPENR` at offset `0x108`, resets to `0x0000_0000`, read-write.
Ahb4lpenr = 49,
/// `APB3LPENR` at offset `0x10C`, resets to `0x0000_0000`, read-write.
Apb3lpenr = 50,
/// `APB1LLPENR` at offset `0x110`, resets to `0x0000_0000`, read-write.
Apb1llpenr = 51,
/// `APB1HLPENR` at offset `0x114`, resets to `0x0000_0000`, read-write.
Apb1hlpenr = 52,
/// `APB2LPENR` at offset `0x118`, resets to `0x0000_0000`, read-write.
Apb2lpenr = 53,
/// `APB4LPENR` at offset `0x11C`, resets to `0x0000_0000`, read-write.
Apb4lpenr = 54,
/// `C1_RSR` at offset `0x130`, resets to `0x0000_0000`, read-write.
C1Rsr = 55,
/// `C1_AHB3ENR` at offset `0x134`, resets to `0x0000_0000`, read-write.
C1Ahb3enr = 56,
/// `C1_AHB1ENR` at offset `0x138`, resets to `0x0000_0000`, read-write.
C1Ahb1enr = 57,
/// `C1_AHB2ENR` at offset `0x13C`, resets to `0x0000_0000`, read-write.
C1Ahb2enr = 58,
/// `C1_AHB4ENR` at offset `0x140`, resets to `0x0000_0000`, read-write.
C1Ahb4enr = 59,
/// `C1_APB3ENR` at offset `0x144`, resets to `0x0000_0000`, read-write.
C1Apb3enr = 60,
/// `C1_APB1LENR` at offset `0x148`, resets to `0x0000_0000`, read-write.
C1Apb1lenr = 61,
/// `C1_APB1HENR` at offset `0x14C`, resets to `0x0000_0000`, read-write.
C1Apb1henr = 62,
/// `C1_APB2ENR` at offset `0x150`, resets to `0x0000_0000`, read-write.
C1Apb2enr = 63,
/// `C1_APB4ENR` at offset `0x154`, resets to `0x0000_0000`, read-write.
C1Apb4enr = 64,
/// `C1_AHB3LPENR` at offset `0x15C`, resets to `0x0000_0000`, read-write.
C1Ahb3lpenr = 65,
/// `C1_AHB1LPENR` at offset `0x160`, resets to `0x0000_0000`, read-write.
C1Ahb1lpenr = 66,
/// `C1_AHB2LPENR` at offset `0x164`, resets to `0x0000_0000`, read-write.
C1Ahb2lpenr = 67,
/// `C1_AHB4LPENR` at offset `0x168`, resets to `0x0000_0000`, read-write.
C1Ahb4lpenr = 68,
/// `C1_APB3LPENR` at offset `0x16C`, resets to `0x0000_0000`, read-write.
C1Apb3lpenr = 69,
/// `C1_APB1LLPENR` at offset `0x170`, resets to `0x0000_0000`, read-write.
C1Apb1llpenr = 70,
/// `C1_APB1HLPENR` at offset `0x174`, resets to `0x0000_0000`, read-write.
C1Apb1hlpenr = 71,
/// `C1_APB2LPENR` at offset `0x178`, resets to `0x0000_0000`, read-write.
C1Apb2lpenr = 72,
/// `C1_APB4LPENR` at offset `0x17C`, resets to `0x0000_0000`, read-write.
C1Apb4lpenr = 73,
}
impl Register {
/// Every register, in table order.
pub const ALL: [Self; 74] = [Self::Cr, Self::Hsicfgr, Self::Icscr, Self::Crrcr, Self::Cfgr, Self::D1cfgr, Self::D2cfgr, Self::D3cfgr, Self::Pllckselr, Self::Pllcfgr, Self::Pll1divr, Self::Pll1fracr, Self::Pll2divr, Self::Pll2fracr, Self::Pll3divr, Self::Pll3fracr, Self::D1ccipr, Self::D2ccip1r, Self::D2ccip2r, Self::D3ccipr, Self::Cier, Self::Cifr, Self::Cicr, Self::Bdcr, Self::Csr, Self::Ahb3rstr, Self::Ahb1rstr, Self::Ahb2rstr, Self::Ahb4rstr, Self::Apb3rstr, Self::Apb1lrstr, Self::Apb1hrstr, Self::Apb2rstr, Self::Apb4rstr, Self::Gcr, Self::D3amr, Self::Rsr, Self::Ahb3enr, Self::Ahb1enr, Self::Ahb2enr, Self::Ahb4enr, Self::Apb3enr, Self::Apb1lenr, Self::Apb1henr, Self::Apb2enr, Self::Apb4enr, Self::Ahb3lpenr, Self::Ahb1lpenr, Self::Ahb2lpenr, Self::Ahb4lpenr, Self::Apb3lpenr, Self::Apb1llpenr, Self::Apb1hlpenr, Self::Apb2lpenr, Self::Apb4lpenr, Self::C1Rsr, Self::C1Ahb3enr, Self::C1Ahb1enr, Self::C1Ahb2enr, Self::C1Ahb4enr, Self::C1Apb3enr, Self::C1Apb1lenr, Self::C1Apb1henr, Self::C1Apb2enr, Self::C1Apb4enr, Self::C1Ahb3lpenr, Self::C1Ahb1lpenr, Self::C1Ahb2lpenr, Self::C1Ahb4lpenr, Self::C1Apb3lpenr, Self::C1Apb1llpenr, Self::C1Apb1hlpenr, Self::C1Apb2lpenr, Self::C1Apb4lpenr];
}
impl Layout for Register {
const REGISTERS: &'static [RegisterSpec] = ®ISTERS;
fn from_index(index: usize) -> Option<Self> {
Self::ALL.get(index).copied()
}
fn index(self) -> usize {
self as usize
}
}
/// The fields of `CR`.
pub mod cr {
use super::FieldSpec;
/// `HSION`, bit 0.
pub const HSION: &FieldSpec = &super::REGISTERS[0].fields[0];
/// `HSIKERON`, bit 1.
pub const HSIKERON: &FieldSpec = &super::REGISTERS[0].fields[1];
/// `HSIRDY`, bit 2.
pub const HSIRDY: &FieldSpec = &super::REGISTERS[0].fields[2];
/// `HSIDIV`, bits 3..=4.
pub const HSIDIV: &FieldSpec = &super::REGISTERS[0].fields[3];
/// `HSIDIVF`, bit 5.
pub const HSIDIVF: &FieldSpec = &super::REGISTERS[0].fields[4];
/// `CSION`, bit 7.
pub const CSION: &FieldSpec = &super::REGISTERS[0].fields[5];
/// `CSIRDY`, bit 8.
pub const CSIRDY: &FieldSpec = &super::REGISTERS[0].fields[6];
/// `CSIKERON`, bit 9.
pub const CSIKERON: &FieldSpec = &super::REGISTERS[0].fields[7];
/// `RC48ON`, bit 12.
pub const RC48ON: &FieldSpec = &super::REGISTERS[0].fields[8];
/// `RC48RDY`, bit 13.
pub const RC48RDY: &FieldSpec = &super::REGISTERS[0].fields[9];
/// `D1CKRDY`, bit 14.
pub const D1CKRDY: &FieldSpec = &super::REGISTERS[0].fields[10];
/// `D2CKRDY`, bit 15.
pub const D2CKRDY: &FieldSpec = &super::REGISTERS[0].fields[11];
/// `HSEON`, bit 16.
pub const HSEON: &FieldSpec = &super::REGISTERS[0].fields[12];
/// `HSERDY`, bit 17.
pub const HSERDY: &FieldSpec = &super::REGISTERS[0].fields[13];
/// `HSEBYP`, bit 18.
pub const HSEBYP: &FieldSpec = &super::REGISTERS[0].fields[14];
/// `HSECSSON`, bit 19.
pub const HSECSSON: &FieldSpec = &super::REGISTERS[0].fields[15];
/// `PLL1ON`, bit 24.
pub const PLL1ON: &FieldSpec = &super::REGISTERS[0].fields[16];
/// `PLL1RDY`, bit 25.
pub const PLL1RDY: &FieldSpec = &super::REGISTERS[0].fields[17];
/// `PLL2ON`, bit 26.
pub const PLL2ON: &FieldSpec = &super::REGISTERS[0].fields[18];
/// `PLL2RDY`, bit 27.
pub const PLL2RDY: &FieldSpec = &super::REGISTERS[0].fields[19];
/// `PLL3ON`, bit 28.
pub const PLL3ON: &FieldSpec = &super::REGISTERS[0].fields[20];
/// `PLL3RDY`, bit 29.
pub const PLL3RDY: &FieldSpec = &super::REGISTERS[0].fields[21];
}
/// The fields of `HSICFGR`.
pub mod hsicfgr {
use super::FieldSpec;
/// `HSICAL`, bits 0..=11, read-only.
pub const HSICAL: &FieldSpec = &super::REGISTERS[1].fields[0];
/// `HSITRIM`, bits 24..=30.
pub const HSITRIM: &FieldSpec = &super::REGISTERS[1].fields[1];
}
/// The fields of `ICSCR`.
pub mod icscr {
use super::FieldSpec;
/// `HSICAL`, bits 0..=11, read-only.
pub const HSICAL: &FieldSpec = &super::REGISTERS[2].fields[0];
/// `HSITRIM`, bits 12..=17.
pub const HSITRIM: &FieldSpec = &super::REGISTERS[2].fields[1];
/// `CSICAL`, bits 18..=25, read-only.
pub const CSICAL: &FieldSpec = &super::REGISTERS[2].fields[2];
/// `CSITRIM`, bits 26..=30.
pub const CSITRIM: &FieldSpec = &super::REGISTERS[2].fields[3];
}
/// The fields of `CRRCR`.
pub mod crrcr {
use super::FieldSpec;
/// `RC48CAL`, bits 0..=9.
pub const RC48CAL: &FieldSpec = &super::REGISTERS[3].fields[0];
}
/// The fields of `CFGR`.
pub mod cfgr {
use super::FieldSpec;
/// `SW`, bits 0..=2.
pub const SW: &FieldSpec = &super::REGISTERS[4].fields[0];
/// `SWS`, bits 3..=5.
pub const SWS: &FieldSpec = &super::REGISTERS[4].fields[1];
/// `STOPWUCK`, bit 6.
pub const STOPWUCK: &FieldSpec = &super::REGISTERS[4].fields[2];
/// `STOPKERWUCK`, bit 7.
pub const STOPKERWUCK: &FieldSpec = &super::REGISTERS[4].fields[3];
/// `RTCPRE`, bits 8..=13.
pub const RTCPRE: &FieldSpec = &super::REGISTERS[4].fields[4];
/// `HRTIMSEL`, bit 14.
pub const HRTIMSEL: &FieldSpec = &super::REGISTERS[4].fields[5];
/// `TIMPRE`, bit 15.
pub const TIMPRE: &FieldSpec = &super::REGISTERS[4].fields[6];
/// `MCO1PRE`, bits 18..=21.
pub const MCO1PRE: &FieldSpec = &super::REGISTERS[4].fields[7];
/// `MCO1SEL`, bits 22..=24.
pub const MCO1SEL: &FieldSpec = &super::REGISTERS[4].fields[8];
/// `MCO2PRE`, bits 25..=28.
pub const MCO2PRE: &FieldSpec = &super::REGISTERS[4].fields[9];
/// `MCO2SEL`, bits 29..=31.
pub const MCO2SEL: &FieldSpec = &super::REGISTERS[4].fields[10];
}
/// The fields of `D1CFGR`.
pub mod d1cfgr {
use super::FieldSpec;
/// `HPRE`, bits 0..=3.
pub const HPRE: &FieldSpec = &super::REGISTERS[5].fields[0];
/// `D1PPRE`, bits 4..=6.
pub const D1PPRE: &FieldSpec = &super::REGISTERS[5].fields[1];
/// `D1CPRE`, bits 8..=11.
pub const D1CPRE: &FieldSpec = &super::REGISTERS[5].fields[2];
}
/// The fields of `D2CFGR`.
pub mod d2cfgr {
use super::FieldSpec;
/// `D2PPRE1`, bits 4..=6.
pub const D2PPRE1: &FieldSpec = &super::REGISTERS[6].fields[0];
/// `D2PPRE2`, bits 8..=10.
pub const D2PPRE2: &FieldSpec = &super::REGISTERS[6].fields[1];
}
/// The fields of `D3CFGR`.
pub mod d3cfgr {
use super::FieldSpec;
/// `D3PPRE`, bits 4..=6.
pub const D3PPRE: &FieldSpec = &super::REGISTERS[7].fields[0];
}
/// The fields of `PLLCKSELR`.
pub mod pllckselr {
use super::FieldSpec;
/// `PLLSRC`, bits 0..=1.
pub const PLLSRC: &FieldSpec = &super::REGISTERS[8].fields[0];
/// `DIVM1`, bits 4..=9.
pub const DIVM1: &FieldSpec = &super::REGISTERS[8].fields[1];
/// `DIVM2`, bits 12..=17.
pub const DIVM2: &FieldSpec = &super::REGISTERS[8].fields[2];
/// `DIVM3`, bits 20..=25.
pub const DIVM3: &FieldSpec = &super::REGISTERS[8].fields[3];
}
/// The fields of `PLLCFGR`.
pub mod pllcfgr {
use super::FieldSpec;
/// `PLL1FRACEN`, bit 0.
pub const PLL1FRACEN: &FieldSpec = &super::REGISTERS[9].fields[0];
/// `PLL1VCOSEL`, bit 1.
pub const PLL1VCOSEL: &FieldSpec = &super::REGISTERS[9].fields[1];
/// `PLL1RGE`, bits 2..=3.
pub const PLL1RGE: &FieldSpec = &super::REGISTERS[9].fields[2];
/// `PLL2FRACEN`, bit 4.
pub const PLL2FRACEN: &FieldSpec = &super::REGISTERS[9].fields[3];
/// `PLL2VCOSEL`, bit 5.
pub const PLL2VCOSEL: &FieldSpec = &super::REGISTERS[9].fields[4];
/// `PLL2RGE`, bits 6..=7.
pub const PLL2RGE: &FieldSpec = &super::REGISTERS[9].fields[5];
/// `PLL3FRACEN`, bit 8.
pub const PLL3FRACEN: &FieldSpec = &super::REGISTERS[9].fields[6];
/// `PLL3VCOSEL`, bit 9.
pub const PLL3VCOSEL: &FieldSpec = &super::REGISTERS[9].fields[7];
/// `PLL3RGE`, bits 10..=11.
pub const PLL3RGE: &FieldSpec = &super::REGISTERS[9].fields[8];
/// `DIVP1EN`, bit 16.
pub const DIVP1EN: &FieldSpec = &super::REGISTERS[9].fields[9];
/// `DIVQ1EN`, bit 17.
pub const DIVQ1EN: &FieldSpec = &super::REGISTERS[9].fields[10];
/// `DIVR1EN`, bit 18.
pub const DIVR1EN: &FieldSpec = &super::REGISTERS[9].fields[11];
/// `DIVP2EN`, bit 19.
pub const DIVP2EN: &FieldSpec = &super::REGISTERS[9].fields[12];
/// `DIVQ2EN`, bit 20.
pub const DIVQ2EN: &FieldSpec = &super::REGISTERS[9].fields[13];
/// `DIVR2EN`, bit 21.
pub const DIVR2EN: &FieldSpec = &super::REGISTERS[9].fields[14];
/// `DIVP3EN`, bit 22.
pub const DIVP3EN: &FieldSpec = &super::REGISTERS[9].fields[15];
/// `DIVQ3EN`, bit 23.
pub const DIVQ3EN: &FieldSpec = &super::REGISTERS[9].fields[16];
/// `DIVR3EN`, bit 24.
pub const DIVR3EN: &FieldSpec = &super::REGISTERS[9].fields[17];
}
/// The fields of `PLL1DIVR`.
pub mod pll1divr {
use super::FieldSpec;
/// `DIVN1`, bits 0..=8.
pub const DIVN1: &FieldSpec = &super::REGISTERS[10].fields[0];
/// `DIVP1`, bits 9..=15.
pub const DIVP1: &FieldSpec = &super::REGISTERS[10].fields[1];
/// `DIVQ1`, bits 16..=22.
pub const DIVQ1: &FieldSpec = &super::REGISTERS[10].fields[2];
/// `DIVR1`, bits 24..=30.
pub const DIVR1: &FieldSpec = &super::REGISTERS[10].fields[3];
}
/// The fields of `PLL1FRACR`.
pub mod pll1fracr {
use super::FieldSpec;
/// `FRACN1`, bits 3..=15.
pub const FRACN1: &FieldSpec = &super::REGISTERS[11].fields[0];
}
/// The fields of `PLL2DIVR`.
pub mod pll2divr {
use super::FieldSpec;
/// `DIVN2`, bits 0..=8.
pub const DIVN2: &FieldSpec = &super::REGISTERS[12].fields[0];
/// `DIVP2`, bits 9..=15.
pub const DIVP2: &FieldSpec = &super::REGISTERS[12].fields[1];
/// `DIVQ2`, bits 16..=22.
pub const DIVQ2: &FieldSpec = &super::REGISTERS[12].fields[2];
/// `DIVR2`, bits 24..=30.
pub const DIVR2: &FieldSpec = &super::REGISTERS[12].fields[3];
}
/// The fields of `PLL2FRACR`.
pub mod pll2fracr {
use super::FieldSpec;
/// `FRACN2`, bits 3..=15.
pub const FRACN2: &FieldSpec = &super::REGISTERS[13].fields[0];
}
/// The fields of `PLL3DIVR`.
pub mod pll3divr {
use super::FieldSpec;
/// `DIVN3`, bits 0..=8.
pub const DIVN3: &FieldSpec = &super::REGISTERS[14].fields[0];
/// `DIVP3`, bits 9..=15.
pub const DIVP3: &FieldSpec = &super::REGISTERS[14].fields[1];
/// `DIVQ3`, bits 16..=22.
pub const DIVQ3: &FieldSpec = &super::REGISTERS[14].fields[2];
/// `DIVR3`, bits 24..=30.
pub const DIVR3: &FieldSpec = &super::REGISTERS[14].fields[3];
}
/// The fields of `PLL3FRACR`.
pub mod pll3fracr {
use super::FieldSpec;
/// `FRACN3`, bits 3..=15.
pub const FRACN3: &FieldSpec = &super::REGISTERS[15].fields[0];
}
/// The fields of `D1CCIPR`.
pub mod d1ccipr {
use super::FieldSpec;
/// `FMCSEL`, bits 0..=1.
pub const FMCSEL: &FieldSpec = &super::REGISTERS[16].fields[0];
/// `QSPISEL`, bits 4..=5.
pub const QSPISEL: &FieldSpec = &super::REGISTERS[16].fields[1];
/// `SDMMCSEL`, bit 16.
pub const SDMMCSEL: &FieldSpec = &super::REGISTERS[16].fields[2];
/// `CKPERSEL`, bits 28..=29.
pub const CKPERSEL: &FieldSpec = &super::REGISTERS[16].fields[3];
}
/// The fields of `D2CCIP1R`.
pub mod d2ccip1r {
use super::FieldSpec;
/// `SAI1SEL`, bits 0..=2.
pub const SAI1SEL: &FieldSpec = &super::REGISTERS[17].fields[0];
/// `SAI23SEL`, bits 6..=8.
pub const SAI23SEL: &FieldSpec = &super::REGISTERS[17].fields[1];
/// `SPI123SEL`, bits 12..=14.
pub const SPI123SEL: &FieldSpec = &super::REGISTERS[17].fields[2];
/// `SPI45SEL`, bits 16..=18.
pub const SPI45SEL: &FieldSpec = &super::REGISTERS[17].fields[3];
/// `SPDIFSEL`, bits 20..=21.
pub const SPDIFSEL: &FieldSpec = &super::REGISTERS[17].fields[4];
/// `DFSDM1SEL`, bit 24.
pub const DFSDM1SEL: &FieldSpec = &super::REGISTERS[17].fields[5];
/// `FDCANSEL`, bits 28..=29.
pub const FDCANSEL: &FieldSpec = &super::REGISTERS[17].fields[6];
/// `SWPSEL`, bit 31.
pub const SWPSEL: &FieldSpec = &super::REGISTERS[17].fields[7];
}
/// The fields of `D2CCIP2R`.
pub mod d2ccip2r {
use super::FieldSpec;
/// `USART234578SEL`, bits 0..=2.
pub const USART234578SEL: &FieldSpec = &super::REGISTERS[18].fields[0];
/// `USART16SEL`, bits 3..=5.
pub const USART16SEL: &FieldSpec = &super::REGISTERS[18].fields[1];
/// `RNGSEL`, bits 8..=9.
pub const RNGSEL: &FieldSpec = &super::REGISTERS[18].fields[2];
/// `I2C123SEL`, bits 12..=13.
pub const I2C123SEL: &FieldSpec = &super::REGISTERS[18].fields[3];
/// `USBSEL`, bits 20..=21.
pub const USBSEL: &FieldSpec = &super::REGISTERS[18].fields[4];
/// `CECSEL`, bits 22..=23.
pub const CECSEL: &FieldSpec = &super::REGISTERS[18].fields[5];
/// `LPTIM1SEL`, bits 28..=30.
pub const LPTIM1SEL: &FieldSpec = &super::REGISTERS[18].fields[6];
}
/// The fields of `D3CCIPR`.
pub mod d3ccipr {
use super::FieldSpec;
/// `LPUART1SEL`, bits 0..=2.
pub const LPUART1SEL: &FieldSpec = &super::REGISTERS[19].fields[0];
/// `I2C4SEL`, bits 8..=9.
pub const I2C4SEL: &FieldSpec = &super::REGISTERS[19].fields[1];
/// `LPTIM2SEL`, bits 10..=12.
pub const LPTIM2SEL: &FieldSpec = &super::REGISTERS[19].fields[2];
/// `LPTIM345SEL`, bits 13..=15.
pub const LPTIM345SEL: &FieldSpec = &super::REGISTERS[19].fields[3];
/// `ADCSEL`, bits 16..=17.
pub const ADCSEL: &FieldSpec = &super::REGISTERS[19].fields[4];
/// `SAI4ASEL`, bits 21..=23.
pub const SAI4ASEL: &FieldSpec = &super::REGISTERS[19].fields[5];
/// `SAI4BSEL`, bits 24..=26.
pub const SAI4BSEL: &FieldSpec = &super::REGISTERS[19].fields[6];
/// `SPI6SEL`, bits 28..=30.
pub const SPI6SEL: &FieldSpec = &super::REGISTERS[19].fields[7];
}
/// The fields of `CIER`.
pub mod cier {
use super::FieldSpec;
/// `LSIRDYIE`, bit 0.
pub const LSIRDYIE: &FieldSpec = &super::REGISTERS[20].fields[0];
/// `LSERDYIE`, bit 1.
pub const LSERDYIE: &FieldSpec = &super::REGISTERS[20].fields[1];
/// `HSIRDYIE`, bit 2.
pub const HSIRDYIE: &FieldSpec = &super::REGISTERS[20].fields[2];
/// `HSERDYIE`, bit 3.
pub const HSERDYIE: &FieldSpec = &super::REGISTERS[20].fields[3];
/// `CSIRDYIE`, bit 4.
pub const CSIRDYIE: &FieldSpec = &super::REGISTERS[20].fields[4];
/// `RC48RDYIE`, bit 5.
pub const RC48RDYIE: &FieldSpec = &super::REGISTERS[20].fields[5];
/// `PLL1RDYIE`, bit 6.
pub const PLL1RDYIE: &FieldSpec = &super::REGISTERS[20].fields[6];
/// `PLL2RDYIE`, bit 7.
pub const PLL2RDYIE: &FieldSpec = &super::REGISTERS[20].fields[7];
/// `PLL3RDYIE`, bit 8.
pub const PLL3RDYIE: &FieldSpec = &super::REGISTERS[20].fields[8];
/// `LSECSSIE`, bit 9.
pub const LSECSSIE: &FieldSpec = &super::REGISTERS[20].fields[9];
}
/// The fields of `CIFR`.
pub mod cifr {
use super::FieldSpec;
/// `LSIRDYF`, bit 0.
pub const LSIRDYF: &FieldSpec = &super::REGISTERS[21].fields[0];
/// `LSERDYF`, bit 1.
pub const LSERDYF: &FieldSpec = &super::REGISTERS[21].fields[1];
/// `HSIRDYF`, bit 2.
pub const HSIRDYF: &FieldSpec = &super::REGISTERS[21].fields[2];
/// `HSERDYF`, bit 3.
pub const HSERDYF: &FieldSpec = &super::REGISTERS[21].fields[3];
/// `CSIRDY`, bit 4.
pub const CSIRDY: &FieldSpec = &super::REGISTERS[21].fields[4];
/// `RC48RDYF`, bit 5.
pub const RC48RDYF: &FieldSpec = &super::REGISTERS[21].fields[5];
/// `PLL1RDYF`, bit 6.
pub const PLL1RDYF: &FieldSpec = &super::REGISTERS[21].fields[6];
/// `PLL2RDYF`, bit 7.
pub const PLL2RDYF: &FieldSpec = &super::REGISTERS[21].fields[7];
/// `PLL3RDYF`, bit 8.
pub const PLL3RDYF: &FieldSpec = &super::REGISTERS[21].fields[8];
/// `LSECSSF`, bit 9.
pub const LSECSSF: &FieldSpec = &super::REGISTERS[21].fields[9];
/// `HSECSSF`, bit 10.
pub const HSECSSF: &FieldSpec = &super::REGISTERS[21].fields[10];
}
/// The fields of `CICR`.
pub mod cicr {
use super::FieldSpec;
/// `LSIRDYC`, bit 0.
pub const LSIRDYC: &FieldSpec = &super::REGISTERS[22].fields[0];
/// `LSERDYC`, bit 1.
pub const LSERDYC: &FieldSpec = &super::REGISTERS[22].fields[1];
/// `HSIRDYC`, bit 2.
pub const HSIRDYC: &FieldSpec = &super::REGISTERS[22].fields[2];
/// `HSERDYC`, bit 3.
pub const HSERDYC: &FieldSpec = &super::REGISTERS[22].fields[3];
/// `HSE_ready_Interrupt_Clear`, bit 4.
pub const HSE_READY_INTERRUPT_CLEAR: &FieldSpec = &super::REGISTERS[22].fields[4];
/// `RC48RDYC`, bit 5.
pub const RC48RDYC: &FieldSpec = &super::REGISTERS[22].fields[5];
/// `PLL1RDYC`, bit 6.
pub const PLL1RDYC: &FieldSpec = &super::REGISTERS[22].fields[6];
/// `PLL2RDYC`, bit 7.
pub const PLL2RDYC: &FieldSpec = &super::REGISTERS[22].fields[7];
/// `PLL3RDYC`, bit 8.
pub const PLL3RDYC: &FieldSpec = &super::REGISTERS[22].fields[8];
/// `LSECSSC`, bit 9.
pub const LSECSSC: &FieldSpec = &super::REGISTERS[22].fields[9];
/// `HSECSSC`, bit 10.
pub const HSECSSC: &FieldSpec = &super::REGISTERS[22].fields[10];
}
/// The fields of `BDCR`.
pub mod bdcr {
use super::FieldSpec;
/// `LSEON`, bit 0.
pub const LSEON: &FieldSpec = &super::REGISTERS[23].fields[0];
/// `LSERDY`, bit 1.
pub const LSERDY: &FieldSpec = &super::REGISTERS[23].fields[1];
/// `LSEBYP`, bit 2.
pub const LSEBYP: &FieldSpec = &super::REGISTERS[23].fields[2];
/// `LSEDRV`, bits 3..=4.
pub const LSEDRV: &FieldSpec = &super::REGISTERS[23].fields[3];
/// `LSECSSON`, bit 5.
pub const LSECSSON: &FieldSpec = &super::REGISTERS[23].fields[4];
/// `LSECSSD`, bit 6.
pub const LSECSSD: &FieldSpec = &super::REGISTERS[23].fields[5];
/// `RTCSRC`, bits 8..=9.
pub const RTCSRC: &FieldSpec = &super::REGISTERS[23].fields[6];
/// `RTCEN`, bit 15.
pub const RTCEN: &FieldSpec = &super::REGISTERS[23].fields[7];
/// `VSWRST`, bit 16.
pub const VSWRST: &FieldSpec = &super::REGISTERS[23].fields[8];
}
/// The fields of `CSR`.
pub mod csr {
use super::FieldSpec;
/// `LSION`, bit 0.
pub const LSION: &FieldSpec = &super::REGISTERS[24].fields[0];
/// `LSIRDY`, bit 1.
pub const LSIRDY: &FieldSpec = &super::REGISTERS[24].fields[1];
}
/// The fields of `AHB3RSTR`.
pub mod ahb3rstr {
use super::FieldSpec;
/// `MDMARST`, bit 0.
pub const MDMARST: &FieldSpec = &super::REGISTERS[25].fields[0];
/// `DMA2DRST`, bit 4.
pub const DMA2DRST: &FieldSpec = &super::REGISTERS[25].fields[1];
/// `JPGDECRST`, bit 5.
pub const JPGDECRST: &FieldSpec = &super::REGISTERS[25].fields[2];
/// `FMCRST`, bit 12.
pub const FMCRST: &FieldSpec = &super::REGISTERS[25].fields[3];
/// `QSPIRST`, bit 14.
pub const QSPIRST: &FieldSpec = &super::REGISTERS[25].fields[4];
/// `SDMMC1RST`, bit 16.
pub const SDMMC1RST: &FieldSpec = &super::REGISTERS[25].fields[5];
/// `CPURST`, bit 31.
pub const CPURST: &FieldSpec = &super::REGISTERS[25].fields[6];
}
/// The fields of `AHB1RSTR`.
pub mod ahb1rstr {
use super::FieldSpec;
/// `DMA1RST`, bit 0.
pub const DMA1RST: &FieldSpec = &super::REGISTERS[26].fields[0];
/// `DMA2RST`, bit 1.
pub const DMA2RST: &FieldSpec = &super::REGISTERS[26].fields[1];
/// `ADC12RST`, bit 5.
pub const ADC12RST: &FieldSpec = &super::REGISTERS[26].fields[2];
/// `ETH1MACRST`, bit 15.
pub const ETH1MACRST: &FieldSpec = &super::REGISTERS[26].fields[3];
/// `USB1OTGRST`, bit 25.
pub const USB1OTGRST: &FieldSpec = &super::REGISTERS[26].fields[4];
/// `USB2OTGRST`, bit 27.
pub const USB2OTGRST: &FieldSpec = &super::REGISTERS[26].fields[5];
}
/// The fields of `AHB2RSTR`.
pub mod ahb2rstr {
use super::FieldSpec;
/// `CAMITFRST`, bit 0.
pub const CAMITFRST: &FieldSpec = &super::REGISTERS[27].fields[0];
/// `CRYPTRST`, bit 4.
pub const CRYPTRST: &FieldSpec = &super::REGISTERS[27].fields[1];
/// `HASHRST`, bit 5.
pub const HASHRST: &FieldSpec = &super::REGISTERS[27].fields[2];
/// `RNGRST`, bit 6.
pub const RNGRST: &FieldSpec = &super::REGISTERS[27].fields[3];
/// `SDMMC2RST`, bit 9.
pub const SDMMC2RST: &FieldSpec = &super::REGISTERS[27].fields[4];
}
/// The fields of `AHB4RSTR`.
pub mod ahb4rstr {
use super::FieldSpec;
/// `GPIOARST`, bit 0.
pub const GPIOARST: &FieldSpec = &super::REGISTERS[28].fields[0];
/// `GPIOBRST`, bit 1.
pub const GPIOBRST: &FieldSpec = &super::REGISTERS[28].fields[1];
/// `GPIOCRST`, bit 2.
pub const GPIOCRST: &FieldSpec = &super::REGISTERS[28].fields[2];
/// `GPIODRST`, bit 3.
pub const GPIODRST: &FieldSpec = &super::REGISTERS[28].fields[3];
/// `GPIOERST`, bit 4.
pub const GPIOERST: &FieldSpec = &super::REGISTERS[28].fields[4];
/// `GPIOFRST`, bit 5.
pub const GPIOFRST: &FieldSpec = &super::REGISTERS[28].fields[5];
/// `GPIOGRST`, bit 6.
pub const GPIOGRST: &FieldSpec = &super::REGISTERS[28].fields[6];
/// `GPIOHRST`, bit 7.
pub const GPIOHRST: &FieldSpec = &super::REGISTERS[28].fields[7];
/// `GPIOIRST`, bit 8.
pub const GPIOIRST: &FieldSpec = &super::REGISTERS[28].fields[8];
/// `GPIOJRST`, bit 9.
pub const GPIOJRST: &FieldSpec = &super::REGISTERS[28].fields[9];
/// `GPIOKRST`, bit 10.
pub const GPIOKRST: &FieldSpec = &super::REGISTERS[28].fields[10];
/// `CRCRST`, bit 19.
pub const CRCRST: &FieldSpec = &super::REGISTERS[28].fields[11];
/// `BDMARST`, bit 21.
pub const BDMARST: &FieldSpec = &super::REGISTERS[28].fields[12];
/// `ADC3RST`, bit 24.
pub const ADC3RST: &FieldSpec = &super::REGISTERS[28].fields[13];
/// `HSEMRST`, bit 25.
pub const HSEMRST: &FieldSpec = &super::REGISTERS[28].fields[14];
}
/// The fields of `APB3RSTR`.
pub mod apb3rstr {
use super::FieldSpec;
/// `LTDCRST`, bit 3.
pub const LTDCRST: &FieldSpec = &super::REGISTERS[29].fields[0];
}
/// The fields of `APB1LRSTR`.
pub mod apb1lrstr {
use super::FieldSpec;
/// `TIM2RST`, bit 0.
pub const TIM2RST: &FieldSpec = &super::REGISTERS[30].fields[0];
/// `TIM3RST`, bit 1.
pub const TIM3RST: &FieldSpec = &super::REGISTERS[30].fields[1];
/// `TIM4RST`, bit 2.
pub const TIM4RST: &FieldSpec = &super::REGISTERS[30].fields[2];
/// `TIM5RST`, bit 3.
pub const TIM5RST: &FieldSpec = &super::REGISTERS[30].fields[3];
/// `TIM6RST`, bit 4.
pub const TIM6RST: &FieldSpec = &super::REGISTERS[30].fields[4];
/// `TIM7RST`, bit 5.
pub const TIM7RST: &FieldSpec = &super::REGISTERS[30].fields[5];
/// `TIM12RST`, bit 6.
pub const TIM12RST: &FieldSpec = &super::REGISTERS[30].fields[6];
/// `TIM13RST`, bit 7.
pub const TIM13RST: &FieldSpec = &super::REGISTERS[30].fields[7];
/// `TIM14RST`, bit 8.
pub const TIM14RST: &FieldSpec = &super::REGISTERS[30].fields[8];
/// `LPTIM1RST`, bit 9.
pub const LPTIM1RST: &FieldSpec = &super::REGISTERS[30].fields[9];
/// `SPI2RST`, bit 14.
pub const SPI2RST: &FieldSpec = &super::REGISTERS[30].fields[10];
/// `SPI3RST`, bit 15.
pub const SPI3RST: &FieldSpec = &super::REGISTERS[30].fields[11];
/// `SPDIFRXRST`, bit 16.
pub const SPDIFRXRST: &FieldSpec = &super::REGISTERS[30].fields[12];
/// `USART2RST`, bit 17.
pub const USART2RST: &FieldSpec = &super::REGISTERS[30].fields[13];
/// `USART3RST`, bit 18.
pub const USART3RST: &FieldSpec = &super::REGISTERS[30].fields[14];
/// `UART4RST`, bit 19.
pub const UART4RST: &FieldSpec = &super::REGISTERS[30].fields[15];
/// `UART5RST`, bit 20.
pub const UART5RST: &FieldSpec = &super::REGISTERS[30].fields[16];
/// `I2C1RST`, bit 21.
pub const I2C1RST: &FieldSpec = &super::REGISTERS[30].fields[17];
/// `I2C2RST`, bit 22.
pub const I2C2RST: &FieldSpec = &super::REGISTERS[30].fields[18];
/// `I2C3RST`, bit 23.
pub const I2C3RST: &FieldSpec = &super::REGISTERS[30].fields[19];
/// `CECRST`, bit 27.
pub const CECRST: &FieldSpec = &super::REGISTERS[30].fields[20];
/// `DAC12RST`, bit 29.
pub const DAC12RST: &FieldSpec = &super::REGISTERS[30].fields[21];
/// `USART7RST`, bit 30.
pub const USART7RST: &FieldSpec = &super::REGISTERS[30].fields[22];
/// `USART8RST`, bit 31.
pub const USART8RST: &FieldSpec = &super::REGISTERS[30].fields[23];
}
/// The fields of `APB1HRSTR`.
pub mod apb1hrstr {
use super::FieldSpec;
/// `CRSRST`, bit 1.
pub const CRSRST: &FieldSpec = &super::REGISTERS[31].fields[0];
/// `SWPRST`, bit 2.
pub const SWPRST: &FieldSpec = &super::REGISTERS[31].fields[1];
/// `OPAMPRST`, bit 4.
pub const OPAMPRST: &FieldSpec = &super::REGISTERS[31].fields[2];
/// `MDIOSRST`, bit 5.
pub const MDIOSRST: &FieldSpec = &super::REGISTERS[31].fields[3];
/// `FDCANRST`, bit 8.
pub const FDCANRST: &FieldSpec = &super::REGISTERS[31].fields[4];
}
/// The fields of `APB2RSTR`.
pub mod apb2rstr {
use super::FieldSpec;
/// `TIM1RST`, bit 0.
pub const TIM1RST: &FieldSpec = &super::REGISTERS[32].fields[0];
/// `TIM8RST`, bit 1.
pub const TIM8RST: &FieldSpec = &super::REGISTERS[32].fields[1];
/// `USART1RST`, bit 4.
pub const USART1RST: &FieldSpec = &super::REGISTERS[32].fields[2];
/// `USART6RST`, bit 5.
pub const USART6RST: &FieldSpec = &super::REGISTERS[32].fields[3];
/// `SPI1RST`, bit 12.
pub const SPI1RST: &FieldSpec = &super::REGISTERS[32].fields[4];
/// `SPI4RST`, bit 13.
pub const SPI4RST: &FieldSpec = &super::REGISTERS[32].fields[5];
/// `TIM15RST`, bit 16.
pub const TIM15RST: &FieldSpec = &super::REGISTERS[32].fields[6];
/// `TIM16RST`, bit 17.
pub const TIM16RST: &FieldSpec = &super::REGISTERS[32].fields[7];
/// `TIM17RST`, bit 18.
pub const TIM17RST: &FieldSpec = &super::REGISTERS[32].fields[8];
/// `SPI5RST`, bit 20.
pub const SPI5RST: &FieldSpec = &super::REGISTERS[32].fields[9];
/// `SAI1RST`, bit 22.
pub const SAI1RST: &FieldSpec = &super::REGISTERS[32].fields[10];
/// `SAI2RST`, bit 23.
pub const SAI2RST: &FieldSpec = &super::REGISTERS[32].fields[11];
/// `SAI3RST`, bit 24.
pub const SAI3RST: &FieldSpec = &super::REGISTERS[32].fields[12];
/// `DFSDM1RST`, bit 28.
pub const DFSDM1RST: &FieldSpec = &super::REGISTERS[32].fields[13];
/// `HRTIMRST`, bit 29.
pub const HRTIMRST: &FieldSpec = &super::REGISTERS[32].fields[14];
}
/// The fields of `APB4RSTR`.
pub mod apb4rstr {
use super::FieldSpec;
/// `SYSCFGRST`, bit 1.
pub const SYSCFGRST: &FieldSpec = &super::REGISTERS[33].fields[0];
/// `LPUART1RST`, bit 3.
pub const LPUART1RST: &FieldSpec = &super::REGISTERS[33].fields[1];
/// `SPI6RST`, bit 5.
pub const SPI6RST: &FieldSpec = &super::REGISTERS[33].fields[2];
/// `I2C4RST`, bit 7.
pub const I2C4RST: &FieldSpec = &super::REGISTERS[33].fields[3];
/// `LPTIM2RST`, bit 9.
pub const LPTIM2RST: &FieldSpec = &super::REGISTERS[33].fields[4];
/// `LPTIM3RST`, bit 10.
pub const LPTIM3RST: &FieldSpec = &super::REGISTERS[33].fields[5];
/// `LPTIM4RST`, bit 11.
pub const LPTIM4RST: &FieldSpec = &super::REGISTERS[33].fields[6];
/// `LPTIM5RST`, bit 12.
pub const LPTIM5RST: &FieldSpec = &super::REGISTERS[33].fields[7];
/// `COMP12RST`, bit 14.
pub const COMP12RST: &FieldSpec = &super::REGISTERS[33].fields[8];
/// `VREFRST`, bit 15.
pub const VREFRST: &FieldSpec = &super::REGISTERS[33].fields[9];
/// `SAI4RST`, bit 21.
pub const SAI4RST: &FieldSpec = &super::REGISTERS[33].fields[10];
}
/// The fields of `GCR`.
pub mod gcr {
use super::FieldSpec;
/// `WW1RSC`, bit 0.
pub const WW1RSC: &FieldSpec = &super::REGISTERS[34].fields[0];
}
/// The fields of `D3AMR`.
pub mod d3amr {
use super::FieldSpec;
/// `BDMAAMEN`, bit 0.
pub const BDMAAMEN: &FieldSpec = &super::REGISTERS[35].fields[0];
/// `LPUART1AMEN`, bit 3.
pub const LPUART1AMEN: &FieldSpec = &super::REGISTERS[35].fields[1];
/// `SPI6AMEN`, bit 5.
pub const SPI6AMEN: &FieldSpec = &super::REGISTERS[35].fields[2];
/// `I2C4AMEN`, bit 7.
pub const I2C4AMEN: &FieldSpec = &super::REGISTERS[35].fields[3];
/// `LPTIM2AMEN`, bit 9.
pub const LPTIM2AMEN: &FieldSpec = &super::REGISTERS[35].fields[4];
/// `LPTIM3AMEN`, bit 10.
pub const LPTIM3AMEN: &FieldSpec = &super::REGISTERS[35].fields[5];
/// `LPTIM4AMEN`, bit 11.
pub const LPTIM4AMEN: &FieldSpec = &super::REGISTERS[35].fields[6];
/// `LPTIM5AMEN`, bit 12.
pub const LPTIM5AMEN: &FieldSpec = &super::REGISTERS[35].fields[7];
/// `COMP12AMEN`, bit 14.
pub const COMP12AMEN: &FieldSpec = &super::REGISTERS[35].fields[8];
/// `VREFAMEN`, bit 15.
pub const VREFAMEN: &FieldSpec = &super::REGISTERS[35].fields[9];
/// `RTCAMEN`, bit 16.
pub const RTCAMEN: &FieldSpec = &super::REGISTERS[35].fields[10];
/// `CRCAMEN`, bit 19.
pub const CRCAMEN: &FieldSpec = &super::REGISTERS[35].fields[11];
/// `SAI4AMEN`, bit 21.
pub const SAI4AMEN: &FieldSpec = &super::REGISTERS[35].fields[12];
/// `ADC3AMEN`, bit 24.
pub const ADC3AMEN: &FieldSpec = &super::REGISTERS[35].fields[13];
/// `BKPRAMAMEN`, bit 28.
pub const BKPRAMAMEN: &FieldSpec = &super::REGISTERS[35].fields[14];
/// `SRAM4AMEN`, bit 29.
pub const SRAM4AMEN: &FieldSpec = &super::REGISTERS[35].fields[15];
}
/// The fields of `RSR`.
pub mod rsr {
use super::FieldSpec;
/// `RMVF`, bit 16.
pub const RMVF: &FieldSpec = &super::REGISTERS[36].fields[0];
/// `CPURSTF`, bit 17.
pub const CPURSTF: &FieldSpec = &super::REGISTERS[36].fields[1];
/// `D1RSTF`, bit 19.
pub const D1RSTF: &FieldSpec = &super::REGISTERS[36].fields[2];
/// `D2RSTF`, bit 20.
pub const D2RSTF: &FieldSpec = &super::REGISTERS[36].fields[3];
/// `BORRSTF`, bit 21.
pub const BORRSTF: &FieldSpec = &super::REGISTERS[36].fields[4];
/// `PINRSTF`, bit 22.
pub const PINRSTF: &FieldSpec = &super::REGISTERS[36].fields[5];
/// `PORRSTF`, bit 23.
pub const PORRSTF: &FieldSpec = &super::REGISTERS[36].fields[6];
/// `SFTRSTF`, bit 24.
pub const SFTRSTF: &FieldSpec = &super::REGISTERS[36].fields[7];
/// `IWDG1RSTF`, bit 26.
pub const IWDG1RSTF: &FieldSpec = &super::REGISTERS[36].fields[8];
/// `WWDG1RSTF`, bit 28.
pub const WWDG1RSTF: &FieldSpec = &super::REGISTERS[36].fields[9];
/// `LPWRRSTF`, bit 30.
pub const LPWRRSTF: &FieldSpec = &super::REGISTERS[36].fields[10];
}
/// The fields of `AHB3ENR`.
pub mod ahb3enr {
use super::FieldSpec;
/// `MDMAEN`, bit 0.
pub const MDMAEN: &FieldSpec = &super::REGISTERS[37].fields[0];
/// `DMA2DEN`, bit 4.
pub const DMA2DEN: &FieldSpec = &super::REGISTERS[37].fields[1];
/// `JPGDECEN`, bit 5.
pub const JPGDECEN: &FieldSpec = &super::REGISTERS[37].fields[2];
/// `FMCEN`, bit 12.
pub const FMCEN: &FieldSpec = &super::REGISTERS[37].fields[3];
/// `QSPIEN`, bit 14.
pub const QSPIEN: &FieldSpec = &super::REGISTERS[37].fields[4];
/// `SDMMC1EN`, bit 16.
pub const SDMMC1EN: &FieldSpec = &super::REGISTERS[37].fields[5];
}
/// The fields of `AHB1ENR`.
pub mod ahb1enr {
use super::FieldSpec;
/// `DMA1EN`, bit 0.
pub const DMA1EN: &FieldSpec = &super::REGISTERS[38].fields[0];
/// `DMA2EN`, bit 1.
pub const DMA2EN: &FieldSpec = &super::REGISTERS[38].fields[1];
/// `ADC12EN`, bit 5.
pub const ADC12EN: &FieldSpec = &super::REGISTERS[38].fields[2];
/// `ETH1MACEN`, bit 15.
pub const ETH1MACEN: &FieldSpec = &super::REGISTERS[38].fields[3];
/// `ETH1TXEN`, bit 16.
pub const ETH1TXEN: &FieldSpec = &super::REGISTERS[38].fields[4];
/// `ETH1RXEN`, bit 17.
pub const ETH1RXEN: &FieldSpec = &super::REGISTERS[38].fields[5];
/// `USB1OTGHSEN`, bit 25.
pub const USB1OTGHSEN: &FieldSpec = &super::REGISTERS[38].fields[6];
/// `USB1OTGHSULPIEN`, bit 26.
pub const USB1OTGHSULPIEN: &FieldSpec = &super::REGISTERS[38].fields[7];
/// `USB2OTGHSEN`, bit 27.
pub const USB2OTGHSEN: &FieldSpec = &super::REGISTERS[38].fields[8];
/// `USB2OTGHSULPIEN`, bit 28.
pub const USB2OTGHSULPIEN: &FieldSpec = &super::REGISTERS[38].fields[9];
}
/// The fields of `AHB2ENR`.
pub mod ahb2enr {
use super::FieldSpec;
/// `DCMIEN`, bit 0.
pub const DCMIEN: &FieldSpec = &super::REGISTERS[39].fields[0];
/// `CRYPTEN`, bit 4.
pub const CRYPTEN: &FieldSpec = &super::REGISTERS[39].fields[1];
/// `HASHEN`, bit 5.
pub const HASHEN: &FieldSpec = &super::REGISTERS[39].fields[2];
/// `RNGEN`, bit 6.
pub const RNGEN: &FieldSpec = &super::REGISTERS[39].fields[3];
/// `SDMMC2EN`, bit 9.
pub const SDMMC2EN: &FieldSpec = &super::REGISTERS[39].fields[4];
/// `SRAM1EN`, bit 29.
pub const SRAM1EN: &FieldSpec = &super::REGISTERS[39].fields[5];
/// `SRAM2EN`, bit 30.
pub const SRAM2EN: &FieldSpec = &super::REGISTERS[39].fields[6];
/// `SRAM3EN`, bit 31.
pub const SRAM3EN: &FieldSpec = &super::REGISTERS[39].fields[7];
}
/// The fields of `AHB4ENR`.
pub mod ahb4enr {
use super::FieldSpec;
/// `GPIOAEN`, bit 0.
pub const GPIOAEN: &FieldSpec = &super::REGISTERS[40].fields[0];
/// `GPIOBEN`, bit 1.
pub const GPIOBEN: &FieldSpec = &super::REGISTERS[40].fields[1];
/// `GPIOCEN`, bit 2.
pub const GPIOCEN: &FieldSpec = &super::REGISTERS[40].fields[2];
/// `GPIODEN`, bit 3.
pub const GPIODEN: &FieldSpec = &super::REGISTERS[40].fields[3];
/// `GPIOEEN`, bit 4.
pub const GPIOEEN: &FieldSpec = &super::REGISTERS[40].fields[4];
/// `GPIOFEN`, bit 5.
pub const GPIOFEN: &FieldSpec = &super::REGISTERS[40].fields[5];
/// `GPIOGEN`, bit 6.
pub const GPIOGEN: &FieldSpec = &super::REGISTERS[40].fields[6];
/// `GPIOHEN`, bit 7.
pub const GPIOHEN: &FieldSpec = &super::REGISTERS[40].fields[7];
/// `GPIOIEN`, bit 8.
pub const GPIOIEN: &FieldSpec = &super::REGISTERS[40].fields[8];
/// `GPIOJEN`, bit 9.
pub const GPIOJEN: &FieldSpec = &super::REGISTERS[40].fields[9];
/// `GPIOKEN`, bit 10.
pub const GPIOKEN: &FieldSpec = &super::REGISTERS[40].fields[10];
/// `CRCEN`, bit 19.
pub const CRCEN: &FieldSpec = &super::REGISTERS[40].fields[11];
/// `BDMAEN`, bit 21.
pub const BDMAEN: &FieldSpec = &super::REGISTERS[40].fields[12];
/// `ADC3EN`, bit 24.
pub const ADC3EN: &FieldSpec = &super::REGISTERS[40].fields[13];
/// `HSEMEN`, bit 25.
pub const HSEMEN: &FieldSpec = &super::REGISTERS[40].fields[14];
/// `BKPRAMEN`, bit 28.
pub const BKPRAMEN: &FieldSpec = &super::REGISTERS[40].fields[15];
}
/// The fields of `APB3ENR`.
pub mod apb3enr {
use super::FieldSpec;
/// `LTDCEN`, bit 3.
pub const LTDCEN: &FieldSpec = &super::REGISTERS[41].fields[0];
/// `WWDG1EN`, bit 6.
pub const WWDG1EN: &FieldSpec = &super::REGISTERS[41].fields[1];
}
/// The fields of `APB1LENR`.
pub mod apb1lenr {
use super::FieldSpec;
/// `TIM2EN`, bit 0.
pub const TIM2EN: &FieldSpec = &super::REGISTERS[42].fields[0];
/// `TIM3EN`, bit 1.
pub const TIM3EN: &FieldSpec = &super::REGISTERS[42].fields[1];
/// `TIM4EN`, bit 2.
pub const TIM4EN: &FieldSpec = &super::REGISTERS[42].fields[2];
/// `TIM5EN`, bit 3.
pub const TIM5EN: &FieldSpec = &super::REGISTERS[42].fields[3];
/// `TIM6EN`, bit 4.
pub const TIM6EN: &FieldSpec = &super::REGISTERS[42].fields[4];
/// `TIM7EN`, bit 5.
pub const TIM7EN: &FieldSpec = &super::REGISTERS[42].fields[5];
/// `TIM12EN`, bit 6.
pub const TIM12EN: &FieldSpec = &super::REGISTERS[42].fields[6];
/// `TIM13EN`, bit 7.
pub const TIM13EN: &FieldSpec = &super::REGISTERS[42].fields[7];
/// `TIM14EN`, bit 8.
pub const TIM14EN: &FieldSpec = &super::REGISTERS[42].fields[8];
/// `LPTIM1EN`, bit 9.
pub const LPTIM1EN: &FieldSpec = &super::REGISTERS[42].fields[9];
/// `SPI2EN`, bit 14.
pub const SPI2EN: &FieldSpec = &super::REGISTERS[42].fields[10];
/// `SPI3EN`, bit 15.
pub const SPI3EN: &FieldSpec = &super::REGISTERS[42].fields[11];
/// `SPDIFRXEN`, bit 16.
pub const SPDIFRXEN: &FieldSpec = &super::REGISTERS[42].fields[12];
/// `USART2EN`, bit 17.
pub const USART2EN: &FieldSpec = &super::REGISTERS[42].fields[13];
/// `USART3EN`, bit 18.
pub const USART3EN: &FieldSpec = &super::REGISTERS[42].fields[14];
/// `UART4EN`, bit 19.
pub const UART4EN: &FieldSpec = &super::REGISTERS[42].fields[15];
/// `UART5EN`, bit 20.
pub const UART5EN: &FieldSpec = &super::REGISTERS[42].fields[16];
/// `I2C1EN`, bit 21.
pub const I2C1EN: &FieldSpec = &super::REGISTERS[42].fields[17];
/// `I2C2EN`, bit 22.
pub const I2C2EN: &FieldSpec = &super::REGISTERS[42].fields[18];
/// `I2C3EN`, bit 23.
pub const I2C3EN: &FieldSpec = &super::REGISTERS[42].fields[19];
/// `CECEN`, bit 27.
pub const CECEN: &FieldSpec = &super::REGISTERS[42].fields[20];
/// `DAC12EN`, bit 29.
pub const DAC12EN: &FieldSpec = &super::REGISTERS[42].fields[21];
/// `USART7EN`, bit 30.
pub const USART7EN: &FieldSpec = &super::REGISTERS[42].fields[22];
/// `USART8EN`, bit 31.
pub const USART8EN: &FieldSpec = &super::REGISTERS[42].fields[23];
}
/// The fields of `APB1HENR`.
pub mod apb1henr {
use super::FieldSpec;
/// `CRSEN`, bit 1.
pub const CRSEN: &FieldSpec = &super::REGISTERS[43].fields[0];
/// `SWPEN`, bit 2.
pub const SWPEN: &FieldSpec = &super::REGISTERS[43].fields[1];
/// `OPAMPEN`, bit 4.
pub const OPAMPEN: &FieldSpec = &super::REGISTERS[43].fields[2];
/// `MDIOSEN`, bit 5.
pub const MDIOSEN: &FieldSpec = &super::REGISTERS[43].fields[3];
/// `FDCANEN`, bit 8.
pub const FDCANEN: &FieldSpec = &super::REGISTERS[43].fields[4];
}
/// The fields of `APB2ENR`.
pub mod apb2enr {
use super::FieldSpec;
/// `TIM1EN`, bit 0.
pub const TIM1EN: &FieldSpec = &super::REGISTERS[44].fields[0];
/// `TIM8EN`, bit 1.
pub const TIM8EN: &FieldSpec = &super::REGISTERS[44].fields[1];
/// `USART1EN`, bit 4.
pub const USART1EN: &FieldSpec = &super::REGISTERS[44].fields[2];
/// `USART6EN`, bit 5.
pub const USART6EN: &FieldSpec = &super::REGISTERS[44].fields[3];
/// `SPI1EN`, bit 12.
pub const SPI1EN: &FieldSpec = &super::REGISTERS[44].fields[4];
/// `SPI4EN`, bit 13.
pub const SPI4EN: &FieldSpec = &super::REGISTERS[44].fields[5];
/// `TIM15EN`, bit 16.
pub const TIM15EN: &FieldSpec = &super::REGISTERS[44].fields[6];
/// `TIM16EN`, bit 17.
pub const TIM16EN: &FieldSpec = &super::REGISTERS[44].fields[7];
/// `TIM17EN`, bit 18.
pub const TIM17EN: &FieldSpec = &super::REGISTERS[44].fields[8];
/// `SPI5EN`, bit 20.
pub const SPI5EN: &FieldSpec = &super::REGISTERS[44].fields[9];
/// `SAI1EN`, bit 22.
pub const SAI1EN: &FieldSpec = &super::REGISTERS[44].fields[10];
/// `SAI2EN`, bit 23.
pub const SAI2EN: &FieldSpec = &super::REGISTERS[44].fields[11];
/// `SAI3EN`, bit 24.
pub const SAI3EN: &FieldSpec = &super::REGISTERS[44].fields[12];
/// `DFSDM1EN`, bit 28.
pub const DFSDM1EN: &FieldSpec = &super::REGISTERS[44].fields[13];
/// `HRTIMEN`, bit 29.
pub const HRTIMEN: &FieldSpec = &super::REGISTERS[44].fields[14];
}
/// The fields of `APB4ENR`.
pub mod apb4enr {
use super::FieldSpec;
/// `SYSCFGEN`, bit 1.
pub const SYSCFGEN: &FieldSpec = &super::REGISTERS[45].fields[0];
/// `LPUART1EN`, bit 3.
pub const LPUART1EN: &FieldSpec = &super::REGISTERS[45].fields[1];
/// `SPI6EN`, bit 5.
pub const SPI6EN: &FieldSpec = &super::REGISTERS[45].fields[2];
/// `I2C4EN`, bit 7.
pub const I2C4EN: &FieldSpec = &super::REGISTERS[45].fields[3];
/// `LPTIM2EN`, bit 9.
pub const LPTIM2EN: &FieldSpec = &super::REGISTERS[45].fields[4];
/// `LPTIM3EN`, bit 10.
pub const LPTIM3EN: &FieldSpec = &super::REGISTERS[45].fields[5];
/// `LPTIM4EN`, bit 11.
pub const LPTIM4EN: &FieldSpec = &super::REGISTERS[45].fields[6];
/// `LPTIM5EN`, bit 12.
pub const LPTIM5EN: &FieldSpec = &super::REGISTERS[45].fields[7];
/// `COMP12EN`, bit 14.
pub const COMP12EN: &FieldSpec = &super::REGISTERS[45].fields[8];
/// `VREFEN`, bit 15.
pub const VREFEN: &FieldSpec = &super::REGISTERS[45].fields[9];
/// `RTCAPBEN`, bit 16.
pub const RTCAPBEN: &FieldSpec = &super::REGISTERS[45].fields[10];
/// `SAI4EN`, bit 21.
pub const SAI4EN: &FieldSpec = &super::REGISTERS[45].fields[11];
}
/// The fields of `AHB3LPENR`.
pub mod ahb3lpenr {
use super::FieldSpec;
/// `MDMALPEN`, bit 0.
pub const MDMALPEN: &FieldSpec = &super::REGISTERS[46].fields[0];
/// `DMA2DLPEN`, bit 4.
pub const DMA2DLPEN: &FieldSpec = &super::REGISTERS[46].fields[1];
/// `JPGDECLPEN`, bit 5.
pub const JPGDECLPEN: &FieldSpec = &super::REGISTERS[46].fields[2];
/// `FLASHLPEN`, bit 8.
pub const FLASHLPEN: &FieldSpec = &super::REGISTERS[46].fields[3];
/// `FMCLPEN`, bit 12.
pub const FMCLPEN: &FieldSpec = &super::REGISTERS[46].fields[4];
/// `QSPILPEN`, bit 14.
pub const QSPILPEN: &FieldSpec = &super::REGISTERS[46].fields[5];
/// `SDMMC1LPEN`, bit 16.
pub const SDMMC1LPEN: &FieldSpec = &super::REGISTERS[46].fields[6];
/// `D1DTCM1LPEN`, bit 28.
pub const D1DTCM1LPEN: &FieldSpec = &super::REGISTERS[46].fields[7];
/// `DTCM2LPEN`, bit 29.
pub const DTCM2LPEN: &FieldSpec = &super::REGISTERS[46].fields[8];
/// `ITCMLPEN`, bit 30.
pub const ITCMLPEN: &FieldSpec = &super::REGISTERS[46].fields[9];
/// `AXISRAMLPEN`, bit 31.
pub const AXISRAMLPEN: &FieldSpec = &super::REGISTERS[46].fields[10];
}
/// The fields of `AHB1LPENR`.
pub mod ahb1lpenr {
use super::FieldSpec;
/// `DMA1LPEN`, bit 0.
pub const DMA1LPEN: &FieldSpec = &super::REGISTERS[47].fields[0];
/// `DMA2LPEN`, bit 1.
pub const DMA2LPEN: &FieldSpec = &super::REGISTERS[47].fields[1];
/// `ADC12LPEN`, bit 5.
pub const ADC12LPEN: &FieldSpec = &super::REGISTERS[47].fields[2];
/// `ETH1MACLPEN`, bit 15.
pub const ETH1MACLPEN: &FieldSpec = &super::REGISTERS[47].fields[3];
/// `ETH1TXLPEN`, bit 16.
pub const ETH1TXLPEN: &FieldSpec = &super::REGISTERS[47].fields[4];
/// `ETH1RXLPEN`, bit 17.
pub const ETH1RXLPEN: &FieldSpec = &super::REGISTERS[47].fields[5];
/// `USB1OTGHSLPEN`, bit 25.
pub const USB1OTGHSLPEN: &FieldSpec = &super::REGISTERS[47].fields[6];
/// `USB1OTGHSULPILPEN`, bit 26.
pub const USB1OTGHSULPILPEN: &FieldSpec = &super::REGISTERS[47].fields[7];
/// `USB2OTGHSLPEN`, bit 27.
pub const USB2OTGHSLPEN: &FieldSpec = &super::REGISTERS[47].fields[8];
/// `USB2OTGHSULPILPEN`, bit 28.
pub const USB2OTGHSULPILPEN: &FieldSpec = &super::REGISTERS[47].fields[9];
}
/// The fields of `AHB2LPENR`.
pub mod ahb2lpenr {
use super::FieldSpec;
/// `CAMITFLPEN`, bit 0.
pub const CAMITFLPEN: &FieldSpec = &super::REGISTERS[48].fields[0];
/// `CRYPTLPEN`, bit 4.
pub const CRYPTLPEN: &FieldSpec = &super::REGISTERS[48].fields[1];
/// `HASHLPEN`, bit 5.
pub const HASHLPEN: &FieldSpec = &super::REGISTERS[48].fields[2];
/// `RNGLPEN`, bit 6.
pub const RNGLPEN: &FieldSpec = &super::REGISTERS[48].fields[3];
/// `SDMMC2LPEN`, bit 9.
pub const SDMMC2LPEN: &FieldSpec = &super::REGISTERS[48].fields[4];
/// `SRAM1LPEN`, bit 29.
pub const SRAM1LPEN: &FieldSpec = &super::REGISTERS[48].fields[5];
/// `SRAM2LPEN`, bit 30.
pub const SRAM2LPEN: &FieldSpec = &super::REGISTERS[48].fields[6];
/// `SRAM3LPEN`, bit 31.
pub const SRAM3LPEN: &FieldSpec = &super::REGISTERS[48].fields[7];
}
/// The fields of `AHB4LPENR`.
pub mod ahb4lpenr {
use super::FieldSpec;
/// `GPIOALPEN`, bit 0.
pub const GPIOALPEN: &FieldSpec = &super::REGISTERS[49].fields[0];
/// `GPIOBLPEN`, bit 1.
pub const GPIOBLPEN: &FieldSpec = &super::REGISTERS[49].fields[1];
/// `GPIOCLPEN`, bit 2.
pub const GPIOCLPEN: &FieldSpec = &super::REGISTERS[49].fields[2];
/// `GPIODLPEN`, bit 3.
pub const GPIODLPEN: &FieldSpec = &super::REGISTERS[49].fields[3];
/// `GPIOELPEN`, bit 4.
pub const GPIOELPEN: &FieldSpec = &super::REGISTERS[49].fields[4];
/// `GPIOFLPEN`, bit 5.
pub const GPIOFLPEN: &FieldSpec = &super::REGISTERS[49].fields[5];
/// `GPIOGLPEN`, bit 6.
pub const GPIOGLPEN: &FieldSpec = &super::REGISTERS[49].fields[6];
/// `GPIOHLPEN`, bit 7.
pub const GPIOHLPEN: &FieldSpec = &super::REGISTERS[49].fields[7];
/// `GPIOILPEN`, bit 8.
pub const GPIOILPEN: &FieldSpec = &super::REGISTERS[49].fields[8];
/// `GPIOJLPEN`, bit 9.
pub const GPIOJLPEN: &FieldSpec = &super::REGISTERS[49].fields[9];
/// `GPIOKLPEN`, bit 10.
pub const GPIOKLPEN: &FieldSpec = &super::REGISTERS[49].fields[10];
/// `CRCLPEN`, bit 19.
pub const CRCLPEN: &FieldSpec = &super::REGISTERS[49].fields[11];
/// `BDMALPEN`, bit 21.
pub const BDMALPEN: &FieldSpec = &super::REGISTERS[49].fields[12];
/// `ADC3LPEN`, bit 24.
pub const ADC3LPEN: &FieldSpec = &super::REGISTERS[49].fields[13];
/// `BKPRAMLPEN`, bit 28.
pub const BKPRAMLPEN: &FieldSpec = &super::REGISTERS[49].fields[14];
/// `SRAM4LPEN`, bit 29.
pub const SRAM4LPEN: &FieldSpec = &super::REGISTERS[49].fields[15];
}
/// The fields of `APB3LPENR`.
pub mod apb3lpenr {
use super::FieldSpec;
/// `LTDCLPEN`, bit 3.
pub const LTDCLPEN: &FieldSpec = &super::REGISTERS[50].fields[0];
/// `WWDG1LPEN`, bit 6.
pub const WWDG1LPEN: &FieldSpec = &super::REGISTERS[50].fields[1];
}
/// The fields of `APB1LLPENR`.
pub mod apb1llpenr {
use super::FieldSpec;
/// `TIM2LPEN`, bit 0.
pub const TIM2LPEN: &FieldSpec = &super::REGISTERS[51].fields[0];
/// `TIM3LPEN`, bit 1.
pub const TIM3LPEN: &FieldSpec = &super::REGISTERS[51].fields[1];
/// `TIM4LPEN`, bit 2.
pub const TIM4LPEN: &FieldSpec = &super::REGISTERS[51].fields[2];
/// `TIM5LPEN`, bit 3.
pub const TIM5LPEN: &FieldSpec = &super::REGISTERS[51].fields[3];
/// `TIM6LPEN`, bit 4.
pub const TIM6LPEN: &FieldSpec = &super::REGISTERS[51].fields[4];
/// `TIM7LPEN`, bit 5.
pub const TIM7LPEN: &FieldSpec = &super::REGISTERS[51].fields[5];
/// `TIM12LPEN`, bit 6.
pub const TIM12LPEN: &FieldSpec = &super::REGISTERS[51].fields[6];
/// `TIM13LPEN`, bit 7.
pub const TIM13LPEN: &FieldSpec = &super::REGISTERS[51].fields[7];
/// `TIM14LPEN`, bit 8.
pub const TIM14LPEN: &FieldSpec = &super::REGISTERS[51].fields[8];
/// `LPTIM1LPEN`, bit 9.
pub const LPTIM1LPEN: &FieldSpec = &super::REGISTERS[51].fields[9];
/// `SPI2LPEN`, bit 14.
pub const SPI2LPEN: &FieldSpec = &super::REGISTERS[51].fields[10];
/// `SPI3LPEN`, bit 15.
pub const SPI3LPEN: &FieldSpec = &super::REGISTERS[51].fields[11];
/// `SPDIFRXLPEN`, bit 16.
pub const SPDIFRXLPEN: &FieldSpec = &super::REGISTERS[51].fields[12];
/// `USART2LPEN`, bit 17.
pub const USART2LPEN: &FieldSpec = &super::REGISTERS[51].fields[13];
/// `USART3LPEN`, bit 18.
pub const USART3LPEN: &FieldSpec = &super::REGISTERS[51].fields[14];
/// `UART4LPEN`, bit 19.
pub const UART4LPEN: &FieldSpec = &super::REGISTERS[51].fields[15];
/// `UART5LPEN`, bit 20.
pub const UART5LPEN: &FieldSpec = &super::REGISTERS[51].fields[16];
/// `I2C1LPEN`, bit 21.
pub const I2C1LPEN: &FieldSpec = &super::REGISTERS[51].fields[17];
/// `I2C2LPEN`, bit 22.
pub const I2C2LPEN: &FieldSpec = &super::REGISTERS[51].fields[18];
/// `I2C3LPEN`, bit 23.
pub const I2C3LPEN: &FieldSpec = &super::REGISTERS[51].fields[19];
/// `HDMICECLPEN`, bit 27.
pub const HDMICECLPEN: &FieldSpec = &super::REGISTERS[51].fields[20];
/// `DAC12LPEN`, bit 29.
pub const DAC12LPEN: &FieldSpec = &super::REGISTERS[51].fields[21];
/// `USART7LPEN`, bit 30.
pub const USART7LPEN: &FieldSpec = &super::REGISTERS[51].fields[22];
/// `USART8LPEN`, bit 31.
pub const USART8LPEN: &FieldSpec = &super::REGISTERS[51].fields[23];
}
/// The fields of `APB1HLPENR`.
pub mod apb1hlpenr {
use super::FieldSpec;
/// `CRSLPEN`, bit 1.
pub const CRSLPEN: &FieldSpec = &super::REGISTERS[52].fields[0];
/// `SWPLPEN`, bit 2.
pub const SWPLPEN: &FieldSpec = &super::REGISTERS[52].fields[1];
/// `OPAMPLPEN`, bit 4.
pub const OPAMPLPEN: &FieldSpec = &super::REGISTERS[52].fields[2];
/// `MDIOSLPEN`, bit 5.
pub const MDIOSLPEN: &FieldSpec = &super::REGISTERS[52].fields[3];
/// `FDCANLPEN`, bit 8.
pub const FDCANLPEN: &FieldSpec = &super::REGISTERS[52].fields[4];
}
/// The fields of `APB2LPENR`.
pub mod apb2lpenr {
use super::FieldSpec;
/// `TIM1LPEN`, bit 0.
pub const TIM1LPEN: &FieldSpec = &super::REGISTERS[53].fields[0];
/// `TIM8LPEN`, bit 1.
pub const TIM8LPEN: &FieldSpec = &super::REGISTERS[53].fields[1];
/// `USART1LPEN`, bit 4.
pub const USART1LPEN: &FieldSpec = &super::REGISTERS[53].fields[2];
/// `USART6LPEN`, bit 5.
pub const USART6LPEN: &FieldSpec = &super::REGISTERS[53].fields[3];
/// `SPI1LPEN`, bit 12.
pub const SPI1LPEN: &FieldSpec = &super::REGISTERS[53].fields[4];
/// `SPI4LPEN`, bit 13.
pub const SPI4LPEN: &FieldSpec = &super::REGISTERS[53].fields[5];
/// `TIM15LPEN`, bit 16.
pub const TIM15LPEN: &FieldSpec = &super::REGISTERS[53].fields[6];
/// `TIM16LPEN`, bit 17.
pub const TIM16LPEN: &FieldSpec = &super::REGISTERS[53].fields[7];
/// `TIM17LPEN`, bit 18.
pub const TIM17LPEN: &FieldSpec = &super::REGISTERS[53].fields[8];
/// `SPI5LPEN`, bit 20.
pub const SPI5LPEN: &FieldSpec = &super::REGISTERS[53].fields[9];
/// `SAI1LPEN`, bit 22.
pub const SAI1LPEN: &FieldSpec = &super::REGISTERS[53].fields[10];
/// `SAI2LPEN`, bit 23.
pub const SAI2LPEN: &FieldSpec = &super::REGISTERS[53].fields[11];
/// `SAI3LPEN`, bit 24.
pub const SAI3LPEN: &FieldSpec = &super::REGISTERS[53].fields[12];
/// `DFSDM1LPEN`, bit 28.
pub const DFSDM1LPEN: &FieldSpec = &super::REGISTERS[53].fields[13];
/// `HRTIMLPEN`, bit 29.
pub const HRTIMLPEN: &FieldSpec = &super::REGISTERS[53].fields[14];
}
/// The fields of `APB4LPENR`.
pub mod apb4lpenr {
use super::FieldSpec;
/// `SYSCFGLPEN`, bit 1.
pub const SYSCFGLPEN: &FieldSpec = &super::REGISTERS[54].fields[0];
/// `LPUART1LPEN`, bit 3.
pub const LPUART1LPEN: &FieldSpec = &super::REGISTERS[54].fields[1];
/// `SPI6LPEN`, bit 5.
pub const SPI6LPEN: &FieldSpec = &super::REGISTERS[54].fields[2];
/// `I2C4LPEN`, bit 7.
pub const I2C4LPEN: &FieldSpec = &super::REGISTERS[54].fields[3];
/// `LPTIM2LPEN`, bit 9.
pub const LPTIM2LPEN: &FieldSpec = &super::REGISTERS[54].fields[4];
/// `LPTIM3LPEN`, bit 10.
pub const LPTIM3LPEN: &FieldSpec = &super::REGISTERS[54].fields[5];
/// `LPTIM4LPEN`, bit 11.
pub const LPTIM4LPEN: &FieldSpec = &super::REGISTERS[54].fields[6];
/// `LPTIM5LPEN`, bit 12.
pub const LPTIM5LPEN: &FieldSpec = &super::REGISTERS[54].fields[7];
/// `COMP12LPEN`, bit 14.
pub const COMP12LPEN: &FieldSpec = &super::REGISTERS[54].fields[8];
/// `VREFLPEN`, bit 15.
pub const VREFLPEN: &FieldSpec = &super::REGISTERS[54].fields[9];
/// `RTCAPBLPEN`, bit 16.
pub const RTCAPBLPEN: &FieldSpec = &super::REGISTERS[54].fields[10];
/// `SAI4LPEN`, bit 21.
pub const SAI4LPEN: &FieldSpec = &super::REGISTERS[54].fields[11];
}
/// The fields of `C1_RSR`.
pub mod c1_rsr {
use super::FieldSpec;
/// `RMVF`, bit 16.
pub const RMVF: &FieldSpec = &super::REGISTERS[55].fields[0];
/// `CPURSTF`, bit 17.
pub const CPURSTF: &FieldSpec = &super::REGISTERS[55].fields[1];
/// `D1RSTF`, bit 19.
pub const D1RSTF: &FieldSpec = &super::REGISTERS[55].fields[2];
/// `D2RSTF`, bit 20.
pub const D2RSTF: &FieldSpec = &super::REGISTERS[55].fields[3];
/// `BORRSTF`, bit 21.
pub const BORRSTF: &FieldSpec = &super::REGISTERS[55].fields[4];
/// `PINRSTF`, bit 22.
pub const PINRSTF: &FieldSpec = &super::REGISTERS[55].fields[5];
/// `PORRSTF`, bit 23.
pub const PORRSTF: &FieldSpec = &super::REGISTERS[55].fields[6];
/// `SFTRSTF`, bit 24.
pub const SFTRSTF: &FieldSpec = &super::REGISTERS[55].fields[7];
/// `IWDG1RSTF`, bit 26.
pub const IWDG1RSTF: &FieldSpec = &super::REGISTERS[55].fields[8];
/// `WWDG1RSTF`, bit 28.
pub const WWDG1RSTF: &FieldSpec = &super::REGISTERS[55].fields[9];
/// `LPWRRSTF`, bit 30.
pub const LPWRRSTF: &FieldSpec = &super::REGISTERS[55].fields[10];
}
/// The fields of `C1_AHB3ENR`.
pub mod c1_ahb3enr {
use super::FieldSpec;
/// `MDMAEN`, bit 0.
pub const MDMAEN: &FieldSpec = &super::REGISTERS[56].fields[0];
/// `DMA2DEN`, bit 4.
pub const DMA2DEN: &FieldSpec = &super::REGISTERS[56].fields[1];
/// `JPGDECEN`, bit 5.
pub const JPGDECEN: &FieldSpec = &super::REGISTERS[56].fields[2];
/// `FMCEN`, bit 12.
pub const FMCEN: &FieldSpec = &super::REGISTERS[56].fields[3];
/// `QSPIEN`, bit 14.
pub const QSPIEN: &FieldSpec = &super::REGISTERS[56].fields[4];
/// `SDMMC1EN`, bit 16.
pub const SDMMC1EN: &FieldSpec = &super::REGISTERS[56].fields[5];
}
/// The fields of `C1_AHB1ENR`.
pub mod c1_ahb1enr {
use super::FieldSpec;
/// `DMA1EN`, bit 0.
pub const DMA1EN: &FieldSpec = &super::REGISTERS[57].fields[0];
/// `DMA2EN`, bit 1.
pub const DMA2EN: &FieldSpec = &super::REGISTERS[57].fields[1];
/// `ADC12EN`, bit 5.
pub const ADC12EN: &FieldSpec = &super::REGISTERS[57].fields[2];
/// `ETH1MACEN`, bit 15.
pub const ETH1MACEN: &FieldSpec = &super::REGISTERS[57].fields[3];
/// `ETH1TXEN`, bit 16.
pub const ETH1TXEN: &FieldSpec = &super::REGISTERS[57].fields[4];
/// `ETH1RXEN`, bit 17.
pub const ETH1RXEN: &FieldSpec = &super::REGISTERS[57].fields[5];
/// `USB1OTGHSEN`, bit 25.
pub const USB1OTGHSEN: &FieldSpec = &super::REGISTERS[57].fields[6];
/// `USB1OTGHSULPIEN`, bit 26.
pub const USB1OTGHSULPIEN: &FieldSpec = &super::REGISTERS[57].fields[7];
/// `USB2OTGHSEN`, bit 27.
pub const USB2OTGHSEN: &FieldSpec = &super::REGISTERS[57].fields[8];
/// `USB2OTGHSULPIEN`, bit 28.
pub const USB2OTGHSULPIEN: &FieldSpec = &super::REGISTERS[57].fields[9];
}
/// The fields of `C1_AHB2ENR`.
pub mod c1_ahb2enr {
use super::FieldSpec;
/// `DCMIEN`, bit 0.
pub const DCMIEN: &FieldSpec = &super::REGISTERS[58].fields[0];
/// `CRYPTEN`, bit 4.
pub const CRYPTEN: &FieldSpec = &super::REGISTERS[58].fields[1];
/// `HASHEN`, bit 5.
pub const HASHEN: &FieldSpec = &super::REGISTERS[58].fields[2];
/// `RNGEN`, bit 6.
pub const RNGEN: &FieldSpec = &super::REGISTERS[58].fields[3];
/// `SDMMC2EN`, bit 9.
pub const SDMMC2EN: &FieldSpec = &super::REGISTERS[58].fields[4];
/// `SRAM1EN`, bit 29.
pub const SRAM1EN: &FieldSpec = &super::REGISTERS[58].fields[5];
/// `SRAM2EN`, bit 30.
pub const SRAM2EN: &FieldSpec = &super::REGISTERS[58].fields[6];
/// `SRAM3EN`, bit 31.
pub const SRAM3EN: &FieldSpec = &super::REGISTERS[58].fields[7];
}
/// The fields of `C1_AHB4ENR`.
pub mod c1_ahb4enr {
use super::FieldSpec;
/// `GPIOAEN`, bit 0.
pub const GPIOAEN: &FieldSpec = &super::REGISTERS[59].fields[0];
/// `GPIOBEN`, bit 1.
pub const GPIOBEN: &FieldSpec = &super::REGISTERS[59].fields[1];
/// `GPIOCEN`, bit 2.
pub const GPIOCEN: &FieldSpec = &super::REGISTERS[59].fields[2];
/// `GPIODEN`, bit 3.
pub const GPIODEN: &FieldSpec = &super::REGISTERS[59].fields[3];
/// `GPIOEEN`, bit 4.
pub const GPIOEEN: &FieldSpec = &super::REGISTERS[59].fields[4];
/// `GPIOFEN`, bit 5.
pub const GPIOFEN: &FieldSpec = &super::REGISTERS[59].fields[5];
/// `GPIOGEN`, bit 6.
pub const GPIOGEN: &FieldSpec = &super::REGISTERS[59].fields[6];
/// `GPIOHEN`, bit 7.
pub const GPIOHEN: &FieldSpec = &super::REGISTERS[59].fields[7];
/// `GPIOIEN`, bit 8.
pub const GPIOIEN: &FieldSpec = &super::REGISTERS[59].fields[8];
/// `GPIOJEN`, bit 9.
pub const GPIOJEN: &FieldSpec = &super::REGISTERS[59].fields[9];
/// `GPIOKEN`, bit 10.
pub const GPIOKEN: &FieldSpec = &super::REGISTERS[59].fields[10];
/// `CRCEN`, bit 19.
pub const CRCEN: &FieldSpec = &super::REGISTERS[59].fields[11];
/// `BDMAEN`, bit 21.
pub const BDMAEN: &FieldSpec = &super::REGISTERS[59].fields[12];
/// `ADC3EN`, bit 24.
pub const ADC3EN: &FieldSpec = &super::REGISTERS[59].fields[13];
/// `HSEMEN`, bit 25.
pub const HSEMEN: &FieldSpec = &super::REGISTERS[59].fields[14];
/// `BKPRAMEN`, bit 28.
pub const BKPRAMEN: &FieldSpec = &super::REGISTERS[59].fields[15];
}
/// The fields of `C1_APB3ENR`.
pub mod c1_apb3enr {
use super::FieldSpec;
/// `LTDCEN`, bit 3.
pub const LTDCEN: &FieldSpec = &super::REGISTERS[60].fields[0];
/// `WWDG1EN`, bit 6.
pub const WWDG1EN: &FieldSpec = &super::REGISTERS[60].fields[1];
}
/// The fields of `C1_APB1LENR`.
pub mod c1_apb1lenr {
use super::FieldSpec;
/// `TIM2EN`, bit 0.
pub const TIM2EN: &FieldSpec = &super::REGISTERS[61].fields[0];
/// `TIM3EN`, bit 1.
pub const TIM3EN: &FieldSpec = &super::REGISTERS[61].fields[1];
/// `TIM4EN`, bit 2.
pub const TIM4EN: &FieldSpec = &super::REGISTERS[61].fields[2];
/// `TIM5EN`, bit 3.
pub const TIM5EN: &FieldSpec = &super::REGISTERS[61].fields[3];
/// `TIM6EN`, bit 4.
pub const TIM6EN: &FieldSpec = &super::REGISTERS[61].fields[4];
/// `TIM7EN`, bit 5.
pub const TIM7EN: &FieldSpec = &super::REGISTERS[61].fields[5];
/// `TIM12EN`, bit 6.
pub const TIM12EN: &FieldSpec = &super::REGISTERS[61].fields[6];
/// `TIM13EN`, bit 7.
pub const TIM13EN: &FieldSpec = &super::REGISTERS[61].fields[7];
/// `TIM14EN`, bit 8.
pub const TIM14EN: &FieldSpec = &super::REGISTERS[61].fields[8];
/// `LPTIM1EN`, bit 9.
pub const LPTIM1EN: &FieldSpec = &super::REGISTERS[61].fields[9];
/// `SPI2EN`, bit 14.
pub const SPI2EN: &FieldSpec = &super::REGISTERS[61].fields[10];
/// `SPI3EN`, bit 15.
pub const SPI3EN: &FieldSpec = &super::REGISTERS[61].fields[11];
/// `SPDIFRXEN`, bit 16.
pub const SPDIFRXEN: &FieldSpec = &super::REGISTERS[61].fields[12];
/// `USART2EN`, bit 17.
pub const USART2EN: &FieldSpec = &super::REGISTERS[61].fields[13];
/// `USART3EN`, bit 18.
pub const USART3EN: &FieldSpec = &super::REGISTERS[61].fields[14];
/// `UART4EN`, bit 19.
pub const UART4EN: &FieldSpec = &super::REGISTERS[61].fields[15];
/// `UART5EN`, bit 20.
pub const UART5EN: &FieldSpec = &super::REGISTERS[61].fields[16];
/// `I2C1EN`, bit 21.
pub const I2C1EN: &FieldSpec = &super::REGISTERS[61].fields[17];
/// `I2C2EN`, bit 22.
pub const I2C2EN: &FieldSpec = &super::REGISTERS[61].fields[18];
/// `I2C3EN`, bit 23.
pub const I2C3EN: &FieldSpec = &super::REGISTERS[61].fields[19];
/// `HDMICECEN`, bit 27.
pub const HDMICECEN: &FieldSpec = &super::REGISTERS[61].fields[20];
/// `DAC12EN`, bit 29.
pub const DAC12EN: &FieldSpec = &super::REGISTERS[61].fields[21];
/// `USART7EN`, bit 30.
pub const USART7EN: &FieldSpec = &super::REGISTERS[61].fields[22];
/// `USART8EN`, bit 31.
pub const USART8EN: &FieldSpec = &super::REGISTERS[61].fields[23];
}
/// The fields of `C1_APB1HENR`.
pub mod c1_apb1henr {
use super::FieldSpec;
/// `CRSEN`, bit 1.
pub const CRSEN: &FieldSpec = &super::REGISTERS[62].fields[0];
/// `SWPEN`, bit 2.
pub const SWPEN: &FieldSpec = &super::REGISTERS[62].fields[1];
/// `OPAMPEN`, bit 4.
pub const OPAMPEN: &FieldSpec = &super::REGISTERS[62].fields[2];
/// `MDIOSEN`, bit 5.
pub const MDIOSEN: &FieldSpec = &super::REGISTERS[62].fields[3];
/// `FDCANEN`, bit 8.
pub const FDCANEN: &FieldSpec = &super::REGISTERS[62].fields[4];
}
/// The fields of `C1_APB2ENR`.
pub mod c1_apb2enr {
use super::FieldSpec;
/// `TIM1EN`, bit 0.
pub const TIM1EN: &FieldSpec = &super::REGISTERS[63].fields[0];
/// `TIM8EN`, bit 1.
pub const TIM8EN: &FieldSpec = &super::REGISTERS[63].fields[1];
/// `USART1EN`, bit 4.
pub const USART1EN: &FieldSpec = &super::REGISTERS[63].fields[2];
/// `USART6EN`, bit 5.
pub const USART6EN: &FieldSpec = &super::REGISTERS[63].fields[3];
/// `SPI1EN`, bit 12.
pub const SPI1EN: &FieldSpec = &super::REGISTERS[63].fields[4];
/// `SPI4EN`, bit 13.
pub const SPI4EN: &FieldSpec = &super::REGISTERS[63].fields[5];
/// `TIM15EN`, bit 16.
pub const TIM15EN: &FieldSpec = &super::REGISTERS[63].fields[6];
/// `TIM16EN`, bit 17.
pub const TIM16EN: &FieldSpec = &super::REGISTERS[63].fields[7];
/// `TIM17EN`, bit 18.
pub const TIM17EN: &FieldSpec = &super::REGISTERS[63].fields[8];
/// `SPI5EN`, bit 20.
pub const SPI5EN: &FieldSpec = &super::REGISTERS[63].fields[9];
/// `SAI1EN`, bit 22.
pub const SAI1EN: &FieldSpec = &super::REGISTERS[63].fields[10];
/// `SAI2EN`, bit 23.
pub const SAI2EN: &FieldSpec = &super::REGISTERS[63].fields[11];
/// `SAI3EN`, bit 24.
pub const SAI3EN: &FieldSpec = &super::REGISTERS[63].fields[12];
/// `DFSDM1EN`, bit 28.
pub const DFSDM1EN: &FieldSpec = &super::REGISTERS[63].fields[13];
/// `HRTIMEN`, bit 29.
pub const HRTIMEN: &FieldSpec = &super::REGISTERS[63].fields[14];
}
/// The fields of `C1_APB4ENR`.
pub mod c1_apb4enr {
use super::FieldSpec;
/// `SYSCFGEN`, bit 1.
pub const SYSCFGEN: &FieldSpec = &super::REGISTERS[64].fields[0];
/// `LPUART1EN`, bit 3.
pub const LPUART1EN: &FieldSpec = &super::REGISTERS[64].fields[1];
/// `SPI6EN`, bit 5.
pub const SPI6EN: &FieldSpec = &super::REGISTERS[64].fields[2];
/// `I2C4EN`, bit 7.
pub const I2C4EN: &FieldSpec = &super::REGISTERS[64].fields[3];
/// `LPTIM2EN`, bit 9.
pub const LPTIM2EN: &FieldSpec = &super::REGISTERS[64].fields[4];
/// `LPTIM3EN`, bit 10.
pub const LPTIM3EN: &FieldSpec = &super::REGISTERS[64].fields[5];
/// `LPTIM4EN`, bit 11.
pub const LPTIM4EN: &FieldSpec = &super::REGISTERS[64].fields[6];
/// `LPTIM5EN`, bit 12.
pub const LPTIM5EN: &FieldSpec = &super::REGISTERS[64].fields[7];
/// `COMP12EN`, bit 14.
pub const COMP12EN: &FieldSpec = &super::REGISTERS[64].fields[8];
/// `VREFEN`, bit 15.
pub const VREFEN: &FieldSpec = &super::REGISTERS[64].fields[9];
/// `RTCAPBEN`, bit 16.
pub const RTCAPBEN: &FieldSpec = &super::REGISTERS[64].fields[10];
/// `SAI4EN`, bit 21.
pub const SAI4EN: &FieldSpec = &super::REGISTERS[64].fields[11];
}
/// The fields of `C1_AHB3LPENR`.
pub mod c1_ahb3lpenr {
use super::FieldSpec;
/// `MDMALPEN`, bit 0.
pub const MDMALPEN: &FieldSpec = &super::REGISTERS[65].fields[0];
/// `DMA2DLPEN`, bit 4.
pub const DMA2DLPEN: &FieldSpec = &super::REGISTERS[65].fields[1];
/// `JPGDECLPEN`, bit 5.
pub const JPGDECLPEN: &FieldSpec = &super::REGISTERS[65].fields[2];
/// `FLITFLPEN`, bit 8.
pub const FLITFLPEN: &FieldSpec = &super::REGISTERS[65].fields[3];
/// `FMCLPEN`, bit 12.
pub const FMCLPEN: &FieldSpec = &super::REGISTERS[65].fields[4];
/// `QSPILPEN`, bit 14.
pub const QSPILPEN: &FieldSpec = &super::REGISTERS[65].fields[5];
/// `SDMMC1LPEN`, bit 16.
pub const SDMMC1LPEN: &FieldSpec = &super::REGISTERS[65].fields[6];
/// `D1DTCM1LPEN`, bit 28.
pub const D1DTCM1LPEN: &FieldSpec = &super::REGISTERS[65].fields[7];
/// `DTCM2LPEN`, bit 29.
pub const DTCM2LPEN: &FieldSpec = &super::REGISTERS[65].fields[8];
/// `ITCMLPEN`, bit 30.
pub const ITCMLPEN: &FieldSpec = &super::REGISTERS[65].fields[9];
/// `AXISRAMLPEN`, bit 31.
pub const AXISRAMLPEN: &FieldSpec = &super::REGISTERS[65].fields[10];
}
/// The fields of `C1_AHB1LPENR`.
pub mod c1_ahb1lpenr {
use super::FieldSpec;
/// `DMA1LPEN`, bit 0.
pub const DMA1LPEN: &FieldSpec = &super::REGISTERS[66].fields[0];
/// `DMA2LPEN`, bit 1.
pub const DMA2LPEN: &FieldSpec = &super::REGISTERS[66].fields[1];
/// `ADC12LPEN`, bit 5.
pub const ADC12LPEN: &FieldSpec = &super::REGISTERS[66].fields[2];
/// `ETH1MACLPEN`, bit 15.
pub const ETH1MACLPEN: &FieldSpec = &super::REGISTERS[66].fields[3];
/// `ETH1TXLPEN`, bit 16.
pub const ETH1TXLPEN: &FieldSpec = &super::REGISTERS[66].fields[4];
/// `ETH1RXLPEN`, bit 17.
pub const ETH1RXLPEN: &FieldSpec = &super::REGISTERS[66].fields[5];
/// `USB1OTGLPEN`, bit 25.
pub const USB1OTGLPEN: &FieldSpec = &super::REGISTERS[66].fields[6];
/// `USB1ULPILPEN`, bit 26.
pub const USB1ULPILPEN: &FieldSpec = &super::REGISTERS[66].fields[7];
/// `USB2OTGLPEN`, bit 27.
pub const USB2OTGLPEN: &FieldSpec = &super::REGISTERS[66].fields[8];
/// `USB2ULPILPEN`, bit 28.
pub const USB2ULPILPEN: &FieldSpec = &super::REGISTERS[66].fields[9];
}
/// The fields of `C1_AHB2LPENR`.
pub mod c1_ahb2lpenr {
use super::FieldSpec;
/// `CAMITFLPEN`, bit 0.
pub const CAMITFLPEN: &FieldSpec = &super::REGISTERS[67].fields[0];
/// `CRYPTLPEN`, bit 4.
pub const CRYPTLPEN: &FieldSpec = &super::REGISTERS[67].fields[1];
/// `HASHLPEN`, bit 5.
pub const HASHLPEN: &FieldSpec = &super::REGISTERS[67].fields[2];
/// `RNGLPEN`, bit 6.
pub const RNGLPEN: &FieldSpec = &super::REGISTERS[67].fields[3];
/// `SDMMC2LPEN`, bit 9.
pub const SDMMC2LPEN: &FieldSpec = &super::REGISTERS[67].fields[4];
/// `SRAM1LPEN`, bit 29.
pub const SRAM1LPEN: &FieldSpec = &super::REGISTERS[67].fields[5];
/// `SRAM2LPEN`, bit 30.
pub const SRAM2LPEN: &FieldSpec = &super::REGISTERS[67].fields[6];
/// `SRAM3LPEN`, bit 31.
pub const SRAM3LPEN: &FieldSpec = &super::REGISTERS[67].fields[7];
}
/// The fields of `C1_AHB4LPENR`.
pub mod c1_ahb4lpenr {
use super::FieldSpec;
/// `GPIOALPEN`, bit 0.
pub const GPIOALPEN: &FieldSpec = &super::REGISTERS[68].fields[0];
/// `GPIOBLPEN`, bit 1.
pub const GPIOBLPEN: &FieldSpec = &super::REGISTERS[68].fields[1];
/// `GPIOCLPEN`, bit 2.
pub const GPIOCLPEN: &FieldSpec = &super::REGISTERS[68].fields[2];
/// `GPIODLPEN`, bit 3.
pub const GPIODLPEN: &FieldSpec = &super::REGISTERS[68].fields[3];
/// `GPIOELPEN`, bit 4.
pub const GPIOELPEN: &FieldSpec = &super::REGISTERS[68].fields[4];
/// `GPIOFLPEN`, bit 5.
pub const GPIOFLPEN: &FieldSpec = &super::REGISTERS[68].fields[5];
/// `GPIOGLPEN`, bit 6.
pub const GPIOGLPEN: &FieldSpec = &super::REGISTERS[68].fields[6];
/// `GPIOHLPEN`, bit 7.
pub const GPIOHLPEN: &FieldSpec = &super::REGISTERS[68].fields[7];
/// `GPIOILPEN`, bit 8.
pub const GPIOILPEN: &FieldSpec = &super::REGISTERS[68].fields[8];
/// `GPIOJLPEN`, bit 9.
pub const GPIOJLPEN: &FieldSpec = &super::REGISTERS[68].fields[9];
/// `GPIOKLPEN`, bit 10.
pub const GPIOKLPEN: &FieldSpec = &super::REGISTERS[68].fields[10];
/// `CRCLPEN`, bit 19.
pub const CRCLPEN: &FieldSpec = &super::REGISTERS[68].fields[11];
/// `BDMALPEN`, bit 21.
pub const BDMALPEN: &FieldSpec = &super::REGISTERS[68].fields[12];
/// `ADC3LPEN`, bit 24.
pub const ADC3LPEN: &FieldSpec = &super::REGISTERS[68].fields[13];
/// `BKPRAMLPEN`, bit 28.
pub const BKPRAMLPEN: &FieldSpec = &super::REGISTERS[68].fields[14];
/// `SRAM4LPEN`, bit 29.
pub const SRAM4LPEN: &FieldSpec = &super::REGISTERS[68].fields[15];
}
/// The fields of `C1_APB3LPENR`.
pub mod c1_apb3lpenr {
use super::FieldSpec;
/// `LTDCLPEN`, bit 3.
pub const LTDCLPEN: &FieldSpec = &super::REGISTERS[69].fields[0];
/// `WWDG1LPEN`, bit 6.
pub const WWDG1LPEN: &FieldSpec = &super::REGISTERS[69].fields[1];
}
/// The fields of `C1_APB1LLPENR`.
pub mod c1_apb1llpenr {
use super::FieldSpec;
/// `TIM2LPEN`, bit 0.
pub const TIM2LPEN: &FieldSpec = &super::REGISTERS[70].fields[0];
/// `TIM3LPEN`, bit 1.
pub const TIM3LPEN: &FieldSpec = &super::REGISTERS[70].fields[1];
/// `TIM4LPEN`, bit 2.
pub const TIM4LPEN: &FieldSpec = &super::REGISTERS[70].fields[2];
/// `TIM5LPEN`, bit 3.
pub const TIM5LPEN: &FieldSpec = &super::REGISTERS[70].fields[3];
/// `TIM6LPEN`, bit 4.
pub const TIM6LPEN: &FieldSpec = &super::REGISTERS[70].fields[4];
/// `TIM7LPEN`, bit 5.
pub const TIM7LPEN: &FieldSpec = &super::REGISTERS[70].fields[5];
/// `TIM12LPEN`, bit 6.
pub const TIM12LPEN: &FieldSpec = &super::REGISTERS[70].fields[6];
/// `TIM13LPEN`, bit 7.
pub const TIM13LPEN: &FieldSpec = &super::REGISTERS[70].fields[7];
/// `TIM14LPEN`, bit 8.
pub const TIM14LPEN: &FieldSpec = &super::REGISTERS[70].fields[8];
/// `LPTIM1LPEN`, bit 9.
pub const LPTIM1LPEN: &FieldSpec = &super::REGISTERS[70].fields[9];
/// `SPI2LPEN`, bit 14.
pub const SPI2LPEN: &FieldSpec = &super::REGISTERS[70].fields[10];
/// `SPI3LPEN`, bit 15.
pub const SPI3LPEN: &FieldSpec = &super::REGISTERS[70].fields[11];
/// `SPDIFRXLPEN`, bit 16.
pub const SPDIFRXLPEN: &FieldSpec = &super::REGISTERS[70].fields[12];
/// `USART2LPEN`, bit 17.
pub const USART2LPEN: &FieldSpec = &super::REGISTERS[70].fields[13];
/// `USART3LPEN`, bit 18.
pub const USART3LPEN: &FieldSpec = &super::REGISTERS[70].fields[14];
/// `UART4LPEN`, bit 19.
pub const UART4LPEN: &FieldSpec = &super::REGISTERS[70].fields[15];
/// `UART5LPEN`, bit 20.
pub const UART5LPEN: &FieldSpec = &super::REGISTERS[70].fields[16];
/// `I2C1LPEN`, bit 21.
pub const I2C1LPEN: &FieldSpec = &super::REGISTERS[70].fields[17];
/// `I2C2LPEN`, bit 22.
pub const I2C2LPEN: &FieldSpec = &super::REGISTERS[70].fields[18];
/// `I2C3LPEN`, bit 23.
pub const I2C3LPEN: &FieldSpec = &super::REGISTERS[70].fields[19];
/// `HDMICECLPEN`, bit 27.
pub const HDMICECLPEN: &FieldSpec = &super::REGISTERS[70].fields[20];
/// `DAC12LPEN`, bit 29.
pub const DAC12LPEN: &FieldSpec = &super::REGISTERS[70].fields[21];
/// `USART7LPEN`, bit 30.
pub const USART7LPEN: &FieldSpec = &super::REGISTERS[70].fields[22];
/// `USART8LPEN`, bit 31.
pub const USART8LPEN: &FieldSpec = &super::REGISTERS[70].fields[23];
}
/// The fields of `C1_APB1HLPENR`.
pub mod c1_apb1hlpenr {
use super::FieldSpec;
/// `CRSLPEN`, bit 1.
pub const CRSLPEN: &FieldSpec = &super::REGISTERS[71].fields[0];
/// `SWPLPEN`, bit 2.
pub const SWPLPEN: &FieldSpec = &super::REGISTERS[71].fields[1];
/// `OPAMPLPEN`, bit 4.
pub const OPAMPLPEN: &FieldSpec = &super::REGISTERS[71].fields[2];
/// `MDIOSLPEN`, bit 5.
pub const MDIOSLPEN: &FieldSpec = &super::REGISTERS[71].fields[3];
/// `FDCANLPEN`, bit 8.
pub const FDCANLPEN: &FieldSpec = &super::REGISTERS[71].fields[4];
}
/// The fields of `C1_APB2LPENR`.
pub mod c1_apb2lpenr {
use super::FieldSpec;
/// `TIM1LPEN`, bit 0.
pub const TIM1LPEN: &FieldSpec = &super::REGISTERS[72].fields[0];
/// `TIM8LPEN`, bit 1.
pub const TIM8LPEN: &FieldSpec = &super::REGISTERS[72].fields[1];
/// `USART1LPEN`, bit 4.
pub const USART1LPEN: &FieldSpec = &super::REGISTERS[72].fields[2];
/// `USART6LPEN`, bit 5.
pub const USART6LPEN: &FieldSpec = &super::REGISTERS[72].fields[3];
/// `SPI1LPEN`, bit 12.
pub const SPI1LPEN: &FieldSpec = &super::REGISTERS[72].fields[4];
/// `SPI4LPEN`, bit 13.
pub const SPI4LPEN: &FieldSpec = &super::REGISTERS[72].fields[5];
/// `TIM15LPEN`, bit 16.
pub const TIM15LPEN: &FieldSpec = &super::REGISTERS[72].fields[6];
/// `TIM16LPEN`, bit 17.
pub const TIM16LPEN: &FieldSpec = &super::REGISTERS[72].fields[7];
/// `TIM17LPEN`, bit 18.
pub const TIM17LPEN: &FieldSpec = &super::REGISTERS[72].fields[8];
/// `SPI5LPEN`, bit 20.
pub const SPI5LPEN: &FieldSpec = &super::REGISTERS[72].fields[9];
/// `SAI1LPEN`, bit 22.
pub const SAI1LPEN: &FieldSpec = &super::REGISTERS[72].fields[10];
/// `SAI2LPEN`, bit 23.
pub const SAI2LPEN: &FieldSpec = &super::REGISTERS[72].fields[11];
/// `SAI3LPEN`, bit 24.
pub const SAI3LPEN: &FieldSpec = &super::REGISTERS[72].fields[12];
/// `DFSDM1LPEN`, bit 28.
pub const DFSDM1LPEN: &FieldSpec = &super::REGISTERS[72].fields[13];
/// `HRTIMLPEN`, bit 29.
pub const HRTIMLPEN: &FieldSpec = &super::REGISTERS[72].fields[14];
}
/// The fields of `C1_APB4LPENR`.
pub mod c1_apb4lpenr {
use super::FieldSpec;
/// `SYSCFGLPEN`, bit 1.
pub const SYSCFGLPEN: &FieldSpec = &super::REGISTERS[73].fields[0];
/// `LPUART1LPEN`, bit 3.
pub const LPUART1LPEN: &FieldSpec = &super::REGISTERS[73].fields[1];
/// `SPI6LPEN`, bit 5.
pub const SPI6LPEN: &FieldSpec = &super::REGISTERS[73].fields[2];
/// `I2C4LPEN`, bit 7.
pub const I2C4LPEN: &FieldSpec = &super::REGISTERS[73].fields[3];
/// `LPTIM2LPEN`, bit 9.
pub const LPTIM2LPEN: &FieldSpec = &super::REGISTERS[73].fields[4];
/// `LPTIM3LPEN`, bit 10.
pub const LPTIM3LPEN: &FieldSpec = &super::REGISTERS[73].fields[5];
/// `LPTIM4LPEN`, bit 11.
pub const LPTIM4LPEN: &FieldSpec = &super::REGISTERS[73].fields[6];
/// `LPTIM5LPEN`, bit 12.
pub const LPTIM5LPEN: &FieldSpec = &super::REGISTERS[73].fields[7];
/// `COMP12LPEN`, bit 14.
pub const COMP12LPEN: &FieldSpec = &super::REGISTERS[73].fields[8];
/// `VREFLPEN`, bit 15.
pub const VREFLPEN: &FieldSpec = &super::REGISTERS[73].fields[9];
/// `RTCAPBLPEN`, bit 16.
pub const RTCAPBLPEN: &FieldSpec = &super::REGISTERS[73].fields[10];
/// `SAI4LPEN`, bit 21.
pub const SAI4LPEN: &FieldSpec = &super::REGISTERS[73].fields[11];
}
/// The register table.
pub static REGISTERS: [RegisterSpec; 74] = [
RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0083, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "HSION", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIKERON", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIRDY", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIDIV", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIDIVF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSION", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSIRDY", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSIKERON", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RC48ON", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RC48RDY", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1CKRDY", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D2CKRDY", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSEON", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSERDY", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSEBYP", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSECSSON", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1ON", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1RDY", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2ON", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2RDY", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3ON", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3RDY", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "HSICFGR", offset: 0x4, width: Width::W32, reset: 0x4000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "HSICAL", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSITRIM", bit: 24, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "ICSCR", offset: 0x4, width: Width::W32, reset: 0x4000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "HSICAL", bit: 0, width: 12, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSITRIM", bit: 12, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSICAL", bit: 18, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSITRIM", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CRRCR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RC48CAL", bit: 0, width: 10, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CFGR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SW", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWS", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STOPWUCK", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "STOPKERWUCK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCPRE", bit: 8, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMSEL", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIMPRE", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MCO1PRE", bit: 18, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MCO1SEL", bit: 22, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MCO2PRE", bit: 25, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MCO2SEL", bit: 29, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D1CFGR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "HPRE", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1PPRE", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1CPRE", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D2CFGR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "D2PPRE1", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D2PPRE2", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D3CFGR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "D3PPRE", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLLCKSELR", offset: 0x28, width: Width::W32, reset: 0x0202_0200, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PLLSRC", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVM1", bit: 4, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVM2", bit: 12, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVM3", bit: 20, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLLCFGR", offset: 0x2C, width: Width::W32, reset: 0x01FF_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "PLL1FRACEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1VCOSEL", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1RGE", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2FRACEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2VCOSEL", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2RGE", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3FRACEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3VCOSEL", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3RGE", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP1EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ1EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR1EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP2EN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ2EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR2EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP3EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ3EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR3EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL1DIVR", offset: 0x30, width: Width::W32, reset: 0x0101_0280, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIVN1", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP1", bit: 9, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ1", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR1", bit: 24, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL1FRACR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FRACN1", bit: 3, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL2DIVR", offset: 0x38, width: Width::W32, reset: 0x0101_0280, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIVN2", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP2", bit: 9, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ2", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR2", bit: 24, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL2FRACR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FRACN2", bit: 3, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL3DIVR", offset: 0x40, width: Width::W32, reset: 0x0101_0280, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DIVN3", bit: 0, width: 9, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVP3", bit: 9, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVQ3", bit: 16, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DIVR3", bit: 24, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "PLL3FRACR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FRACN3", bit: 3, width: 13, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D1CCIPR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "FMCSEL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPISEL", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMCSEL", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CKPERSEL", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D2CCIP1R", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SAI1SEL", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI23SEL", bit: 6, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI123SEL", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI45SEL", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFSEL", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1SEL", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANSEL", bit: 28, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPSEL", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D2CCIP2R", offset: 0x54, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "USART234578SEL", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART16SEL", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGSEL", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C123SEL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USBSEL", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CECSEL", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1SEL", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D3CCIPR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LPUART1SEL", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4SEL", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2SEL", bit: 10, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM345SEL", bit: 13, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADCSEL", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4ASEL", bit: 21, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4BSEL", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6SEL", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CIER", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LSIRDYIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSERDYIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIRDYIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSERDYIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSIRDYIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RC48RDYIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1RDYIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2RDYIE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3RDYIE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSECSSIE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CIFR", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LSIRDYF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSERDYF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIRDYF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSERDYF", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CSIRDY", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RC48RDYF", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1RDYF", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2RDYF", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3RDYF", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSECSSF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSECSSF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CICR", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LSIRDYC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSERDYC", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSIRDYC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSERDYC", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSE_ready_Interrupt_Clear", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RC48RDYC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL1RDYC", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL2RDYC", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PLL3RDYC", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSECSSC", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSECSSC", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "BDCR", offset: 0x70, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LSEON", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSERDY", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSEBYP", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSEDRV", bit: 3, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSECSSON", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSECSSD", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCSRC", bit: 8, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VSWRST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "CSR", offset: 0x74, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LSION", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LSIRDY", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB3RSTR", offset: 0x7C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDMARST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2DRST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JPGDECRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMCRST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPIRST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC1RST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CPURST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB1RSTR", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DMA1RST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2RST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC12RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1MACRST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGRST", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGRST", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB2RSTR", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CAMITFRST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRYPTRST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HASHRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGRST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC2RST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB4RSTR", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GPIOARST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOBRST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOCRST", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIODRST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOERST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOFRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOGRST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOHRST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOJRST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOKRST", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCRST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BDMARST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3RST", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSEMRST", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB3RSTR", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCRST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1LRSTR", offset: 0x90, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM2RST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM3RST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM4RST", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM5RST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM6RST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM7RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM12RST", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM13RST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM14RST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1RST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI2RST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI3RST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFRXRST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART2RST", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART3RST", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART4RST", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART5RST", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C1RST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C2RST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C3RST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CECRST", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DAC12RST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART7RST", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART8RST", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1HRSTR", offset: 0x94, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRSRST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPRST", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPAMPRST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDIOSRST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB2RSTR", offset: 0x98, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM1RST", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM8RST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART1RST", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART6RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI1RST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI4RST", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM15RST", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM16RST", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM17RST", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI5RST", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI1RST", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI2RST", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI3RST", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1RST", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMRST", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB4RSTR", offset: 0x9C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SYSCFGRST", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1RST", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6RST", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4RST", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2RST", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3RST", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4RST", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5RST", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12RST", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFRST", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4RST", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "GCR", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "WW1RSC", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "D3AMR", offset: 0xA8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "BDMAAMEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1AMEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6AMEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4AMEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2AMEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3AMEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4AMEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5AMEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12AMEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFAMEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCAMEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCAMEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4AMEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3AMEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKPRAMAMEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM4AMEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "RSR", offset: 0xD0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RMVF", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CPURSTF", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1RSTF", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D2RSTF", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BORRSTF", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PINRSTF", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PORRSTF", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SFTRSTF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1RSTF", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1RSTF", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPWRRSTF", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB3ENR", offset: 0xD4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDMAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2DEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JPGDECEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMCEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPIEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC1EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB1ENR", offset: 0xD8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DMA1EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC12EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1MACEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1TXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1RXEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSULPIEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSULPIEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB2ENR", offset: 0xDC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DCMIEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRYPTEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HASHEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC2EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM1EN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM2EN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM3EN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB4ENR", offset: 0xE0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GPIOAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOBEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOCEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIODEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOEEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOIEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOJEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOKEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSEMEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKPRAMEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB3ENR", offset: 0xE4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1EN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1LENR", offset: 0xE8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM2EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM3EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM4EN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM5EN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM6EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM7EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM12EN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM13EN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM14EN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI2EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI3EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFRXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART2EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART3EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART4EN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C1EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C2EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C3EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CECEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DAC12EN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART7EN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART8EN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1HENR", offset: 0xEC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRSEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPAMPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDIOSEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB2ENR", offset: 0xF0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM1EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM8EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART1EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART6EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI1EN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI4EN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM15EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM16EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM17EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI1EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI2EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI3EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1EN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB4ENR", offset: 0xF4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SYSCFGEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1EN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4EN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3EN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4EN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5EN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCAPBEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB3LPENR", offset: 0xFC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDMALPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2DLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JPGDECLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FLASHLPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMCLPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPILPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC1LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1DTCM1LPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DTCM2LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ITCMLPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "AXISRAMLPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB1LPENR", offset: 0x100, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DMA1LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC12LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1MACLPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1TXLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1RXLPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSLPEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSULPILPEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSLPEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSULPILPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB2LPENR", offset: 0x104, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CAMITFLPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRYPTLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HASHLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC2LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM1LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM2LPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM3LPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "AHB4LPENR", offset: 0x108, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GPIOALPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOBLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOCLPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIODLPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOELPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOFLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOHLPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOILPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOJLPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOKLPEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCLPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BDMALPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3LPEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKPRAMLPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM4LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB3LPENR", offset: 0x10C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCLPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1LPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1LLPENR", offset: 0x110, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM2LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM3LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM4LPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM5LPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM6LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM7LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM12LPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM13LPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM14LPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI2LPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI3LPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFRXLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART2LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART3LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART4LPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C1LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C2LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C3LPEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HDMICECLPEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DAC12LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART7LPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART8LPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB1HLPENR", offset: 0x114, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRSLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPLPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPAMPLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDIOSLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANLPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB2LPENR", offset: 0x118, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM1LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM8LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART1LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART6LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI1LPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI4LPEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM15LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM16LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM17LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI1LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI2LPEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI3LPEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1LPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMLPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "APB4LPENR", offset: 0x11C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SYSCFGLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1LPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4LPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3LPEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4LPEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5LPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12LPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFLPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCAPBLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_RSR", offset: 0x130, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "RMVF", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CPURSTF", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1RSTF", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D2RSTF", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BORRSTF", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PINRSTF", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "PORRSTF", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SFTRSTF", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "IWDG1RSTF", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1RSTF", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPWRRSTF", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB3ENR", offset: 0x134, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDMAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2DEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JPGDECEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMCEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPIEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC1EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB1ENR", offset: 0x138, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DMA1EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC12EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1MACEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1TXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1RXEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGHSULPIEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGHSULPIEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB2ENR", offset: 0x13C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DCMIEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRYPTEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HASHEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC2EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM1EN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM2EN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM3EN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB4ENR", offset: 0x140, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GPIOAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOBEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOCEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIODEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOEEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOFEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOGEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOHEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOIEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOJEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOKEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BDMAEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HSEMEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKPRAMEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB3ENR", offset: 0x144, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1EN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB1LENR", offset: 0x148, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM2EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM3EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM4EN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM5EN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM6EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM7EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM12EN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM13EN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM14EN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI2EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI3EN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFRXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART2EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART3EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART4EN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C1EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C2EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C3EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HDMICECEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DAC12EN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART7EN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART8EN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB1HENR", offset: 0x14C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRSEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPAMPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDIOSEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB2ENR", offset: 0x150, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM1EN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM8EN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART1EN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART6EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI1EN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI4EN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM15EN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM16EN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM17EN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI5EN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI1EN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI2EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI3EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1EN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB4ENR", offset: 0x154, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SYSCFGEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1EN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6EN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4EN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2EN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3EN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4EN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5EN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12EN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCAPBEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4EN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB3LPENR", offset: 0x15C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "MDMALPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2DLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "JPGDECLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FLITFLPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FMCLPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "QSPILPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC1LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "D1DTCM1LPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DTCM2LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ITCMLPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "AXISRAMLPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB1LPENR", offset: 0x160, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "DMA1LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DMA2LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC12LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1MACLPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1TXLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ETH1RXLPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1OTGLPEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB1ULPILPEN", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2OTGLPEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USB2ULPILPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB2LPENR", offset: 0x164, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CAMITFLPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRYPTLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HASHLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RNGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SDMMC2LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM1LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM2LPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM3LPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_AHB4LPENR", offset: 0x168, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "GPIOALPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOBLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOCLPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIODLPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOELPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOFLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOGLPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOHLPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOILPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOJLPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "GPIOKLPEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "CRCLPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BDMALPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "ADC3LPEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "BKPRAMLPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SRAM4LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB3LPENR", offset: 0x16C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "LTDCLPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "WWDG1LPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB1LLPENR", offset: 0x170, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM2LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM3LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM4LPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM5LPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM6LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM7LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM12LPEN", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM13LPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM14LPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM1LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI2LPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI3LPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPDIFRXLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART2LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART3LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART4LPEN", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "UART5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C1LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C2LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C3LPEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HDMICECLPEN", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DAC12LPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART7LPEN", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART8LPEN", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB1HLPENR", offset: 0x174, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "CRSLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SWPLPEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "OPAMPLPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "MDIOSLPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "FDCANLPEN", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB2LPENR", offset: 0x178, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "TIM1LPEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM8LPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART1LPEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "USART6LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI1LPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI4LPEN", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM15LPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM16LPEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "TIM17LPEN", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI5LPEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI1LPEN", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI2LPEN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI3LPEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "DFSDM1LPEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "HRTIMLPEN", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
RegisterSpec { name: "C1_APB4LPENR", offset: 0x17C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
FieldSpec { name: "SYSCFGLPEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPUART1LPEN", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SPI6LPEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "I2C4LPEN", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM2LPEN", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM3LPEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM4LPEN", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "LPTIM5LPEN", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "COMP12LPEN", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "VREFLPEN", bit: 15, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "RTCAPBLPEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
FieldSpec { name: "SAI4LPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
] },
];