rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `RAMECC3` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `IER` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Ier = 0,
    /// `M1CR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    M1cr = 1,
    /// `M1SR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    M1sr = 2,
    /// `M1FAR` at offset `0x28`, resets to `0x0000_0000`, read-only.
    M1far = 3,
    /// `M1FDRL` at offset `0x2C`, resets to `0x0000_0000`, read-only.
    M1fdrl = 4,
    /// `M1FDRH` at offset `0x30`, resets to `0x0000_0000`, read-only.
    M1fdrh = 5,
    /// `M1FECR` at offset `0x34`, resets to `0x0000_0000`, read-write.
    M1fecr = 6,
    /// `M2CR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    M2cr = 7,
    /// `M2SR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    M2sr = 8,
    /// `M2FAR` at offset `0x48`, resets to `0x0000_0000`, read-only.
    M2far = 9,
    /// `M2FDRL` at offset `0x4C`, resets to `0x0000_0000`, read-only.
    M2fdrl = 10,
    /// `M2FDRH` at offset `0x50`, resets to `0x0000_0000`, read-write.
    M2fdrh = 11,
    /// `M2FECR` at offset `0x58`, resets to `0x0000_0000`, read-write.
    M2fecr = 12,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 13] = [Self::Ier, Self::M1cr, Self::M1sr, Self::M1far, Self::M1fdrl, Self::M1fdrh, Self::M1fecr, Self::M2cr, Self::M2sr, Self::M2far, Self::M2fdrl, Self::M2fdrh, Self::M2fecr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `GIE`, bit 0.
    pub const GIE: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `GECCSEIE_`, bit 1.
    pub const GECCSEIE_: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `GECCDEIE`, bit 2.
    pub const GECCDEIE: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `GECCDEBWIE`, bit 3.
    pub const GECCDEBWIE: &FieldSpec = &super::REGISTERS[0].fields[3];
}

/// The fields of `M1CR`.
pub mod m1cr {
    use super::FieldSpec;
    /// `ECCSEIE`, bit 2.
    pub const ECCSEIE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ECCDEIE`, bit 3.
    pub const ECCDEIE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `ECCDEBWIE`, bit 4.
    pub const ECCDEBWIE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `ECCELEN`, bit 5.
    pub const ECCELEN: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The fields of `M1SR`.
pub mod m1sr {
    use super::FieldSpec;
    /// `SEDCF`, bit 0.
    pub const SEDCF: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `DEDF`, bit 1.
    pub const DEDF: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `DEBWDF`, bit 2.
    pub const DEBWDF: &FieldSpec = &super::REGISTERS[2].fields[2];
}

/// The fields of `M1FAR`.
pub mod m1far {
    use super::FieldSpec;
    /// `FADD`, bits 0..=31.
    pub const FADD: &FieldSpec = &super::REGISTERS[3].fields[0];
}

/// The fields of `M1FDRL`.
pub mod m1fdrl {
    use super::FieldSpec;
    /// `FDATAL`, bits 0..=31.
    pub const FDATAL: &FieldSpec = &super::REGISTERS[4].fields[0];
}

/// The fields of `M1FDRH`.
pub mod m1fdrh {
    use super::FieldSpec;
    /// `FDATAH`, bits 0..=31.
    pub const FDATAH: &FieldSpec = &super::REGISTERS[5].fields[0];
}

/// The fields of `M1FECR`.
pub mod m1fecr {
    use super::FieldSpec;
    /// `FEC`, bits 0..=31.
    pub const FEC: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `M2CR`.
pub mod m2cr {
    use super::FieldSpec;
    /// `ECCSEIE`, bit 2.
    pub const ECCSEIE: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `ECCDEIE`, bit 3.
    pub const ECCDEIE: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `ECCDEBWIE`, bit 4.
    pub const ECCDEBWIE: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `ECCELEN`, bit 5.
    pub const ECCELEN: &FieldSpec = &super::REGISTERS[7].fields[3];
}

/// The fields of `M2SR`.
pub mod m2sr {
    use super::FieldSpec;
    /// `SEDCF`, bit 0.
    pub const SEDCF: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `DEDF`, bit 1.
    pub const DEDF: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `DEBWDF`, bit 2.
    pub const DEBWDF: &FieldSpec = &super::REGISTERS[8].fields[2];
}

/// The fields of `M2FAR`.
pub mod m2far {
    use super::FieldSpec;
    /// `FADD`, bits 0..=31.
    pub const FADD: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `M2FDRL`.
pub mod m2fdrl {
    use super::FieldSpec;
    /// `FDATAL`, bits 0..=31.
    pub const FDATAL: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `M2FDRH`.
pub mod m2fdrh {
    use super::FieldSpec;
    /// `FDATAH`, bits 0..=31.
    pub const FDATAH: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The fields of `M2FECR`.
pub mod m2fecr {
    use super::FieldSpec;
    /// `FEC`, bits 0..=31.
    pub const FEC: &FieldSpec = &super::REGISTERS[12].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 13] = [
    RegisterSpec { name: "IER", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "GIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GECCSEIE_", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GECCDEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "GECCDEBWIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1CR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ECCSEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCDEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCDEBWIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCELEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1SR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SEDCF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEDF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEBWDF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1FAR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FADD", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1FDRL", offset: 0x2C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FDATAL", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1FDRH", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FDATAH", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M1FECR", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FEC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2CR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ECCSEIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCDEIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCDEBWIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ECCELEN", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2SR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SEDCF", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEDF", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEBWDF", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2FAR", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FADD", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2FDRL", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FDATAL", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2FDRH", offset: 0x50, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FDATAH", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "M2FECR", offset: 0x58, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FEC", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];