rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `OPAMP` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `OPAMP1_CSR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Opamp1Csr = 0,
    /// `OPAMP1_OTR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Opamp1Otr = 1,
    /// `OPAMP1_HSOTR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Opamp1Hsotr = 2,
    /// `OPAMP2_CSR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Opamp2Csr = 3,
    /// `OPAMP2_OTR` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Opamp2Otr = 4,
    /// `OPAMP2_HSOTR` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Opamp2Hsotr = 5,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 6] = [Self::Opamp1Csr, Self::Opamp1Otr, Self::Opamp1Hsotr, Self::Opamp2Csr, Self::Opamp2Otr, Self::Opamp2Hsotr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `OPAMP1_CSR`.
pub mod opamp1_csr {
    use super::FieldSpec;
    /// `OPAEN`, bit 0.
    pub const OPAEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `FORCE_VP`, bit 1.
    pub const FORCE_VP: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `VP_SEL`, bits 2..=3.
    pub const VP_SEL: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `VM_SEL`, bits 5..=6.
    pub const VM_SEL: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `OPAHSM`, bit 8.
    pub const OPAHSM: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `CALON`, bit 11.
    pub const CALON: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `CALSEL`, bits 12..=13.
    pub const CALSEL: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `PGA_GAIN`, bits 14..=17.
    pub const PGA_GAIN: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `USERTRIM`, bit 18.
    pub const USERTRIM: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `TSTREF`, bit 29.
    pub const TSTREF: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `CALOUT`, bit 30.
    pub const CALOUT: &FieldSpec = &super::REGISTERS[0].fields[10];
}

/// The fields of `OPAMP1_OTR`.
pub mod opamp1_otr {
    use super::FieldSpec;
    /// `TRIMOFFSETN`, bits 0..=4.
    pub const TRIMOFFSETN: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `TRIMOFFSETP`, bits 8..=12.
    pub const TRIMOFFSETP: &FieldSpec = &super::REGISTERS[1].fields[1];
}

/// The fields of `OPAMP1_HSOTR`.
pub mod opamp1_hsotr {
    use super::FieldSpec;
    /// `TRIMLPOFFSETN`, bits 0..=4.
    pub const TRIMLPOFFSETN: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `TRIMLPOFFSETP`, bits 8..=12.
    pub const TRIMLPOFFSETP: &FieldSpec = &super::REGISTERS[2].fields[1];
}

/// The fields of `OPAMP2_CSR`.
pub mod opamp2_csr {
    use super::FieldSpec;
    /// `OPAEN`, bit 0.
    pub const OPAEN: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `FORCE_VP`, bit 1.
    pub const FORCE_VP: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `VM_SEL`, bits 5..=6.
    pub const VM_SEL: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `OPAHSM`, bit 8.
    pub const OPAHSM: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `CALON`, bit 11.
    pub const CALON: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `CALSEL`, bits 12..=13.
    pub const CALSEL: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `PGA_GAIN`, bits 14..=17.
    pub const PGA_GAIN: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `USERTRIM`, bit 18.
    pub const USERTRIM: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `TSTREF`, bit 29.
    pub const TSTREF: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `CALOUT`, bit 30.
    pub const CALOUT: &FieldSpec = &super::REGISTERS[3].fields[9];
}

/// The fields of `OPAMP2_OTR`.
pub mod opamp2_otr {
    use super::FieldSpec;
    /// `TRIMOFFSETN`, bits 0..=4.
    pub const TRIMOFFSETN: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `TRIMOFFSETP`, bits 8..=12.
    pub const TRIMOFFSETP: &FieldSpec = &super::REGISTERS[4].fields[1];
}

/// The fields of `OPAMP2_HSOTR`.
pub mod opamp2_hsotr {
    use super::FieldSpec;
    /// `TRIMLPOFFSETN`, bits 0..=4.
    pub const TRIMLPOFFSETN: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `TRIMLPOFFSETP`, bits 8..=12.
    pub const TRIMLPOFFSETP: &FieldSpec = &super::REGISTERS[5].fields[1];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 6] = [
    RegisterSpec { name: "OPAMP1_CSR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OPAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORCE_VP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VP_SEL", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VM_SEL", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPAHSM", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALON", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALSEL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PGA_GAIN", bit: 14, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USERTRIM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTREF", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALOUT", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPAMP1_OTR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRIMOFFSETN", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIMOFFSETP", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPAMP1_HSOTR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRIMLPOFFSETN", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIMLPOFFSETP", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPAMP2_CSR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OPAEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FORCE_VP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VM_SEL", bit: 5, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OPAHSM", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALON", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALSEL", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PGA_GAIN", bit: 14, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USERTRIM", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TSTREF", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALOUT", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPAMP2_OTR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRIMOFFSETN", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIMOFFSETP", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OPAMP2_HSOTR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "TRIMLPOFFSETN", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIMLPOFFSETP", bit: 8, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];