rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
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// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `PWR` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR1` at offset `0x0`, resets to `0xF000_C000`, read-write.
    Cr1 = 0,
    /// `CSR1` at offset `0x4`, resets to `0x0000_4000`, read-only.
    Csr1 = 1,
    /// `CR2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cr2 = 2,
    /// `CR3` at offset `0xC`, resets to `0x0000_0006`, read-write.
    Cr3 = 3,
    /// `CPUCR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Cpucr = 4,
    /// `D3CR` at offset `0x18`, resets to `0x0000_4000`, read-write.
    D3cr = 5,
    /// `WKUPCR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    Wkupcr = 6,
    /// `WKUPFR` at offset `0x24`, resets to `0x0000_0000`, read-write.
    Wkupfr = 7,
    /// `WKUPEPR` at offset `0x28`, resets to `0x0000_0000`, read-write.
    Wkupepr = 8,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 9] = [Self::Cr1, Self::Csr1, Self::Cr2, Self::Cr3, Self::Cpucr, Self::D3cr, Self::Wkupcr, Self::Wkupfr, Self::Wkupepr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR1`.
pub mod cr1 {
    use super::FieldSpec;
    /// `LPDS`, bit 0.
    pub const LPDS: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `PVDE`, bit 4.
    pub const PVDE: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `PLS`, bits 5..=7.
    pub const PLS: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `DBP`, bit 8.
    pub const DBP: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `FLPS`, bit 9.
    pub const FLPS: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `SVOS`, bits 14..=15.
    pub const SVOS: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `AVDEN`, bit 16.
    pub const AVDEN: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `ALS`, bits 17..=18.
    pub const ALS: &FieldSpec = &super::REGISTERS[0].fields[7];
}

/// The fields of `CSR1`.
pub mod csr1 {
    use super::FieldSpec;
    /// `PVDO`, bit 4.
    pub const PVDO: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `ACTVOSRDY`, bit 13.
    pub const ACTVOSRDY: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `ACTVOS`, bits 14..=15.
    pub const ACTVOS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `AVDO`, bit 16.
    pub const AVDO: &FieldSpec = &super::REGISTERS[1].fields[3];
}

/// The fields of `CR2`.
pub mod cr2 {
    use super::FieldSpec;
    /// `BREN`, bit 0.
    pub const BREN: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `MONEN`, bit 4.
    pub const MONEN: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `BRRDY`, bit 16, read-only.
    pub const BRRDY: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `VBATL`, bit 20, read-only.
    pub const VBATL: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `VBATH`, bit 21, read-only.
    pub const VBATH: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `TEMPL`, bit 22, read-only.
    pub const TEMPL: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `TEMPH`, bit 23, read-only.
    pub const TEMPH: &FieldSpec = &super::REGISTERS[2].fields[6];
}

/// The fields of `CR3`.
pub mod cr3 {
    use super::FieldSpec;
    /// `BYPASS`, bit 0.
    pub const BYPASS: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `LDOEN`, bit 1.
    pub const LDOEN: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `SCUEN`, bit 2.
    pub const SCUEN: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `VBE`, bit 8.
    pub const VBE: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `VBRS`, bit 9.
    pub const VBRS: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `USB33DEN`, bit 24.
    pub const USB33DEN: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `USBREGEN`, bit 25.
    pub const USBREGEN: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `USB33RDY`, bit 26, read-only.
    pub const USB33RDY: &FieldSpec = &super::REGISTERS[3].fields[7];
}

/// The fields of `CPUCR`.
pub mod cpucr {
    use super::FieldSpec;
    /// `PDDS_D1`, bit 0.
    pub const PDDS_D1: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `PDDS_D2`, bit 1.
    pub const PDDS_D2: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `PDDS_D3`, bit 2.
    pub const PDDS_D3: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `STOPF`, bit 5, read-only.
    pub const STOPF: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `SBF`, bit 6, read-only.
    pub const SBF: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `SBF_D1`, bit 7, read-only.
    pub const SBF_D1: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `SBF_D2`, bit 8, read-only.
    pub const SBF_D2: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `CSSF`, bit 9.
    pub const CSSF: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `RUN_D3`, bit 11.
    pub const RUN_D3: &FieldSpec = &super::REGISTERS[4].fields[8];
}

/// The fields of `D3CR`.
pub mod d3cr {
    use super::FieldSpec;
    /// `VOSRDY`, bit 13, read-only.
    pub const VOSRDY: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `VOS`, bits 14..=15.
    pub const VOS: &FieldSpec = &super::REGISTERS[5].fields[1];
}

/// The fields of `WKUPCR`.
pub mod wkupcr {
    use super::FieldSpec;
    /// `WKUPC`, bits 0..=5.
    pub const WKUPC: &FieldSpec = &super::REGISTERS[6].fields[0];
}

/// The fields of `WKUPFR`.
pub mod wkupfr {
    use super::FieldSpec;
    /// `WKUPF1`, bit 0.
    pub const WKUPF1: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `WKUPF2`, bit 1.
    pub const WKUPF2: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `WKUPF3`, bit 2.
    pub const WKUPF3: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `WKUPF4`, bit 3.
    pub const WKUPF4: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `WKUPF5`, bit 4.
    pub const WKUPF5: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `WKUPF6`, bit 5.
    pub const WKUPF6: &FieldSpec = &super::REGISTERS[7].fields[5];
}

/// The fields of `WKUPEPR`.
pub mod wkupepr {
    use super::FieldSpec;
    /// `WKUPEN1`, bit 0.
    pub const WKUPEN1: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `WKUPEN2`, bit 1.
    pub const WKUPEN2: &FieldSpec = &super::REGISTERS[8].fields[1];
    /// `WKUPEN3`, bit 2.
    pub const WKUPEN3: &FieldSpec = &super::REGISTERS[8].fields[2];
    /// `WKUPEN4`, bit 3.
    pub const WKUPEN4: &FieldSpec = &super::REGISTERS[8].fields[3];
    /// `WKUPEN5`, bit 4.
    pub const WKUPEN5: &FieldSpec = &super::REGISTERS[8].fields[4];
    /// `WKUPEN6`, bit 5.
    pub const WKUPEN6: &FieldSpec = &super::REGISTERS[8].fields[5];
    /// `WKUPP1`, bit 8.
    pub const WKUPP1: &FieldSpec = &super::REGISTERS[8].fields[6];
    /// `WKUPP2`, bit 9.
    pub const WKUPP2: &FieldSpec = &super::REGISTERS[8].fields[7];
    /// `WKUPP3`, bit 10.
    pub const WKUPP3: &FieldSpec = &super::REGISTERS[8].fields[8];
    /// `WKUPP4`, bit 11.
    pub const WKUPP4: &FieldSpec = &super::REGISTERS[8].fields[9];
    /// `WKUPP5`, bit 12.
    pub const WKUPP5: &FieldSpec = &super::REGISTERS[8].fields[10];
    /// `WKUPP6`, bit 13.
    pub const WKUPP6: &FieldSpec = &super::REGISTERS[8].fields[11];
    /// `WKUPPUPD1`, bits 16..=17.
    pub const WKUPPUPD1: &FieldSpec = &super::REGISTERS[8].fields[12];
    /// `WKUPPUPD2`, bits 18..=19.
    pub const WKUPPUPD2: &FieldSpec = &super::REGISTERS[8].fields[13];
    /// `WKUPPUPD3`, bits 20..=21.
    pub const WKUPPUPD3: &FieldSpec = &super::REGISTERS[8].fields[14];
    /// `WKUPPUPD4`, bits 22..=23.
    pub const WKUPPUPD4: &FieldSpec = &super::REGISTERS[8].fields[15];
    /// `WKUPPUPD5`, bits 24..=25.
    pub const WKUPPUPD5: &FieldSpec = &super::REGISTERS[8].fields[16];
    /// `WKUPPUPD6`, bits 26..=27.
    pub const WKUPPUPD6: &FieldSpec = &super::REGISTERS[8].fields[17];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 9] = [
    RegisterSpec { name: "CR1", offset: 0x0, width: Width::W32, reset: 0xF000_C000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LPDS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PVDE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PLS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DBP", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLPS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SVOS", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AVDEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ALS", bit: 17, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSR1", offset: 0x4, width: Width::W32, reset: 0x0000_4000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PVDO", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACTVOSRDY", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ACTVOS", bit: 14, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AVDO", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BREN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MONEN", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BRRDY", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBATL", bit: 20, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBATH", bit: 21, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEMPL", bit: 22, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TEMPH", bit: 23, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR3", offset: 0xC, width: Width::W32, reset: 0x0000_0006, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "BYPASS", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LDOEN", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SCUEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VBRS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USB33DEN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USBREGEN", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "USB33RDY", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CPUCR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PDDS_D1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PDDS_D2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PDDS_D3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "STOPF", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBF", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBF_D1", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBF_D2", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSSF", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RUN_D3", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "D3CR", offset: 0x18, width: Width::W32, reset: 0x0000_4000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "VOSRDY", bit: 13, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VOS", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "WKUPCR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WKUPC", bit: 0, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "WKUPFR", offset: 0x24, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WKUPF1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPF2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPF3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPF4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPF5", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPF6", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "WKUPEPR", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "WKUPEN1", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPEN2", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPEN3", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPEN4", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPEN5", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPEN6", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP1", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP2", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP3", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP4", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP5", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPP6", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD1", bit: 16, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD2", bit: 18, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD3", bit: 20, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD4", bit: 22, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD5", bit: 24, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WKUPPUPD6", bit: 26, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];