rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SAI4` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `SAI_GCR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    SaiGcr = 0,
    /// `SAI_ACR1` at offset `0x4`, resets to `0x0000_0040`, read-write.
    SaiAcr1 = 1,
    /// `SAI_ACR2` at offset `0x8`, resets to `0x0000_0000`, read-write.
    SaiAcr2 = 2,
    /// `SAI_AFRCR` at offset `0xC`, resets to `0x0000_0007`, read-write.
    SaiAfrcr = 3,
    /// `SAI_ASLOTR` at offset `0x10`, resets to `0x0000_0000`, read-write.
    SaiAslotr = 4,
    /// `SAI_AIM` at offset `0x14`, resets to `0x0000_0000`, read-write.
    SaiAim = 5,
    /// `SAI_ASR` at offset `0x18`, resets to `0x0000_0008`, read-only.
    SaiAsr = 6,
    /// `SAI_ACLRFR` at offset `0x1C`, resets to `0x0000_0000`, write-only.
    SaiAclrfr = 7,
    /// `SAI_ADR` at offset `0x20`, resets to `0x0000_0000`, read-write.
    SaiAdr = 8,
    /// `SAI_BCR1` at offset `0x24`, resets to `0x0000_0040`, read-write.
    SaiBcr1 = 9,
    /// `SAI_BCR2` at offset `0x28`, resets to `0x0000_0000`, read-write.
    SaiBcr2 = 10,
    /// `SAI_BFRCR` at offset `0x2C`, resets to `0x0000_0007`, read-write.
    SaiBfrcr = 11,
    /// `SAI_BSLOTR` at offset `0x30`, resets to `0x0000_0000`, read-write.
    SaiBslotr = 12,
    /// `SAI_BIM` at offset `0x34`, resets to `0x0000_0000`, read-write.
    SaiBim = 13,
    /// `SAI_BSR` at offset `0x38`, resets to `0x0000_0008`, read-only.
    SaiBsr = 14,
    /// `SAI_BCLRFR` at offset `0x3C`, resets to `0x0000_0000`, write-only.
    SaiBclrfr = 15,
    /// `SAI_BDR` at offset `0x40`, resets to `0x0000_0000`, read-write.
    SaiBdr = 16,
    /// `SAI_PDMCR` at offset `0x44`, resets to `0x0000_0000`, read-write.
    SaiPdmcr = 17,
    /// `SAI_PDMDLY` at offset `0x48`, resets to `0x0000_0000`, read-write.
    SaiPdmdly = 18,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 19] = [Self::SaiGcr, Self::SaiAcr1, Self::SaiAcr2, Self::SaiAfrcr, Self::SaiAslotr, Self::SaiAim, Self::SaiAsr, Self::SaiAclrfr, Self::SaiAdr, Self::SaiBcr1, Self::SaiBcr2, Self::SaiBfrcr, Self::SaiBslotr, Self::SaiBim, Self::SaiBsr, Self::SaiBclrfr, Self::SaiBdr, Self::SaiPdmcr, Self::SaiPdmdly];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `SAI_GCR`.
pub mod sai_gcr {
    use super::FieldSpec;
    /// `SYNCIN`, bits 0..=1.
    pub const SYNCIN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `SYNCOUT`, bits 4..=5.
    pub const SYNCOUT: &FieldSpec = &super::REGISTERS[0].fields[1];
}

/// The fields of `SAI_ACR1`.
pub mod sai_acr1 {
    use super::FieldSpec;
    /// `MODE`, bits 0..=1.
    pub const MODE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `PRTCFG`, bits 2..=3.
    pub const PRTCFG: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `DS`, bits 5..=7.
    pub const DS: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `LSBFIRST`, bit 8.
    pub const LSBFIRST: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `CKSTR`, bit 9.
    pub const CKSTR: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `SYNCEN`, bits 10..=11.
    pub const SYNCEN: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `MONO`, bit 12.
    pub const MONO: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `OUTDRIV`, bit 13.
    pub const OUTDRIV: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `SAIXEN`, bit 16.
    pub const SAIXEN: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `DMAEN`, bit 17.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `NOMCK`, bit 19.
    pub const NOMCK: &FieldSpec = &super::REGISTERS[1].fields[10];
    /// `MCKDIV`, bits 20..=23.
    pub const MCKDIV: &FieldSpec = &super::REGISTERS[1].fields[11];
    /// `OSR`, bit 26.
    pub const OSR: &FieldSpec = &super::REGISTERS[1].fields[12];
}

/// The fields of `SAI_ACR2`.
pub mod sai_acr2 {
    use super::FieldSpec;
    /// `FTH`, bits 0..=2.
    pub const FTH: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `FFLUSH`, bit 3, write-only.
    pub const FFLUSH: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `TRIS`, bit 4.
    pub const TRIS: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `MUTE`, bit 5.
    pub const MUTE: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `MUTEVAL`, bit 6.
    pub const MUTEVAL: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `MUTECNT`, bits 7..=12.
    pub const MUTECNT: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `CPL`, bit 13.
    pub const CPL: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `COMP`, bits 14..=15.
    pub const COMP: &FieldSpec = &super::REGISTERS[2].fields[7];
}

/// The fields of `SAI_AFRCR`.
pub mod sai_afrcr {
    use super::FieldSpec;
    /// `FRL`, bits 0..=7.
    pub const FRL: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `FSALL`, bits 8..=14.
    pub const FSALL: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `FSDEF`, bit 16, read-only.
    pub const FSDEF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `FSPOL`, bit 17.
    pub const FSPOL: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `FSOFF`, bit 18.
    pub const FSOFF: &FieldSpec = &super::REGISTERS[3].fields[4];
}

/// The fields of `SAI_ASLOTR`.
pub mod sai_aslotr {
    use super::FieldSpec;
    /// `FBOFF`, bits 0..=4.
    pub const FBOFF: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `SLOTSZ`, bits 6..=7.
    pub const SLOTSZ: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `NBSLOT`, bits 8..=11.
    pub const NBSLOT: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `SLOTEN`, bits 16..=31.
    pub const SLOTEN: &FieldSpec = &super::REGISTERS[4].fields[3];
}

/// The fields of `SAI_AIM`.
pub mod sai_aim {
    use super::FieldSpec;
    /// `OVRUDRIE`, bit 0.
    pub const OVRUDRIE: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `MUTEDETIE`, bit 1.
    pub const MUTEDETIE: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `WCKCFGIE`, bit 2.
    pub const WCKCFGIE: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `FREQIE`, bit 3.
    pub const FREQIE: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `CNRDYIE`, bit 4.
    pub const CNRDYIE: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `AFSDETIE`, bit 5.
    pub const AFSDETIE: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `LFSDETIE`, bit 6.
    pub const LFSDETIE: &FieldSpec = &super::REGISTERS[5].fields[6];
}

/// The fields of `SAI_ASR`.
pub mod sai_asr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `FREQ`, bit 3.
    pub const FREQ: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `AFSDET`, bit 5.
    pub const AFSDET: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `FLVL`, bits 16..=18.
    pub const FLVL: &FieldSpec = &super::REGISTERS[6].fields[7];
}

/// The fields of `SAI_ACLRFR`.
pub mod sai_aclrfr {
    use super::FieldSpec;
    /// `COVRUDR`, bit 0.
    pub const COVRUDR: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `CMUTEDET`, bit 1.
    pub const CMUTEDET: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `CWCKCFG`, bit 2.
    pub const CWCKCFG: &FieldSpec = &super::REGISTERS[7].fields[2];
    /// `CCNRDY`, bit 4.
    pub const CCNRDY: &FieldSpec = &super::REGISTERS[7].fields[3];
    /// `CAFSDET`, bit 5.
    pub const CAFSDET: &FieldSpec = &super::REGISTERS[7].fields[4];
    /// `CLFSDET`, bit 6.
    pub const CLFSDET: &FieldSpec = &super::REGISTERS[7].fields[5];
}

/// The fields of `SAI_ADR`.
pub mod sai_adr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=31.
    pub const DATA: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `SAI_BCR1`.
pub mod sai_bcr1 {
    use super::FieldSpec;
    /// `MODE`, bits 0..=1.
    pub const MODE: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `PRTCFG`, bits 2..=3.
    pub const PRTCFG: &FieldSpec = &super::REGISTERS[9].fields[1];
    /// `DS`, bits 5..=7.
    pub const DS: &FieldSpec = &super::REGISTERS[9].fields[2];
    /// `LSBFIRST`, bit 8.
    pub const LSBFIRST: &FieldSpec = &super::REGISTERS[9].fields[3];
    /// `CKSTR`, bit 9.
    pub const CKSTR: &FieldSpec = &super::REGISTERS[9].fields[4];
    /// `SYNCEN`, bits 10..=11.
    pub const SYNCEN: &FieldSpec = &super::REGISTERS[9].fields[5];
    /// `MONO`, bit 12.
    pub const MONO: &FieldSpec = &super::REGISTERS[9].fields[6];
    /// `OUTDRIV`, bit 13.
    pub const OUTDRIV: &FieldSpec = &super::REGISTERS[9].fields[7];
    /// `SAIXEN`, bit 16.
    pub const SAIXEN: &FieldSpec = &super::REGISTERS[9].fields[8];
    /// `DMAEN`, bit 17.
    pub const DMAEN: &FieldSpec = &super::REGISTERS[9].fields[9];
    /// `NOMCK`, bit 19.
    pub const NOMCK: &FieldSpec = &super::REGISTERS[9].fields[10];
    /// `MCKDIV`, bits 20..=23.
    pub const MCKDIV: &FieldSpec = &super::REGISTERS[9].fields[11];
    /// `OSR`, bit 26.
    pub const OSR: &FieldSpec = &super::REGISTERS[9].fields[12];
}

/// The fields of `SAI_BCR2`.
pub mod sai_bcr2 {
    use super::FieldSpec;
    /// `FTH`, bits 0..=2.
    pub const FTH: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `FFLUSH`, bit 3, write-only.
    pub const FFLUSH: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `TRIS`, bit 4.
    pub const TRIS: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `MUTE`, bit 5.
    pub const MUTE: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `MUTEVAL`, bit 6.
    pub const MUTEVAL: &FieldSpec = &super::REGISTERS[10].fields[4];
    /// `MUTECNT`, bits 7..=12.
    pub const MUTECNT: &FieldSpec = &super::REGISTERS[10].fields[5];
    /// `CPL`, bit 13.
    pub const CPL: &FieldSpec = &super::REGISTERS[10].fields[6];
    /// `COMP`, bits 14..=15.
    pub const COMP: &FieldSpec = &super::REGISTERS[10].fields[7];
}

/// The fields of `SAI_BFRCR`.
pub mod sai_bfrcr {
    use super::FieldSpec;
    /// `FRL`, bits 0..=7.
    pub const FRL: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `FSALL`, bits 8..=14.
    pub const FSALL: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `FSDEF`, bit 16, read-only.
    pub const FSDEF: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `FSPOL`, bit 17.
    pub const FSPOL: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `FSOFF`, bit 18.
    pub const FSOFF: &FieldSpec = &super::REGISTERS[11].fields[4];
}

/// The fields of `SAI_BSLOTR`.
pub mod sai_bslotr {
    use super::FieldSpec;
    /// `FBOFF`, bits 0..=4.
    pub const FBOFF: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `SLOTSZ`, bits 6..=7.
    pub const SLOTSZ: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `NBSLOT`, bits 8..=11.
    pub const NBSLOT: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `SLOTEN`, bits 16..=31.
    pub const SLOTEN: &FieldSpec = &super::REGISTERS[12].fields[3];
}

/// The fields of `SAI_BIM`.
pub mod sai_bim {
    use super::FieldSpec;
    /// `OVRUDRIE`, bit 0.
    pub const OVRUDRIE: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `MUTEDETIE`, bit 1.
    pub const MUTEDETIE: &FieldSpec = &super::REGISTERS[13].fields[1];
    /// `WCKCFGIE`, bit 2.
    pub const WCKCFGIE: &FieldSpec = &super::REGISTERS[13].fields[2];
    /// `FREQIE`, bit 3.
    pub const FREQIE: &FieldSpec = &super::REGISTERS[13].fields[3];
    /// `CNRDYIE`, bit 4.
    pub const CNRDYIE: &FieldSpec = &super::REGISTERS[13].fields[4];
    /// `AFSDETIE`, bit 5.
    pub const AFSDETIE: &FieldSpec = &super::REGISTERS[13].fields[5];
    /// `LFSDETIE`, bit 6.
    pub const LFSDETIE: &FieldSpec = &super::REGISTERS[13].fields[6];
}

/// The fields of `SAI_BSR`.
pub mod sai_bsr {
    use super::FieldSpec;
    /// `OVRUDR`, bit 0.
    pub const OVRUDR: &FieldSpec = &super::REGISTERS[14].fields[0];
    /// `MUTEDET`, bit 1.
    pub const MUTEDET: &FieldSpec = &super::REGISTERS[14].fields[1];
    /// `WCKCFG`, bit 2.
    pub const WCKCFG: &FieldSpec = &super::REGISTERS[14].fields[2];
    /// `FREQ`, bit 3.
    pub const FREQ: &FieldSpec = &super::REGISTERS[14].fields[3];
    /// `CNRDY`, bit 4.
    pub const CNRDY: &FieldSpec = &super::REGISTERS[14].fields[4];
    /// `AFSDET`, bit 5.
    pub const AFSDET: &FieldSpec = &super::REGISTERS[14].fields[5];
    /// `LFSDET`, bit 6.
    pub const LFSDET: &FieldSpec = &super::REGISTERS[14].fields[6];
    /// `FLVL`, bits 16..=18.
    pub const FLVL: &FieldSpec = &super::REGISTERS[14].fields[7];
}

/// The fields of `SAI_BCLRFR`.
pub mod sai_bclrfr {
    use super::FieldSpec;
    /// `COVRUDR`, bit 0.
    pub const COVRUDR: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `CMUTEDET`, bit 1.
    pub const CMUTEDET: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `CWCKCFG`, bit 2.
    pub const CWCKCFG: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `CCNRDY`, bit 4.
    pub const CCNRDY: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `CAFSDET`, bit 5.
    pub const CAFSDET: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `CLFSDET`, bit 6.
    pub const CLFSDET: &FieldSpec = &super::REGISTERS[15].fields[5];
}

/// The fields of `SAI_BDR`.
pub mod sai_bdr {
    use super::FieldSpec;
    /// `DATA`, bits 0..=31.
    pub const DATA: &FieldSpec = &super::REGISTERS[16].fields[0];
}

/// The fields of `SAI_PDMCR`.
pub mod sai_pdmcr {
    use super::FieldSpec;
    /// `PDMEN`, bit 0.
    pub const PDMEN: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `MICNBR`, bits 4..=5.
    pub const MICNBR: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `CKEN1`, bit 8.
    pub const CKEN1: &FieldSpec = &super::REGISTERS[17].fields[2];
    /// `CKEN2`, bit 9.
    pub const CKEN2: &FieldSpec = &super::REGISTERS[17].fields[3];
    /// `CKEN3`, bit 10.
    pub const CKEN3: &FieldSpec = &super::REGISTERS[17].fields[4];
    /// `CKEN4`, bit 11.
    pub const CKEN4: &FieldSpec = &super::REGISTERS[17].fields[5];
}

/// The fields of `SAI_PDMDLY`.
pub mod sai_pdmdly {
    use super::FieldSpec;
    /// `DLYM1L`, bits 0..=2.
    pub const DLYM1L: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `DLYM1R`, bits 4..=6.
    pub const DLYM1R: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `DLYM2L`, bits 8..=10.
    pub const DLYM2L: &FieldSpec = &super::REGISTERS[18].fields[2];
    /// `DLYM2R`, bits 12..=14.
    pub const DLYM2R: &FieldSpec = &super::REGISTERS[18].fields[3];
    /// `DLYM3L`, bits 16..=18.
    pub const DLYM3L: &FieldSpec = &super::REGISTERS[18].fields[4];
    /// `DLYM3R`, bits 20..=22.
    pub const DLYM3R: &FieldSpec = &super::REGISTERS[18].fields[5];
    /// `DLYM4L`, bits 24..=26.
    pub const DLYM4L: &FieldSpec = &super::REGISTERS[18].fields[6];
    /// `DLYM4R`, bits 28..=30.
    pub const DLYM4R: &FieldSpec = &super::REGISTERS[18].fields[7];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 19] = [
    RegisterSpec { name: "SAI_GCR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SYNCIN", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCOUT", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ACR1", offset: 0x4, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRTCFG", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCEN", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MONO", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OUTDRIV", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NOMCK", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSR", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ACR2", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FFLUSH", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEVAL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTECNT", bit: 7, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPL", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMP", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_AFRCR", offset: 0xC, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRL", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSALL", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSDEF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSPOL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSOFF", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ASLOTR", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FBOFF", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTSZ", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBSLOT", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTEN", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_AIM", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDRIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDETIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFGIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDYIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDETIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDETIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ASR", offset: 0x18, width: Width::W32, reset: 0x0000_0008, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQ", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDET", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLVL", bit: 16, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ACLRFR", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "COVRUDR", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMUTEDET", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CWCKCFG", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCNRDY", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAFSDET", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLFSDET", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_ADR", offset: 0x20, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BCR1", offset: 0x24, width: Width::W32, reset: 0x0000_0040, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MODE", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PRTCFG", bit: 2, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DS", bit: 5, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSBFIRST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSTR", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCEN", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MONO", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OUTDRIV", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SAIXEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DMAEN", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NOMCK", bit: 19, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MCKDIV", bit: 20, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSR", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BCR2", offset: 0x28, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FTH", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FFLUSH", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TRIS", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEVAL", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTECNT", bit: 7, width: 6, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CPL", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "COMP", bit: 14, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BFRCR", offset: 0x2C, width: Width::W32, reset: 0x0000_0007, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FRL", bit: 0, width: 8, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSALL", bit: 8, width: 7, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSDEF", bit: 16, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSPOL", bit: 17, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FSOFF", bit: 18, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BSLOTR", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "FBOFF", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTSZ", bit: 6, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBSLOT", bit: 8, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SLOTEN", bit: 16, width: 16, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BIM", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDRIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDETIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFGIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDYIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDETIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDETIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BSR", offset: 0x38, width: Width::W32, reset: 0x0000_0008, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OVRUDR", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MUTEDET", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WCKCFG", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FREQ", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CNRDY", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AFSDET", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LFSDET", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FLVL", bit: 16, width: 3, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BCLRFR", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "COVRUDR", bit: 0, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CMUTEDET", bit: 1, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CWCKCFG", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CCNRDY", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CAFSDET", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CLFSDET", bit: 6, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_BDR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DATA", bit: 0, width: 32, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_PDMCR", offset: 0x44, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PDMEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MICNBR", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKEN1", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKEN2", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKEN3", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKEN4", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SAI_PDMDLY", offset: 0x48, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DLYM1L", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM1R", bit: 4, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM2L", bit: 8, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM2R", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM3L", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM3R", bit: 20, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM4L", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DLYM4R", bit: 28, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];