rigless 0.3.0

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `ADC3` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `ISR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Isr = 0,
    /// `IER` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Ier = 1,
    /// `CR` at offset `0x8`, resets to `0x0000_0000`, read-write.
    Cr = 2,
    /// `CFGR` at offset `0xC`, resets to `0x0000_0000`, read-write.
    Cfgr = 3,
    /// `CFGR2` at offset `0x10`, resets to `0x0000_0000`, read-write.
    Cfgr2 = 4,
    /// `SMPR1` at offset `0x14`, resets to `0x0000_0000`, read-write.
    Smpr1 = 5,
    /// `SMPR2` at offset `0x18`, resets to `0x0000_0000`, read-write.
    Smpr2 = 6,
    /// `PCSEL` at offset `0x1C`, resets to `0x0000_0000`, read-write.
    Pcsel = 7,
    /// `LTR1` at offset `0x20`, resets to `0x0FFF_0000`, read-write.
    Ltr1 = 8,
    /// `LHTR1` at offset `0x24`, resets to `0x0FFF_0000`, read-write.
    Lhtr1 = 9,
    /// `SQR1` at offset `0x30`, resets to `0x0000_0000`, read-write.
    Sqr1 = 10,
    /// `SQR2` at offset `0x34`, resets to `0x0000_0000`, read-write.
    Sqr2 = 11,
    /// `SQR3` at offset `0x38`, resets to `0x0000_0000`, read-write.
    Sqr3 = 12,
    /// `SQR4` at offset `0x3C`, resets to `0x0000_0000`, read-write.
    Sqr4 = 13,
    /// `DR` at offset `0x40`, resets to `0x0000_0000`, read-only.
    Dr = 14,
    /// `JSQR` at offset `0x4C`, resets to `0x0000_0000`, read-write.
    Jsqr = 15,
    /// `OFR1` at offset `0x60`, resets to `0x0000_0000`, read-write.
    Ofr1 = 16,
    /// `OFR2` at offset `0x64`, resets to `0x0000_0000`, read-write.
    Ofr2 = 17,
    /// `OFR3` at offset `0x68`, resets to `0x0000_0000`, read-write.
    Ofr3 = 18,
    /// `OFR4` at offset `0x6C`, resets to `0x0000_0000`, read-write.
    Ofr4 = 19,
    /// `JDR1` at offset `0x80`, resets to `0x0000_0000`, read-only.
    Jdr1 = 20,
    /// `JDR2` at offset `0x84`, resets to `0x0000_0000`, read-only.
    Jdr2 = 21,
    /// `JDR3` at offset `0x88`, resets to `0x0000_0000`, read-only.
    Jdr3 = 22,
    /// `JDR4` at offset `0x8C`, resets to `0x0000_0000`, read-only.
    Jdr4 = 23,
    /// `AWD2CR` at offset `0xA0`, resets to `0x0000_0000`, read-write.
    Awd2cr = 24,
    /// `AWD3CR` at offset `0xA4`, resets to `0x0000_0000`, read-write.
    Awd3cr = 25,
    /// `LTR2` at offset `0xB0`, resets to `0x0000_0000`, read-write.
    Ltr2 = 26,
    /// `HTR2` at offset `0xB4`, resets to `0x0000_0000`, read-write.
    Htr2 = 27,
    /// `LTR3` at offset `0xB8`, resets to `0x0000_0000`, read-write.
    Ltr3 = 28,
    /// `HTR3` at offset `0xBC`, resets to `0x0000_0000`, read-write.
    Htr3 = 29,
    /// `DIFSEL` at offset `0xC0`, resets to `0x0000_0000`, read-write.
    Difsel = 30,
    /// `CALFACT` at offset `0xC4`, resets to `0x0000_0000`, read-write.
    Calfact = 31,
    /// `CALFACT2` at offset `0xC8`, resets to `0x0000_0000`, read-write.
    Calfact2 = 32,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 33] = [Self::Isr, Self::Ier, Self::Cr, Self::Cfgr, Self::Cfgr2, Self::Smpr1, Self::Smpr2, Self::Pcsel, Self::Ltr1, Self::Lhtr1, Self::Sqr1, Self::Sqr2, Self::Sqr3, Self::Sqr4, Self::Dr, Self::Jsqr, Self::Ofr1, Self::Ofr2, Self::Ofr3, Self::Ofr4, Self::Jdr1, Self::Jdr2, Self::Jdr3, Self::Jdr4, Self::Awd2cr, Self::Awd3cr, Self::Ltr2, Self::Htr2, Self::Ltr3, Self::Htr3, Self::Difsel, Self::Calfact, Self::Calfact2];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `ISR`.
pub mod isr {
    use super::FieldSpec;
    /// `ADRDY`, bit 0.
    pub const ADRDY: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `EOSMP`, bit 1.
    pub const EOSMP: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `EOC`, bit 2.
    pub const EOC: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `EOS`, bit 3.
    pub const EOS: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `OVR`, bit 4.
    pub const OVR: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `JEOC`, bit 5.
    pub const JEOC: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `JEOS`, bit 6.
    pub const JEOS: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `AWD1`, bit 7.
    pub const AWD1: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `AWD2`, bit 8.
    pub const AWD2: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `AWD3`, bit 9.
    pub const AWD3: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `JQOVF`, bit 10.
    pub const JQOVF: &FieldSpec = &super::REGISTERS[0].fields[10];
}

/// The fields of `IER`.
pub mod ier {
    use super::FieldSpec;
    /// `ADRDYIE`, bit 0.
    pub const ADRDYIE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `EOSMPIE`, bit 1.
    pub const EOSMPIE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `EOCIE`, bit 2.
    pub const EOCIE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `EOSIE`, bit 3.
    pub const EOSIE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `OVRIE`, bit 4.
    pub const OVRIE: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `JEOCIE`, bit 5.
    pub const JEOCIE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `JEOSIE`, bit 6.
    pub const JEOSIE: &FieldSpec = &super::REGISTERS[1].fields[6];
    /// `AWD1IE`, bit 7.
    pub const AWD1IE: &FieldSpec = &super::REGISTERS[1].fields[7];
    /// `AWD2IE`, bit 8.
    pub const AWD2IE: &FieldSpec = &super::REGISTERS[1].fields[8];
    /// `AWD3IE`, bit 9.
    pub const AWD3IE: &FieldSpec = &super::REGISTERS[1].fields[9];
    /// `JQOVFIE`, bit 10.
    pub const JQOVFIE: &FieldSpec = &super::REGISTERS[1].fields[10];
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `ADEN`, bit 0.
    pub const ADEN: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `ADDIS`, bit 1.
    pub const ADDIS: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `ADSTART`, bit 2.
    pub const ADSTART: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `JADSTART`, bit 3.
    pub const JADSTART: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `ADSTP`, bit 4.
    pub const ADSTP: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `JADSTP`, bit 5.
    pub const JADSTP: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `BOOST`, bit 8.
    pub const BOOST: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `ADCALLIN`, bit 16.
    pub const ADCALLIN: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `LINCALRDYW1`, bit 22.
    pub const LINCALRDYW1: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `LINCALRDYW2`, bit 23.
    pub const LINCALRDYW2: &FieldSpec = &super::REGISTERS[2].fields[9];
    /// `LINCALRDYW3`, bit 24.
    pub const LINCALRDYW3: &FieldSpec = &super::REGISTERS[2].fields[10];
    /// `LINCALRDYW4`, bit 25.
    pub const LINCALRDYW4: &FieldSpec = &super::REGISTERS[2].fields[11];
    /// `LINCALRDYW5`, bit 26.
    pub const LINCALRDYW5: &FieldSpec = &super::REGISTERS[2].fields[12];
    /// `LINCALRDYW6`, bit 27.
    pub const LINCALRDYW6: &FieldSpec = &super::REGISTERS[2].fields[13];
    /// `ADVREGEN`, bit 28.
    pub const ADVREGEN: &FieldSpec = &super::REGISTERS[2].fields[14];
    /// `DEEPPWD`, bit 29.
    pub const DEEPPWD: &FieldSpec = &super::REGISTERS[2].fields[15];
    /// `ADCALDIF`, bit 30.
    pub const ADCALDIF: &FieldSpec = &super::REGISTERS[2].fields[16];
    /// `ADCAL`, bit 31.
    pub const ADCAL: &FieldSpec = &super::REGISTERS[2].fields[17];
}

/// The fields of `CFGR`.
pub mod cfgr {
    use super::FieldSpec;
    /// `DMNGT`, bits 0..=1.
    pub const DMNGT: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `RES`, bits 2..=4.
    pub const RES: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `EXTSEL`, bits 5..=9.
    pub const EXTSEL: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `EXTEN`, bits 10..=11.
    pub const EXTEN: &FieldSpec = &super::REGISTERS[3].fields[3];
    /// `OVRMOD`, bit 12.
    pub const OVRMOD: &FieldSpec = &super::REGISTERS[3].fields[4];
    /// `CONT`, bit 13.
    pub const CONT: &FieldSpec = &super::REGISTERS[3].fields[5];
    /// `AUTDLY`, bit 14.
    pub const AUTDLY: &FieldSpec = &super::REGISTERS[3].fields[6];
    /// `DISCEN`, bit 16.
    pub const DISCEN: &FieldSpec = &super::REGISTERS[3].fields[7];
    /// `DISCNUM`, bits 17..=19.
    pub const DISCNUM: &FieldSpec = &super::REGISTERS[3].fields[8];
    /// `JDISCEN`, bit 20.
    pub const JDISCEN: &FieldSpec = &super::REGISTERS[3].fields[9];
    /// `JQM`, bit 21.
    pub const JQM: &FieldSpec = &super::REGISTERS[3].fields[10];
    /// `AWD1SGL`, bit 22.
    pub const AWD1SGL: &FieldSpec = &super::REGISTERS[3].fields[11];
    /// `AWD1EN`, bit 23.
    pub const AWD1EN: &FieldSpec = &super::REGISTERS[3].fields[12];
    /// `JAWD1EN`, bit 24.
    pub const JAWD1EN: &FieldSpec = &super::REGISTERS[3].fields[13];
    /// `JAUTO`, bit 25.
    pub const JAUTO: &FieldSpec = &super::REGISTERS[3].fields[14];
    /// `AWDCH1CH`, bits 26..=30.
    pub const AWDCH1CH: &FieldSpec = &super::REGISTERS[3].fields[15];
    /// `JQDIS`, bit 31.
    pub const JQDIS: &FieldSpec = &super::REGISTERS[3].fields[16];
}

/// The fields of `CFGR2`.
pub mod cfgr2 {
    use super::FieldSpec;
    /// `ROVSE`, bit 0.
    pub const ROVSE: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `JOVSE`, bit 1.
    pub const JOVSE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `OVSS`, bits 5..=8.
    pub const OVSS: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `TROVS`, bit 9.
    pub const TROVS: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `ROVSM`, bit 10.
    pub const ROVSM: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `RSHIFT1`, bit 11.
    pub const RSHIFT1: &FieldSpec = &super::REGISTERS[4].fields[5];
    /// `RSHIFT2`, bit 12.
    pub const RSHIFT2: &FieldSpec = &super::REGISTERS[4].fields[6];
    /// `RSHIFT3`, bit 13.
    pub const RSHIFT3: &FieldSpec = &super::REGISTERS[4].fields[7];
    /// `RSHIFT4`, bit 14.
    pub const RSHIFT4: &FieldSpec = &super::REGISTERS[4].fields[8];
    /// `OSR`, bits 16..=25.
    pub const OSR: &FieldSpec = &super::REGISTERS[4].fields[9];
    /// `LSHIFT`, bits 28..=31.
    pub const LSHIFT: &FieldSpec = &super::REGISTERS[4].fields[10];
}

/// The fields of `SMPR1`.
pub mod smpr1 {
    use super::FieldSpec;
    /// `SMP1`, bits 3..=5.
    pub const SMP1: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `SMP2`, bits 6..=8.
    pub const SMP2: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `SMP3`, bits 9..=11.
    pub const SMP3: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `SMP4`, bits 12..=14.
    pub const SMP4: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `SMP5`, bits 15..=17.
    pub const SMP5: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `SMP6`, bits 18..=20.
    pub const SMP6: &FieldSpec = &super::REGISTERS[5].fields[5];
    /// `SMP7`, bits 21..=23.
    pub const SMP7: &FieldSpec = &super::REGISTERS[5].fields[6];
    /// `SMP8`, bits 24..=26.
    pub const SMP8: &FieldSpec = &super::REGISTERS[5].fields[7];
    /// `SMP9`, bits 27..=29.
    pub const SMP9: &FieldSpec = &super::REGISTERS[5].fields[8];
}

/// The fields of `SMPR2`.
pub mod smpr2 {
    use super::FieldSpec;
    /// `SMP10`, bits 0..=2.
    pub const SMP10: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `SMP11`, bits 3..=5.
    pub const SMP11: &FieldSpec = &super::REGISTERS[6].fields[1];
    /// `SMP12`, bits 6..=8.
    pub const SMP12: &FieldSpec = &super::REGISTERS[6].fields[2];
    /// `SMP13`, bits 9..=11.
    pub const SMP13: &FieldSpec = &super::REGISTERS[6].fields[3];
    /// `SMP14`, bits 12..=14.
    pub const SMP14: &FieldSpec = &super::REGISTERS[6].fields[4];
    /// `SMP15`, bits 15..=17.
    pub const SMP15: &FieldSpec = &super::REGISTERS[6].fields[5];
    /// `SMP16`, bits 18..=20.
    pub const SMP16: &FieldSpec = &super::REGISTERS[6].fields[6];
    /// `SMP17`, bits 21..=23.
    pub const SMP17: &FieldSpec = &super::REGISTERS[6].fields[7];
    /// `SMP18`, bits 24..=26.
    pub const SMP18: &FieldSpec = &super::REGISTERS[6].fields[8];
    /// `SMP19`, bits 27..=29.
    pub const SMP19: &FieldSpec = &super::REGISTERS[6].fields[9];
}

/// The fields of `PCSEL`.
pub mod pcsel {
    use super::FieldSpec;
    /// `PCSEL`, bits 0..=19.
    pub const PCSEL: &FieldSpec = &super::REGISTERS[7].fields[0];
}

/// The fields of `LTR1`.
pub mod ltr1 {
    use super::FieldSpec;
    /// `LTR1`, bits 0..=25.
    pub const LTR1: &FieldSpec = &super::REGISTERS[8].fields[0];
}

/// The fields of `LHTR1`.
pub mod lhtr1 {
    use super::FieldSpec;
    /// `LHTR1`, bits 0..=25.
    pub const LHTR1: &FieldSpec = &super::REGISTERS[9].fields[0];
}

/// The fields of `SQR1`.
pub mod sqr1 {
    use super::FieldSpec;
    /// `L3`, bits 0..=3.
    pub const L3: &FieldSpec = &super::REGISTERS[10].fields[0];
    /// `SQ1`, bits 6..=10.
    pub const SQ1: &FieldSpec = &super::REGISTERS[10].fields[1];
    /// `SQ2`, bits 12..=16.
    pub const SQ2: &FieldSpec = &super::REGISTERS[10].fields[2];
    /// `SQ3`, bits 18..=22.
    pub const SQ3: &FieldSpec = &super::REGISTERS[10].fields[3];
    /// `SQ4`, bits 24..=28.
    pub const SQ4: &FieldSpec = &super::REGISTERS[10].fields[4];
}

/// The fields of `SQR2`.
pub mod sqr2 {
    use super::FieldSpec;
    /// `SQ5`, bits 0..=4.
    pub const SQ5: &FieldSpec = &super::REGISTERS[11].fields[0];
    /// `SQ6`, bits 6..=10.
    pub const SQ6: &FieldSpec = &super::REGISTERS[11].fields[1];
    /// `SQ7`, bits 12..=16.
    pub const SQ7: &FieldSpec = &super::REGISTERS[11].fields[2];
    /// `SQ8`, bits 18..=22.
    pub const SQ8: &FieldSpec = &super::REGISTERS[11].fields[3];
    /// `SQ9`, bits 24..=28.
    pub const SQ9: &FieldSpec = &super::REGISTERS[11].fields[4];
}

/// The fields of `SQR3`.
pub mod sqr3 {
    use super::FieldSpec;
    /// `SQ10`, bits 0..=4.
    pub const SQ10: &FieldSpec = &super::REGISTERS[12].fields[0];
    /// `SQ11`, bits 6..=10.
    pub const SQ11: &FieldSpec = &super::REGISTERS[12].fields[1];
    /// `SQ12`, bits 12..=16.
    pub const SQ12: &FieldSpec = &super::REGISTERS[12].fields[2];
    /// `SQ13`, bits 18..=22.
    pub const SQ13: &FieldSpec = &super::REGISTERS[12].fields[3];
    /// `SQ14`, bits 24..=28.
    pub const SQ14: &FieldSpec = &super::REGISTERS[12].fields[4];
}

/// The fields of `SQR4`.
pub mod sqr4 {
    use super::FieldSpec;
    /// `SQ15`, bits 0..=4.
    pub const SQ15: &FieldSpec = &super::REGISTERS[13].fields[0];
    /// `SQ16`, bits 6..=10.
    pub const SQ16: &FieldSpec = &super::REGISTERS[13].fields[1];
}

/// The fields of `DR`.
pub mod dr {
    use super::FieldSpec;
    /// `RDATA`, bits 0..=15.
    pub const RDATA: &FieldSpec = &super::REGISTERS[14].fields[0];
}

/// The fields of `JSQR`.
pub mod jsqr {
    use super::FieldSpec;
    /// `JL`, bits 0..=1.
    pub const JL: &FieldSpec = &super::REGISTERS[15].fields[0];
    /// `JEXTSEL`, bits 2..=6.
    pub const JEXTSEL: &FieldSpec = &super::REGISTERS[15].fields[1];
    /// `JEXTEN`, bits 7..=8.
    pub const JEXTEN: &FieldSpec = &super::REGISTERS[15].fields[2];
    /// `JSQ1`, bits 9..=13.
    pub const JSQ1: &FieldSpec = &super::REGISTERS[15].fields[3];
    /// `JSQ2`, bits 15..=19.
    pub const JSQ2: &FieldSpec = &super::REGISTERS[15].fields[4];
    /// `JSQ3`, bits 21..=25.
    pub const JSQ3: &FieldSpec = &super::REGISTERS[15].fields[5];
    /// `JSQ4`, bits 27..=31.
    pub const JSQ4: &FieldSpec = &super::REGISTERS[15].fields[6];
}

/// The fields of `OFR1`.
pub mod ofr1 {
    use super::FieldSpec;
    /// `OFFSET1`, bits 0..=25.
    pub const OFFSET1: &FieldSpec = &super::REGISTERS[16].fields[0];
    /// `OFFSET1_CH`, bits 26..=30.
    pub const OFFSET1_CH: &FieldSpec = &super::REGISTERS[16].fields[1];
    /// `SSATE`, bit 31.
    pub const SSATE: &FieldSpec = &super::REGISTERS[16].fields[2];
}

/// The fields of `OFR2`.
pub mod ofr2 {
    use super::FieldSpec;
    /// `OFFSET1`, bits 0..=25.
    pub const OFFSET1: &FieldSpec = &super::REGISTERS[17].fields[0];
    /// `OFFSET1_CH`, bits 26..=30.
    pub const OFFSET1_CH: &FieldSpec = &super::REGISTERS[17].fields[1];
    /// `SSATE`, bit 31.
    pub const SSATE: &FieldSpec = &super::REGISTERS[17].fields[2];
}

/// The fields of `OFR3`.
pub mod ofr3 {
    use super::FieldSpec;
    /// `OFFSET1`, bits 0..=25.
    pub const OFFSET1: &FieldSpec = &super::REGISTERS[18].fields[0];
    /// `OFFSET1_CH`, bits 26..=30.
    pub const OFFSET1_CH: &FieldSpec = &super::REGISTERS[18].fields[1];
    /// `SSATE`, bit 31.
    pub const SSATE: &FieldSpec = &super::REGISTERS[18].fields[2];
}

/// The fields of `OFR4`.
pub mod ofr4 {
    use super::FieldSpec;
    /// `OFFSET1`, bits 0..=25.
    pub const OFFSET1: &FieldSpec = &super::REGISTERS[19].fields[0];
    /// `OFFSET1_CH`, bits 26..=30.
    pub const OFFSET1_CH: &FieldSpec = &super::REGISTERS[19].fields[1];
    /// `SSATE`, bit 31.
    pub const SSATE: &FieldSpec = &super::REGISTERS[19].fields[2];
}

/// The fields of `JDR1`.
pub mod jdr1 {
    use super::FieldSpec;
    /// `JDATA1`, bits 0..=31.
    pub const JDATA1: &FieldSpec = &super::REGISTERS[20].fields[0];
}

/// The fields of `JDR2`.
pub mod jdr2 {
    use super::FieldSpec;
    /// `JDATA2`, bits 0..=31.
    pub const JDATA2: &FieldSpec = &super::REGISTERS[21].fields[0];
}

/// The fields of `JDR3`.
pub mod jdr3 {
    use super::FieldSpec;
    /// `JDATA3`, bits 0..=31.
    pub const JDATA3: &FieldSpec = &super::REGISTERS[22].fields[0];
}

/// The fields of `JDR4`.
pub mod jdr4 {
    use super::FieldSpec;
    /// `JDATA4`, bits 0..=31.
    pub const JDATA4: &FieldSpec = &super::REGISTERS[23].fields[0];
}

/// The fields of `AWD2CR`.
pub mod awd2cr {
    use super::FieldSpec;
    /// `AWD2CH`, bits 0..=19.
    pub const AWD2CH: &FieldSpec = &super::REGISTERS[24].fields[0];
}

/// The fields of `AWD3CR`.
pub mod awd3cr {
    use super::FieldSpec;
    /// `AWD3CH`, bits 1..=20.
    pub const AWD3CH: &FieldSpec = &super::REGISTERS[25].fields[0];
}

/// The fields of `LTR2`.
pub mod ltr2 {
    use super::FieldSpec;
    /// `LTR2`, bits 0..=25.
    pub const LTR2: &FieldSpec = &super::REGISTERS[26].fields[0];
}

/// The fields of `HTR2`.
pub mod htr2 {
    use super::FieldSpec;
    /// `HTR2`, bits 0..=25.
    pub const HTR2: &FieldSpec = &super::REGISTERS[27].fields[0];
}

/// The fields of `LTR3`.
pub mod ltr3 {
    use super::FieldSpec;
    /// `LTR3`, bits 0..=25.
    pub const LTR3: &FieldSpec = &super::REGISTERS[28].fields[0];
}

/// The fields of `HTR3`.
pub mod htr3 {
    use super::FieldSpec;
    /// `HTR3`, bits 0..=25.
    pub const HTR3: &FieldSpec = &super::REGISTERS[29].fields[0];
}

/// The fields of `DIFSEL`.
pub mod difsel {
    use super::FieldSpec;
    /// `DIFSEL`, bits 0..=19.
    pub const DIFSEL: &FieldSpec = &super::REGISTERS[30].fields[0];
}

/// The fields of `CALFACT`.
pub mod calfact {
    use super::FieldSpec;
    /// `CALFACT_S`, bits 0..=10.
    pub const CALFACT_S: &FieldSpec = &super::REGISTERS[31].fields[0];
    /// `CALFACT_D`, bits 16..=26.
    pub const CALFACT_D: &FieldSpec = &super::REGISTERS[31].fields[1];
}

/// The fields of `CALFACT2`.
pub mod calfact2 {
    use super::FieldSpec;
    /// `LINCALFACT`, bits 0..=29.
    pub const LINCALFACT: &FieldSpec = &super::REGISTERS[32].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 33] = [
    RegisterSpec { name: "ISR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADRDY", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOSMP", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOC", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOS", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOC", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOS", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD2", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD3", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQOVF", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IER", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADRDYIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOSMPIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOCIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EOSIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOCIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEOSIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1IE", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD2IE", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD3IE", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQOVFIE", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ADEN", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADDIS", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADSTART", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JADSTART", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADSTP", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JADSTP", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "BOOST", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCALLIN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW1", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW2", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW3", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW4", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW5", bit: 26, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LINCALRDYW6", bit: 27, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADVREGEN", bit: 28, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DEEPPWD", bit: 29, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCALDIF", bit: 30, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ADCAL", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DMNGT", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RES", bit: 2, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTSEL", bit: 5, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "EXTEN", bit: 10, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRMOD", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CONT", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AUTDLY", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DISCEN", bit: 16, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DISCNUM", bit: 17, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JDISCEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQM", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1SGL", bit: 22, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWD1EN", bit: 23, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JAWD1EN", bit: 24, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JAUTO", bit: 25, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "AWDCH1CH", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JQDIS", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CFGR2", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ROVSE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JOVSE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVSS", bit: 5, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TROVS", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "ROVSM", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSHIFT1", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSHIFT2", bit: 12, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSHIFT3", bit: 13, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RSHIFT4", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OSR", bit: 16, width: 10, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "LSHIFT", bit: 28, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMPR1", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMP1", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP2", bit: 6, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP3", bit: 9, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP4", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP5", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP6", bit: 18, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP7", bit: 21, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP8", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP9", bit: 27, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SMPR2", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SMP10", bit: 0, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP11", bit: 3, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP12", bit: 6, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP13", bit: 9, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP14", bit: 12, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP15", bit: 15, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP16", bit: 18, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP17", bit: 21, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP18", bit: 24, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SMP19", bit: 27, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "PCSEL", offset: 0x1C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PCSEL", bit: 0, width: 20, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LTR1", offset: 0x20, width: Width::W32, reset: 0x0FFF_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LTR1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LHTR1", offset: 0x24, width: Width::W32, reset: 0x0FFF_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LHTR1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR1", offset: 0x30, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "L3", bit: 0, width: 4, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ1", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ2", bit: 12, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ3", bit: 18, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ4", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR2", offset: 0x34, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ5", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ6", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ7", bit: 12, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ8", bit: 18, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ9", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR3", offset: 0x38, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ10", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ11", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ12", bit: 12, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ13", bit: 18, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ14", bit: 24, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SQR4", offset: 0x3C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SQ15", bit: 0, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SQ16", bit: 6, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR", offset: 0x40, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RDATA", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JSQR", offset: 0x4C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JL", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTSEL", bit: 2, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JEXTEN", bit: 7, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ1", bit: 9, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ2", bit: 15, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ3", bit: 21, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "JSQ4", bit: 27, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OFR1", offset: 0x60, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OFFSET1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET1_CH", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSATE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OFR2", offset: 0x64, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OFFSET1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET1_CH", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSATE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OFR3", offset: 0x68, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OFFSET1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET1_CH", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSATE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "OFR4", offset: 0x6C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "OFFSET1", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OFFSET1_CH", bit: 26, width: 5, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SSATE", bit: 31, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR1", offset: 0x80, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA1", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR2", offset: 0x84, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA2", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR3", offset: 0x88, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA3", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "JDR4", offset: 0x8C, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "JDATA4", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AWD2CR", offset: 0xA0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWD2CH", bit: 0, width: 20, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "AWD3CR", offset: 0xA4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "AWD3CH", bit: 1, width: 20, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LTR2", offset: 0xB0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LTR2", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HTR2", offset: 0xB4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTR2", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "LTR3", offset: 0xB8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LTR3", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "HTR3", offset: 0xBC, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "HTR3", bit: 0, width: 26, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIFSEL", offset: 0xC0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DIFSEL", bit: 0, width: 20, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CALFACT", offset: 0xC4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "CALFACT_S", bit: 0, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CALFACT_D", bit: 16, width: 11, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CALFACT2", offset: 0xC8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "LINCALFACT", bit: 0, width: 30, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
];