rigless 0.3.0

Virtual hardware-in-the-loop runtime: run unmodified firmware on an emulated MCU with every peripheral, chip model and unit of virtual time in Rust, and a CPU core of its own that translates the firmware's instructions to host code
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315

// rigless svd from STM32H743.svd, sha256 28dd22d7923a16c1167bda9cfe6cb20cc9e98d44095dd930fd987029a839af58. Do not edit.
// Copyright (c) 2025 STMicroelectronics.
// SPDX-License-Identifier: Apache-2.0
//! Registers of `SPDIFRX` and the instances derived from it.

use rigless::soc::{Access, FieldSpec, Layout, ReadAction, RegisterSpec, Width, WriteModify};

/// The registers by name, where a variant's index is its row in [`REGISTERS`].
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum Register {
    /// `CR` at offset `0x0`, resets to `0x0000_0000`, read-write.
    Cr = 0,
    /// `IMR` at offset `0x4`, resets to `0x0000_0000`, read-write.
    Imr = 1,
    /// `SR` at offset `0x8`, resets to `0x0000_0000`, read-only.
    Sr = 2,
    /// `IFCR` at offset `0xC`, resets to `0x0000_0000`, write-only.
    Ifcr = 3,
    /// `DR_00` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Dr00 = 4,
    /// `DR_01` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Dr01 = 5,
    /// `DR_10` at offset `0x10`, resets to `0x0000_0000`, read-only.
    Dr10 = 6,
    /// `CSR` at offset `0x14`, resets to `0x0000_0000`, read-only.
    Csr = 7,
    /// `DIR` at offset `0x18`, resets to `0x0000_0000`, read-only.
    Dir = 8,
    /// `VERR` at offset `0x3F4`, resets to `0x0000_0012`, read-only.
    Verr = 9,
    /// `IDR` at offset `0x3F8`, resets to `0x0013_0041`, read-only.
    Idr = 10,
    /// `SIDR` at offset `0x3FC`, resets to `0xA3C5_DD01`, read-only.
    Sidr = 11,
}

impl Register {
    /// Every register, in table order.
    pub const ALL: [Self; 12] = [Self::Cr, Self::Imr, Self::Sr, Self::Ifcr, Self::Dr00, Self::Dr01, Self::Dr10, Self::Csr, Self::Dir, Self::Verr, Self::Idr, Self::Sidr];
}

impl Layout for Register {
    const REGISTERS: &'static [RegisterSpec] = &REGISTERS;
    fn from_index(index: usize) -> Option<Self> {
        Self::ALL.get(index).copied()
    }
    fn index(self) -> usize {
        self as usize
    }
}

/// The fields of `CR`.
pub mod cr {
    use super::FieldSpec;
    /// `SPDIFRXEN`, bits 0..=1.
    pub const SPDIFRXEN: &FieldSpec = &super::REGISTERS[0].fields[0];
    /// `RXDMAEN`, bit 2.
    pub const RXDMAEN: &FieldSpec = &super::REGISTERS[0].fields[1];
    /// `RXSTEO`, bit 3.
    pub const RXSTEO: &FieldSpec = &super::REGISTERS[0].fields[2];
    /// `DRFMT`, bits 4..=5.
    pub const DRFMT: &FieldSpec = &super::REGISTERS[0].fields[3];
    /// `PMSK`, bit 6.
    pub const PMSK: &FieldSpec = &super::REGISTERS[0].fields[4];
    /// `VMSK`, bit 7.
    pub const VMSK: &FieldSpec = &super::REGISTERS[0].fields[5];
    /// `CUMSK`, bit 8.
    pub const CUMSK: &FieldSpec = &super::REGISTERS[0].fields[6];
    /// `PTMSK`, bit 9.
    pub const PTMSK: &FieldSpec = &super::REGISTERS[0].fields[7];
    /// `CBDMAEN`, bit 10.
    pub const CBDMAEN: &FieldSpec = &super::REGISTERS[0].fields[8];
    /// `CHSEL`, bit 11.
    pub const CHSEL: &FieldSpec = &super::REGISTERS[0].fields[9];
    /// `NBTR`, bits 12..=13.
    pub const NBTR: &FieldSpec = &super::REGISTERS[0].fields[10];
    /// `WFA`, bit 14.
    pub const WFA: &FieldSpec = &super::REGISTERS[0].fields[11];
    /// `INSEL`, bits 16..=18.
    pub const INSEL: &FieldSpec = &super::REGISTERS[0].fields[12];
    /// `CKSEN`, bit 20.
    pub const CKSEN: &FieldSpec = &super::REGISTERS[0].fields[13];
    /// `CKSBKPEN`, bit 21.
    pub const CKSBKPEN: &FieldSpec = &super::REGISTERS[0].fields[14];
}

/// The fields of `IMR`.
pub mod imr {
    use super::FieldSpec;
    /// `RXNEIE`, bit 0.
    pub const RXNEIE: &FieldSpec = &super::REGISTERS[1].fields[0];
    /// `CSRNEIE`, bit 1.
    pub const CSRNEIE: &FieldSpec = &super::REGISTERS[1].fields[1];
    /// `PERRIE`, bit 2.
    pub const PERRIE: &FieldSpec = &super::REGISTERS[1].fields[2];
    /// `OVRIE`, bit 3.
    pub const OVRIE: &FieldSpec = &super::REGISTERS[1].fields[3];
    /// `SBLKIE`, bit 4.
    pub const SBLKIE: &FieldSpec = &super::REGISTERS[1].fields[4];
    /// `SYNCDIE`, bit 5.
    pub const SYNCDIE: &FieldSpec = &super::REGISTERS[1].fields[5];
    /// `IFEIE`, bit 6.
    pub const IFEIE: &FieldSpec = &super::REGISTERS[1].fields[6];
}

/// The fields of `SR`.
pub mod sr {
    use super::FieldSpec;
    /// `RXNE`, bit 0.
    pub const RXNE: &FieldSpec = &super::REGISTERS[2].fields[0];
    /// `CSRNE`, bit 1.
    pub const CSRNE: &FieldSpec = &super::REGISTERS[2].fields[1];
    /// `PERR`, bit 2.
    pub const PERR: &FieldSpec = &super::REGISTERS[2].fields[2];
    /// `OVR`, bit 3.
    pub const OVR: &FieldSpec = &super::REGISTERS[2].fields[3];
    /// `SBD`, bit 4.
    pub const SBD: &FieldSpec = &super::REGISTERS[2].fields[4];
    /// `SYNCD`, bit 5.
    pub const SYNCD: &FieldSpec = &super::REGISTERS[2].fields[5];
    /// `FERR`, bit 6.
    pub const FERR: &FieldSpec = &super::REGISTERS[2].fields[6];
    /// `SERR`, bit 7.
    pub const SERR: &FieldSpec = &super::REGISTERS[2].fields[7];
    /// `TERR`, bit 8.
    pub const TERR: &FieldSpec = &super::REGISTERS[2].fields[8];
    /// `WIDTH5`, bits 16..=30.
    pub const WIDTH5: &FieldSpec = &super::REGISTERS[2].fields[9];
}

/// The fields of `IFCR`.
pub mod ifcr {
    use super::FieldSpec;
    /// `PERRCF`, bit 2.
    pub const PERRCF: &FieldSpec = &super::REGISTERS[3].fields[0];
    /// `OVRCF`, bit 3.
    pub const OVRCF: &FieldSpec = &super::REGISTERS[3].fields[1];
    /// `SBDCF`, bit 4.
    pub const SBDCF: &FieldSpec = &super::REGISTERS[3].fields[2];
    /// `SYNCDCF`, bit 5.
    pub const SYNCDCF: &FieldSpec = &super::REGISTERS[3].fields[3];
}

/// The fields of `DR_00`.
pub mod dr_00 {
    use super::FieldSpec;
    /// `DR`, bits 0..=23.
    pub const DR: &FieldSpec = &super::REGISTERS[4].fields[0];
    /// `PE`, bit 24.
    pub const PE: &FieldSpec = &super::REGISTERS[4].fields[1];
    /// `V`, bit 25.
    pub const V: &FieldSpec = &super::REGISTERS[4].fields[2];
    /// `U`, bit 26.
    pub const U: &FieldSpec = &super::REGISTERS[4].fields[3];
    /// `C`, bit 27.
    pub const C: &FieldSpec = &super::REGISTERS[4].fields[4];
    /// `PT`, bits 28..=29.
    pub const PT: &FieldSpec = &super::REGISTERS[4].fields[5];
}

/// The fields of `DR_01`.
pub mod dr_01 {
    use super::FieldSpec;
    /// `PE`, bit 0.
    pub const PE: &FieldSpec = &super::REGISTERS[5].fields[0];
    /// `V`, bit 1.
    pub const V: &FieldSpec = &super::REGISTERS[5].fields[1];
    /// `U`, bit 2.
    pub const U: &FieldSpec = &super::REGISTERS[5].fields[2];
    /// `C`, bit 3.
    pub const C: &FieldSpec = &super::REGISTERS[5].fields[3];
    /// `PT`, bits 4..=5.
    pub const PT: &FieldSpec = &super::REGISTERS[5].fields[4];
    /// `DR`, bits 8..=31.
    pub const DR: &FieldSpec = &super::REGISTERS[5].fields[5];
}

/// The fields of `DR_10`.
pub mod dr_10 {
    use super::FieldSpec;
    /// `DRNL1`, bits 0..=15.
    pub const DRNL1: &FieldSpec = &super::REGISTERS[6].fields[0];
    /// `DRNL2`, bits 16..=31.
    pub const DRNL2: &FieldSpec = &super::REGISTERS[6].fields[1];
}

/// The fields of `CSR`.
pub mod csr {
    use super::FieldSpec;
    /// `USR`, bits 0..=15.
    pub const USR: &FieldSpec = &super::REGISTERS[7].fields[0];
    /// `CS`, bits 16..=23.
    pub const CS: &FieldSpec = &super::REGISTERS[7].fields[1];
    /// `SOB`, bit 24.
    pub const SOB: &FieldSpec = &super::REGISTERS[7].fields[2];
}

/// The fields of `DIR`.
pub mod dir {
    use super::FieldSpec;
    /// `THI`, bits 0..=12.
    pub const THI: &FieldSpec = &super::REGISTERS[8].fields[0];
    /// `TLO`, bits 16..=28.
    pub const TLO: &FieldSpec = &super::REGISTERS[8].fields[1];
}

/// The fields of `VERR`.
pub mod verr {
    use super::FieldSpec;
    /// `MINREV`, bits 0..=3.
    pub const MINREV: &FieldSpec = &super::REGISTERS[9].fields[0];
    /// `MAJREV`, bits 4..=7.
    pub const MAJREV: &FieldSpec = &super::REGISTERS[9].fields[1];
}

/// The fields of `IDR`.
pub mod idr {
    use super::FieldSpec;
    /// `ID`, bits 0..=31.
    pub const ID: &FieldSpec = &super::REGISTERS[10].fields[0];
}

/// The fields of `SIDR`.
pub mod sidr {
    use super::FieldSpec;
    /// `SID`, bits 0..=31.
    pub const SID: &FieldSpec = &super::REGISTERS[11].fields[0];
}

/// The register table.
pub static REGISTERS: [RegisterSpec; 12] = [
    RegisterSpec { name: "CR", offset: 0x0, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SPDIFRXEN", bit: 0, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXDMAEN", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "RXSTEO", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRFMT", bit: 4, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PMSK", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "VMSK", bit: 7, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CUMSK", bit: 8, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PTMSK", bit: 9, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CBDMAEN", bit: 10, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CHSEL", bit: 11, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "NBTR", bit: 12, width: 2, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WFA", bit: 14, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "INSEL", bit: 16, width: 3, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSEN", bit: 20, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CKSBKPEN", bit: 21, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IMR", offset: 0x4, width: Width::W32, reset: 0x0000_0000, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXNEIE", bit: 0, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSRNEIE", bit: 1, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PERRIE", bit: 2, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRIE", bit: 3, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBLKIE", bit: 4, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCDIE", bit: 5, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "IFEIE", bit: 6, width: 1, access: Access::ReadWrite, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SR", offset: 0x8, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "RXNE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CSRNE", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PERR", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVR", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBD", bit: 4, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCD", bit: 5, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "FERR", bit: 6, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SERR", bit: 7, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TERR", bit: 8, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "WIDTH5", bit: 16, width: 15, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IFCR", offset: 0xC, width: Width::W32, reset: 0x0000_0000, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PERRCF", bit: 2, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "OVRCF", bit: 3, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SBDCF", bit: 4, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SYNCDCF", bit: 5, width: 1, access: Access::WriteOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR_00", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DR", bit: 0, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PE", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "V", bit: 25, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "U", bit: 26, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C", bit: 27, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PT", bit: 28, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR_01", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "PE", bit: 0, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "V", bit: 1, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "U", bit: 2, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "C", bit: 3, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "PT", bit: 4, width: 2, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DR", bit: 8, width: 24, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DR_10", offset: 0x10, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "DRNL1", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "DRNL2", bit: 16, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "CSR", offset: 0x14, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "USR", bit: 0, width: 16, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "CS", bit: 16, width: 8, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "SOB", bit: 24, width: 1, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "DIR", offset: 0x18, width: Width::W32, reset: 0x0000_0000, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "THI", bit: 0, width: 13, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "TLO", bit: 16, width: 13, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "VERR", offset: 0x3F4, width: Width::W32, reset: 0x0000_0012, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "MINREV", bit: 0, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
        FieldSpec { name: "MAJREV", bit: 4, width: 4, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "IDR", offset: 0x3F8, width: Width::W32, reset: 0x0013_0041, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "ID", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
    RegisterSpec { name: "SIDR", offset: 0x3FC, width: Width::W32, reset: 0xA3C5_DD01, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None, fields: &[
        FieldSpec { name: "SID", bit: 0, width: 32, access: Access::ReadOnly, read: ReadAction::None, write: WriteModify::None },
    ] },
];